Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	302182340	102058	0	0
ctrl_regwen_rd_A	302182340	5720	0	0
exec_rd_A	302182340	4751	0	0
exec_regwen_rd_A	302182340	5472	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302182340	102058	0	0
T7	23512	0	0	0
T8	66585	0	0	0
T31	30709	735	0	0
T32	302644	2347	0	0
T33	0	4216	0	0
T42	0	2820	0	0
T52	0	793	0	0
T53	0	2565	0	0
T54	0	2852	0	0
T55	0	6779	0	0
T56	0	3552	0	0
T57	0	819	0	0
T58	129102	0	0	0
T59	205642	0	0	0
T60	180554	0	0	0
T61	237819	0	0	0
T62	31842	0	0	0
T63	34598	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302182340	5720	0	0
T53	108256	484	0	0
T54	0	345	0	0
T88	7152	0	0	0
T116	0	383	0	0
T117	0	857	0	0
T118	0	241	0	0
T119	0	379	0	0
T120	0	165	0	0
T121	0	158	0	0
T122	0	469	0	0
T123	0	533	0	0
T124	1097	0	0	0
T125	3742	0	0	0
T126	125032	0	0	0
T127	2458	0	0	0
T128	352163	0	0	0
T129	12228	0	0	0
T130	25178	0	0	0
T131	201080	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302182340	4751	0	0
T53	108256	384	0	0
T54	0	230	0	0
T88	7152	0	0	0
T116	0	249	0	0
T117	0	720	0	0
T118	0	122	0	0
T119	0	456	0	0
T120	0	115	0	0
T121	0	99	0	0
T122	0	382	0	0
T123	0	498	0	0
T124	1097	0	0	0
T125	3742	0	0	0
T126	125032	0	0	0
T127	2458	0	0	0
T128	352163	0	0	0
T129	12228	0	0	0
T130	25178	0	0	0
T131	201080	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302182340	5472	0	0
T53	108256	492	0	0
T54	0	332	0	0
T88	7152	0	0	0
T116	0	338	0	0
T117	0	716	0	0
T118	0	206	0	0
T119	0	493	0	0
T120	0	127	0	0
T121	0	124	0	0
T122	0	502	0	0
T123	0	591	0	0
T124	1097	0	0	0
T125	3742	0	0	0
T126	125032	0	0	0
T127	2458	0	0	0
T128	352163	0	0	0
T129	12228	0	0	0
T130	25178	0	0	0
T131	201080	0	0	0