| T800 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.2824964028 |
|
|
Apr 25 01:28:09 PM PDT 24 |
Apr 25 01:33:11 PM PDT 24 |
3343770734 ps |
| T801 |
/workspace/coverage/default/19.sram_ctrl_stress_all.1130676999 |
|
|
Apr 25 01:26:33 PM PDT 24 |
Apr 25 01:54:08 PM PDT 24 |
20721659546 ps |
| T802 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2199244507 |
|
|
Apr 25 01:31:04 PM PDT 24 |
Apr 25 01:40:05 PM PDT 24 |
32307124000 ps |
| T803 |
/workspace/coverage/default/26.sram_ctrl_partial_access.1770453599 |
|
|
Apr 25 01:27:34 PM PDT 24 |
Apr 25 01:27:41 PM PDT 24 |
309732968 ps |
| T804 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.951895262 |
|
|
Apr 25 01:22:14 PM PDT 24 |
Apr 25 01:23:22 PM PDT 24 |
127514098 ps |
| T805 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2103780184 |
|
|
Apr 25 01:31:55 PM PDT 24 |
Apr 25 01:32:08 PM PDT 24 |
877800407 ps |
| T806 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2680361228 |
|
|
Apr 25 01:25:14 PM PDT 24 |
Apr 25 01:30:25 PM PDT 24 |
15107790742 ps |
| T807 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1715869305 |
|
|
Apr 25 01:27:26 PM PDT 24 |
Apr 25 01:37:27 PM PDT 24 |
3358360733 ps |
| T808 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.234485214 |
|
|
Apr 25 01:23:13 PM PDT 24 |
Apr 25 01:23:20 PM PDT 24 |
2556633864 ps |
| T809 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.895315267 |
|
|
Apr 25 01:32:25 PM PDT 24 |
Apr 25 01:32:35 PM PDT 24 |
2172668571 ps |
| T810 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3755821287 |
|
|
Apr 25 01:27:54 PM PDT 24 |
Apr 25 01:28:00 PM PDT 24 |
1045798241 ps |
| T811 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.968087181 |
|
|
Apr 25 01:26:17 PM PDT 24 |
Apr 25 01:26:24 PM PDT 24 |
3150404866 ps |
| T812 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3692156570 |
|
|
Apr 25 01:28:23 PM PDT 24 |
Apr 25 01:28:28 PM PDT 24 |
1836701350 ps |
| T813 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3657528152 |
|
|
Apr 25 01:31:49 PM PDT 24 |
Apr 25 01:36:12 PM PDT 24 |
1086688878 ps |
| T814 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2657398041 |
|
|
Apr 25 01:26:32 PM PDT 24 |
Apr 25 01:27:08 PM PDT 24 |
848074784 ps |
| T815 |
/workspace/coverage/default/33.sram_ctrl_partial_access.4229991976 |
|
|
Apr 25 01:28:57 PM PDT 24 |
Apr 25 01:29:08 PM PDT 24 |
384577199 ps |
| T816 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2210335222 |
|
|
Apr 25 01:29:43 PM PDT 24 |
Apr 25 01:29:46 PM PDT 24 |
360043694 ps |
| T817 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1580207130 |
|
|
Apr 25 01:27:42 PM PDT 24 |
Apr 25 01:41:57 PM PDT 24 |
4457815801 ps |
| T818 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.4158027707 |
|
|
Apr 25 01:27:28 PM PDT 24 |
Apr 25 01:27:29 PM PDT 24 |
127457877 ps |
| T819 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.183556840 |
|
|
Apr 25 01:31:39 PM PDT 24 |
Apr 25 01:31:43 PM PDT 24 |
97798063 ps |
| T820 |
/workspace/coverage/default/34.sram_ctrl_alert_test.2999025051 |
|
|
Apr 25 01:29:11 PM PDT 24 |
Apr 25 01:29:12 PM PDT 24 |
24123225 ps |
| T821 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.10264988 |
|
|
Apr 25 01:23:34 PM PDT 24 |
Apr 25 01:24:43 PM PDT 24 |
11122113380 ps |
| T822 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1413536831 |
|
|
Apr 25 01:24:01 PM PDT 24 |
Apr 25 01:41:49 PM PDT 24 |
49762496963 ps |
| T823 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.2118326793 |
|
|
Apr 25 01:27:07 PM PDT 24 |
Apr 25 01:27:16 PM PDT 24 |
148823952 ps |
| T824 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.776372428 |
|
|
Apr 25 01:22:48 PM PDT 24 |
Apr 25 01:40:39 PM PDT 24 |
3725477427 ps |
| T825 |
/workspace/coverage/default/49.sram_ctrl_alert_test.1701045619 |
|
|
Apr 25 01:32:25 PM PDT 24 |
Apr 25 01:32:26 PM PDT 24 |
78621272 ps |
| T826 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.2944758891 |
|
|
Apr 25 01:27:11 PM PDT 24 |
Apr 25 01:29:39 PM PDT 24 |
1536218848 ps |
| T91 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1029082016 |
|
|
Apr 25 01:31:13 PM PDT 24 |
Apr 25 01:31:19 PM PDT 24 |
351886853 ps |
| T827 |
/workspace/coverage/default/2.sram_ctrl_partial_access.4210315534 |
|
|
Apr 25 01:22:45 PM PDT 24 |
Apr 25 01:22:55 PM PDT 24 |
398180032 ps |
| T828 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.4182446045 |
|
|
Apr 25 01:27:45 PM PDT 24 |
Apr 25 01:36:34 PM PDT 24 |
20826589571 ps |
| T829 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.708443958 |
|
|
Apr 25 01:26:24 PM PDT 24 |
Apr 25 01:35:14 PM PDT 24 |
21521079285 ps |
| T830 |
/workspace/coverage/default/2.sram_ctrl_smoke.3390186027 |
|
|
Apr 25 01:22:43 PM PDT 24 |
Apr 25 01:24:26 PM PDT 24 |
703510969 ps |
| T831 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3335973936 |
|
|
Apr 25 01:27:09 PM PDT 24 |
Apr 25 01:27:16 PM PDT 24 |
757665979 ps |
| T832 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3824172176 |
|
|
Apr 25 01:26:28 PM PDT 24 |
Apr 25 01:30:56 PM PDT 24 |
14837799412 ps |
| T833 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.236194629 |
|
|
Apr 25 01:23:49 PM PDT 24 |
Apr 25 01:24:51 PM PDT 24 |
138778666 ps |
| T834 |
/workspace/coverage/default/31.sram_ctrl_alert_test.1263342472 |
|
|
Apr 25 01:28:45 PM PDT 24 |
Apr 25 01:28:46 PM PDT 24 |
12392408 ps |
| T835 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.4002678017 |
|
|
Apr 25 01:27:34 PM PDT 24 |
Apr 25 01:27:37 PM PDT 24 |
153735070 ps |
| T836 |
/workspace/coverage/default/17.sram_ctrl_regwen.1093643462 |
|
|
Apr 25 01:26:16 PM PDT 24 |
Apr 25 01:37:08 PM PDT 24 |
5519182017 ps |
| T837 |
/workspace/coverage/default/18.sram_ctrl_smoke.3833708439 |
|
|
Apr 25 01:26:21 PM PDT 24 |
Apr 25 01:26:35 PM PDT 24 |
813841509 ps |
| T838 |
/workspace/coverage/default/27.sram_ctrl_smoke.1477681998 |
|
|
Apr 25 01:27:40 PM PDT 24 |
Apr 25 01:27:46 PM PDT 24 |
201208816 ps |
| T839 |
/workspace/coverage/default/44.sram_ctrl_regwen.4106735924 |
|
|
Apr 25 01:31:18 PM PDT 24 |
Apr 25 01:40:37 PM PDT 24 |
2006961940 ps |
| T840 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3945929074 |
|
|
Apr 25 01:28:43 PM PDT 24 |
Apr 25 01:34:03 PM PDT 24 |
138867697960 ps |
| T841 |
/workspace/coverage/default/12.sram_ctrl_bijection.1602392245 |
|
|
Apr 25 01:24:52 PM PDT 24 |
Apr 25 01:25:12 PM PDT 24 |
1508938148 ps |
| T842 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3499811373 |
|
|
Apr 25 01:31:25 PM PDT 24 |
Apr 25 01:35:28 PM PDT 24 |
23701734668 ps |
| T843 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3985375394 |
|
|
Apr 25 01:24:23 PM PDT 24 |
Apr 25 01:24:25 PM PDT 24 |
177038588 ps |
| T844 |
/workspace/coverage/default/1.sram_ctrl_executable.2743454218 |
|
|
Apr 25 01:22:25 PM PDT 24 |
Apr 25 01:35:49 PM PDT 24 |
12525139041 ps |
| T845 |
/workspace/coverage/default/26.sram_ctrl_bijection.259797196 |
|
|
Apr 25 01:27:39 PM PDT 24 |
Apr 25 01:28:04 PM PDT 24 |
535613150 ps |
| T846 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.809525356 |
|
|
Apr 25 01:24:19 PM PDT 24 |
Apr 25 01:38:51 PM PDT 24 |
9864562949 ps |
| T847 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.908668969 |
|
|
Apr 25 01:26:25 PM PDT 24 |
Apr 25 01:27:08 PM PDT 24 |
2389000481 ps |
| T848 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.904919786 |
|
|
Apr 25 01:30:59 PM PDT 24 |
Apr 25 01:36:23 PM PDT 24 |
4785309177 ps |
| T849 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3440191526 |
|
|
Apr 25 01:26:32 PM PDT 24 |
Apr 25 01:26:38 PM PDT 24 |
308193620 ps |
| T850 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.309325526 |
|
|
Apr 25 01:26:17 PM PDT 24 |
Apr 25 01:38:07 PM PDT 24 |
12802337495 ps |
| T851 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1268015531 |
|
|
Apr 25 01:22:25 PM PDT 24 |
Apr 25 01:22:30 PM PDT 24 |
53843095 ps |
| T852 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1025113204 |
|
|
Apr 25 01:28:25 PM PDT 24 |
Apr 25 01:33:37 PM PDT 24 |
10518711760 ps |
| T853 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.298720679 |
|
|
Apr 25 01:28:16 PM PDT 24 |
Apr 25 01:32:50 PM PDT 24 |
6085307946 ps |
| T854 |
/workspace/coverage/default/4.sram_ctrl_smoke.2208467980 |
|
|
Apr 25 01:23:07 PM PDT 24 |
Apr 25 01:23:19 PM PDT 24 |
1117801064 ps |
| T855 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3901687180 |
|
|
Apr 25 01:23:19 PM PDT 24 |
Apr 25 01:23:21 PM PDT 24 |
30903564 ps |
| T856 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1721134229 |
|
|
Apr 25 01:31:54 PM PDT 24 |
Apr 25 02:47:05 PM PDT 24 |
13747490604 ps |
| T857 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.3121090540 |
|
|
Apr 25 01:23:43 PM PDT 24 |
Apr 25 01:23:52 PM PDT 24 |
451698796 ps |
| T858 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2601070649 |
|
|
Apr 25 01:24:18 PM PDT 24 |
Apr 25 01:24:23 PM PDT 24 |
187139342 ps |
| T859 |
/workspace/coverage/default/37.sram_ctrl_regwen.4258492191 |
|
|
Apr 25 01:29:50 PM PDT 24 |
Apr 25 01:41:17 PM PDT 24 |
11754182600 ps |
| T860 |
/workspace/coverage/default/39.sram_ctrl_alert_test.184555241 |
|
|
Apr 25 01:30:17 PM PDT 24 |
Apr 25 01:30:18 PM PDT 24 |
143242718 ps |
| T861 |
/workspace/coverage/default/28.sram_ctrl_regwen.478663664 |
|
|
Apr 25 01:28:04 PM PDT 24 |
Apr 25 01:34:42 PM PDT 24 |
7544476316 ps |
| T862 |
/workspace/coverage/default/11.sram_ctrl_smoke.2428599183 |
|
|
Apr 25 01:24:33 PM PDT 24 |
Apr 25 01:24:37 PM PDT 24 |
45409392 ps |
| T863 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1824120335 |
|
|
Apr 25 01:29:03 PM PDT 24 |
Apr 25 01:29:09 PM PDT 24 |
675336467 ps |
| T864 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.1622769346 |
|
|
Apr 25 01:28:23 PM PDT 24 |
Apr 25 01:28:28 PM PDT 24 |
76267393 ps |
| T865 |
/workspace/coverage/default/18.sram_ctrl_stress_all.2207090050 |
|
|
Apr 25 01:26:25 PM PDT 24 |
Apr 25 02:04:20 PM PDT 24 |
6976388048 ps |
| T866 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3961910248 |
|
|
Apr 25 01:26:19 PM PDT 24 |
Apr 25 01:28:52 PM PDT 24 |
1751344222 ps |
| T867 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.143319290 |
|
|
Apr 25 01:26:43 PM PDT 24 |
Apr 25 01:28:22 PM PDT 24 |
159481551 ps |
| T868 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1120151535 |
|
|
Apr 25 01:26:20 PM PDT 24 |
Apr 25 01:27:30 PM PDT 24 |
3837861773 ps |
| T869 |
/workspace/coverage/default/2.sram_ctrl_executable.2294105617 |
|
|
Apr 25 01:22:47 PM PDT 24 |
Apr 25 01:33:29 PM PDT 24 |
3241392574 ps |
| T870 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1320608070 |
|
|
Apr 25 01:25:33 PM PDT 24 |
Apr 25 01:25:35 PM PDT 24 |
78770904 ps |
| T871 |
/workspace/coverage/default/46.sram_ctrl_smoke.2258824812 |
|
|
Apr 25 01:31:38 PM PDT 24 |
Apr 25 01:31:44 PM PDT 24 |
590289242 ps |
| T872 |
/workspace/coverage/default/31.sram_ctrl_smoke.1997709599 |
|
|
Apr 25 01:28:30 PM PDT 24 |
Apr 25 01:29:22 PM PDT 24 |
1778587364 ps |
| T873 |
/workspace/coverage/default/26.sram_ctrl_smoke.3439727371 |
|
|
Apr 25 01:27:34 PM PDT 24 |
Apr 25 01:27:50 PM PDT 24 |
1091022736 ps |
| T874 |
/workspace/coverage/default/29.sram_ctrl_stress_all.46433506 |
|
|
Apr 25 01:28:17 PM PDT 24 |
Apr 25 01:43:08 PM PDT 24 |
33396155462 ps |
| T875 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.4019025773 |
|
|
Apr 25 01:27:53 PM PDT 24 |
Apr 25 01:35:21 PM PDT 24 |
16350982068 ps |
| T876 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4013389063 |
|
|
Apr 25 01:24:42 PM PDT 24 |
Apr 25 01:30:38 PM PDT 24 |
50731209609 ps |
| T877 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.4059919120 |
|
|
Apr 25 01:26:31 PM PDT 24 |
Apr 25 01:30:58 PM PDT 24 |
11873009272 ps |
| T878 |
/workspace/coverage/default/36.sram_ctrl_stress_all.2616293830 |
|
|
Apr 25 01:29:43 PM PDT 24 |
Apr 25 01:50:59 PM PDT 24 |
24290003732 ps |
| T879 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.4246256429 |
|
|
Apr 25 01:28:40 PM PDT 24 |
Apr 25 01:33:38 PM PDT 24 |
4612896160 ps |
| T880 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2263541871 |
|
|
Apr 25 01:26:42 PM PDT 24 |
Apr 25 01:26:51 PM PDT 24 |
730966597 ps |
| T881 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1152788963 |
|
|
Apr 25 01:30:34 PM PDT 24 |
Apr 25 01:39:53 PM PDT 24 |
2624494871 ps |
| T882 |
/workspace/coverage/default/30.sram_ctrl_partial_access.1308839248 |
|
|
Apr 25 01:28:16 PM PDT 24 |
Apr 25 01:28:52 PM PDT 24 |
1963437812 ps |
| T883 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.3048823688 |
|
|
Apr 25 01:25:40 PM PDT 24 |
Apr 25 01:25:48 PM PDT 24 |
2532392879 ps |
| T884 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.669492328 |
|
|
Apr 25 01:22:55 PM PDT 24 |
Apr 25 01:23:02 PM PDT 24 |
654700089 ps |
| T885 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.2678917437 |
|
|
Apr 25 01:30:27 PM PDT 24 |
Apr 25 01:30:33 PM PDT 24 |
317659815 ps |
| T886 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3374052133 |
|
|
Apr 25 01:28:03 PM PDT 24 |
Apr 25 01:30:34 PM PDT 24 |
485566575 ps |
| T887 |
/workspace/coverage/default/36.sram_ctrl_smoke.2191340096 |
|
|
Apr 25 01:29:30 PM PDT 24 |
Apr 25 01:29:35 PM PDT 24 |
294576496 ps |
| T888 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2252997289 |
|
|
Apr 25 01:27:12 PM PDT 24 |
Apr 25 01:27:28 PM PDT 24 |
5229991990 ps |
| T889 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1292722183 |
|
|
Apr 25 01:23:39 PM PDT 24 |
Apr 25 01:24:00 PM PDT 24 |
470670539 ps |
| T890 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1959140070 |
|
|
Apr 25 01:23:44 PM PDT 24 |
Apr 25 01:23:46 PM PDT 24 |
30726712 ps |
| T38 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2966358566 |
|
|
Apr 25 01:22:53 PM PDT 24 |
Apr 25 01:22:59 PM PDT 24 |
1255012612 ps |
| T891 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2036494737 |
|
|
Apr 25 01:22:07 PM PDT 24 |
Apr 25 01:32:21 PM PDT 24 |
68962508235 ps |
| T892 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3883236942 |
|
|
Apr 25 01:25:04 PM PDT 24 |
Apr 25 01:26:31 PM PDT 24 |
591443362 ps |
| T893 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3391583153 |
|
|
Apr 25 01:32:14 PM PDT 24 |
Apr 25 01:38:28 PM PDT 24 |
7242185779 ps |
| T894 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2531486357 |
|
|
Apr 25 01:24:04 PM PDT 24 |
Apr 25 01:24:06 PM PDT 24 |
55055706 ps |
| T895 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1731994956 |
|
|
Apr 25 01:22:59 PM PDT 24 |
Apr 25 01:34:27 PM PDT 24 |
2610895887 ps |
| T896 |
/workspace/coverage/default/49.sram_ctrl_smoke.2117615280 |
|
|
Apr 25 01:32:12 PM PDT 24 |
Apr 25 01:32:17 PM PDT 24 |
885883582 ps |
| T897 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2214192318 |
|
|
Apr 25 01:29:03 PM PDT 24 |
Apr 25 01:29:46 PM PDT 24 |
673061820 ps |
| T898 |
/workspace/coverage/default/34.sram_ctrl_stress_all.4019073963 |
|
|
Apr 25 01:29:09 PM PDT 24 |
Apr 25 01:47:51 PM PDT 24 |
24181659072 ps |
| T899 |
/workspace/coverage/default/12.sram_ctrl_regwen.2502969764 |
|
|
Apr 25 01:24:58 PM PDT 24 |
Apr 25 01:27:02 PM PDT 24 |
3739022283 ps |
| T900 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.2566046781 |
|
|
Apr 25 01:24:53 PM PDT 24 |
Apr 25 01:25:03 PM PDT 24 |
4410605736 ps |
| T901 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1942090673 |
|
|
Apr 25 01:23:14 PM PDT 24 |
Apr 25 01:24:27 PM PDT 24 |
4686563567 ps |
| T902 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2363658401 |
|
|
Apr 25 01:32:19 PM PDT 24 |
Apr 25 01:32:33 PM PDT 24 |
833365868 ps |
| T903 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3675106461 |
|
|
Apr 25 01:27:41 PM PDT 24 |
Apr 25 01:27:46 PM PDT 24 |
73368055 ps |
| T904 |
/workspace/coverage/default/13.sram_ctrl_executable.394332871 |
|
|
Apr 25 01:25:11 PM PDT 24 |
Apr 25 01:37:13 PM PDT 24 |
97127145495 ps |
| T905 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.519778686 |
|
|
Apr 25 01:26:27 PM PDT 24 |
Apr 25 01:31:55 PM PDT 24 |
1772779067 ps |
| T906 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1457833062 |
|
|
Apr 25 01:31:54 PM PDT 24 |
Apr 25 01:37:56 PM PDT 24 |
5141626616 ps |
| T907 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3469785088 |
|
|
Apr 25 01:24:13 PM PDT 24 |
Apr 25 01:24:17 PM PDT 24 |
99497344 ps |
| T908 |
/workspace/coverage/default/1.sram_ctrl_bijection.4080779022 |
|
|
Apr 25 01:22:20 PM PDT 24 |
Apr 25 01:22:45 PM PDT 24 |
405318684 ps |
| T909 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2555677548 |
|
|
Apr 25 01:30:33 PM PDT 24 |
Apr 25 01:31:00 PM PDT 24 |
100476268 ps |
| T910 |
/workspace/coverage/default/26.sram_ctrl_stress_all.3972959470 |
|
|
Apr 25 01:27:40 PM PDT 24 |
Apr 25 02:04:19 PM PDT 24 |
9745836315 ps |
| T911 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3859884452 |
|
|
Apr 25 01:23:46 PM PDT 24 |
Apr 25 01:23:48 PM PDT 24 |
27392344 ps |
| T912 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3974183413 |
|
|
Apr 25 01:31:41 PM PDT 24 |
Apr 25 01:35:37 PM PDT 24 |
5224972158 ps |
| T913 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1441141865 |
|
|
Apr 25 01:24:46 PM PDT 24 |
Apr 25 01:24:48 PM PDT 24 |
28086406 ps |
| T914 |
/workspace/coverage/default/48.sram_ctrl_executable.4052585512 |
|
|
Apr 25 01:32:14 PM PDT 24 |
Apr 25 01:51:50 PM PDT 24 |
16213301646 ps |
| T915 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3838407760 |
|
|
Apr 25 01:31:28 PM PDT 24 |
Apr 25 01:31:34 PM PDT 24 |
186209134 ps |
| T916 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.162989269 |
|
|
Apr 25 01:31:16 PM PDT 24 |
Apr 25 01:36:48 PM PDT 24 |
58192399707 ps |
| T917 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.242974293 |
|
|
Apr 25 01:31:14 PM PDT 24 |
Apr 25 01:32:25 PM PDT 24 |
970701733 ps |
| T918 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1724477431 |
|
|
Apr 25 01:32:09 PM PDT 24 |
Apr 25 01:34:40 PM PDT 24 |
611091568 ps |
| T919 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.4081648173 |
|
|
Apr 25 01:23:43 PM PDT 24 |
Apr 25 01:23:47 PM PDT 24 |
81598862 ps |
| T920 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.21511753 |
|
|
Apr 25 01:24:11 PM PDT 24 |
Apr 25 01:24:21 PM PDT 24 |
465278716 ps |
| T921 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3827551989 |
|
|
Apr 25 01:25:14 PM PDT 24 |
Apr 25 01:46:08 PM PDT 24 |
19145549459 ps |
| T922 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.4000209805 |
|
|
Apr 25 01:26:59 PM PDT 24 |
Apr 25 01:27:05 PM PDT 24 |
346751964 ps |
| T923 |
/workspace/coverage/default/6.sram_ctrl_regwen.52460091 |
|
|
Apr 25 01:23:43 PM PDT 24 |
Apr 25 01:24:44 PM PDT 24 |
2044129299 ps |
| T924 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1042620468 |
|
|
Apr 25 01:31:36 PM PDT 24 |
Apr 25 01:32:00 PM PDT 24 |
1977985010 ps |
| T925 |
/workspace/coverage/default/36.sram_ctrl_alert_test.2195435728 |
|
|
Apr 25 01:29:44 PM PDT 24 |
Apr 25 01:29:45 PM PDT 24 |
23575219 ps |
| T926 |
/workspace/coverage/default/34.sram_ctrl_executable.3316559870 |
|
|
Apr 25 01:29:11 PM PDT 24 |
Apr 25 01:49:38 PM PDT 24 |
3968088138 ps |
| T927 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.904604332 |
|
|
Apr 25 01:32:17 PM PDT 24 |
Apr 25 01:32:20 PM PDT 24 |
159756812 ps |
| T928 |
/workspace/coverage/default/3.sram_ctrl_bijection.2461186726 |
|
|
Apr 25 01:22:59 PM PDT 24 |
Apr 25 01:23:33 PM PDT 24 |
4627057875 ps |
| T929 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3702631212 |
|
|
Apr 25 01:29:49 PM PDT 24 |
Apr 25 01:35:00 PM PDT 24 |
5621449854 ps |
| T930 |
/workspace/coverage/default/5.sram_ctrl_regwen.1644718583 |
|
|
Apr 25 01:23:31 PM PDT 24 |
Apr 25 01:28:14 PM PDT 24 |
21332150741 ps |
| T931 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.247159764 |
|
|
Apr 25 01:26:56 PM PDT 24 |
Apr 25 01:27:22 PM PDT 24 |
171355032 ps |
| T932 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3763986698 |
|
|
Apr 25 01:28:57 PM PDT 24 |
Apr 25 01:29:16 PM PDT 24 |
91860312 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1421939832 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:57 PM PDT 24 |
133220040 ps |
| T71 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1417510093 |
|
|
Apr 25 12:40:02 PM PDT 24 |
Apr 25 12:40:06 PM PDT 24 |
216758918 ps |
| T109 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1037691358 |
|
|
Apr 25 12:39:52 PM PDT 24 |
Apr 25 12:39:57 PM PDT 24 |
85812093 ps |
| T72 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2225274119 |
|
|
Apr 25 12:40:11 PM PDT 24 |
Apr 25 12:40:14 PM PDT 24 |
18410771 ps |
| T110 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2011611855 |
|
|
Apr 25 12:40:22 PM PDT 24 |
Apr 25 12:40:25 PM PDT 24 |
33122379 ps |
| T73 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1969584498 |
|
|
Apr 25 12:39:58 PM PDT 24 |
Apr 25 12:40:01 PM PDT 24 |
936188487 ps |
| T74 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2479094847 |
|
|
Apr 25 12:40:05 PM PDT 24 |
Apr 25 12:40:07 PM PDT 24 |
21070388 ps |
| T75 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4205937651 |
|
|
Apr 25 12:40:04 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
44565748 ps |
| T111 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1009234105 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:56 PM PDT 24 |
13043727 ps |
| T76 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4081925489 |
|
|
Apr 25 12:40:02 PM PDT 24 |
Apr 25 12:40:04 PM PDT 24 |
84852387 ps |
| T933 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.527284677 |
|
|
Apr 25 12:39:59 PM PDT 24 |
Apr 25 12:40:03 PM PDT 24 |
39606466 ps |
| T102 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1545146964 |
|
|
Apr 25 12:40:02 PM PDT 24 |
Apr 25 12:40:14 PM PDT 24 |
156183884 ps |
| T934 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2450389741 |
|
|
Apr 25 12:40:04 PM PDT 24 |
Apr 25 12:40:06 PM PDT 24 |
65708793 ps |
| T935 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2497235754 |
|
|
Apr 25 12:40:07 PM PDT 24 |
Apr 25 12:40:10 PM PDT 24 |
107947282 ps |
| T936 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1463703300 |
|
|
Apr 25 12:39:59 PM PDT 24 |
Apr 25 12:40:01 PM PDT 24 |
44973000 ps |
| T112 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2380109617 |
|
|
Apr 25 12:40:00 PM PDT 24 |
Apr 25 12:40:04 PM PDT 24 |
664313324 ps |
| T937 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1165353878 |
|
|
Apr 25 12:40:06 PM PDT 24 |
Apr 25 12:40:10 PM PDT 24 |
88390305 ps |
| T77 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2063885882 |
|
|
Apr 25 12:39:51 PM PDT 24 |
Apr 25 12:39:54 PM PDT 24 |
17390672 ps |
| T938 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3865212933 |
|
|
Apr 25 12:40:06 PM PDT 24 |
Apr 25 12:40:13 PM PDT 24 |
578813410 ps |
| T78 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3714740218 |
|
|
Apr 25 12:39:52 PM PDT 24 |
Apr 25 12:39:55 PM PDT 24 |
27867254 ps |
| T939 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3710600753 |
|
|
Apr 25 12:40:00 PM PDT 24 |
Apr 25 12:40:04 PM PDT 24 |
152116337 ps |
| T113 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1921579866 |
|
|
Apr 25 12:40:02 PM PDT 24 |
Apr 25 12:40:05 PM PDT 24 |
122154290 ps |
| T940 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.297564604 |
|
|
Apr 25 12:39:47 PM PDT 24 |
Apr 25 12:39:50 PM PDT 24 |
26675402 ps |
| T79 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1654294437 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:59 PM PDT 24 |
5263016955 ps |
| T114 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4170221441 |
|
|
Apr 25 12:40:14 PM PDT 24 |
Apr 25 12:40:16 PM PDT 24 |
85576164 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.472979483 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:57 PM PDT 24 |
52960988 ps |
| T941 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3203206923 |
|
|
Apr 25 12:39:50 PM PDT 24 |
Apr 25 12:39:54 PM PDT 24 |
411131595 ps |
| T134 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2512861633 |
|
|
Apr 25 12:39:59 PM PDT 24 |
Apr 25 12:40:07 PM PDT 24 |
270528787 ps |
| T103 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1570117057 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:56 PM PDT 24 |
25865101 ps |
| T942 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.668297018 |
|
|
Apr 25 12:39:54 PM PDT 24 |
Apr 25 12:40:00 PM PDT 24 |
125840818 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4252302570 |
|
|
Apr 25 12:40:06 PM PDT 24 |
Apr 25 12:40:08 PM PDT 24 |
65209966 ps |
| T83 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3818769708 |
|
|
Apr 25 12:40:24 PM PDT 24 |
Apr 25 12:40:32 PM PDT 24 |
221739827 ps |
| T84 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3068019420 |
|
|
Apr 25 12:40:20 PM PDT 24 |
Apr 25 12:40:23 PM PDT 24 |
256421676 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2234472356 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:57 PM PDT 24 |
39708914 ps |
| T945 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2908953246 |
|
|
Apr 25 12:39:59 PM PDT 24 |
Apr 25 12:40:01 PM PDT 24 |
15630286 ps |
| T85 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.493234596 |
|
|
Apr 25 12:39:59 PM PDT 24 |
Apr 25 12:40:09 PM PDT 24 |
1185951080 ps |
| T946 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3967316546 |
|
|
Apr 25 12:40:08 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
37152907 ps |
| T947 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.16643758 |
|
|
Apr 25 12:40:08 PM PDT 24 |
Apr 25 12:40:11 PM PDT 24 |
21104440 ps |
| T948 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3908750302 |
|
|
Apr 25 12:39:51 PM PDT 24 |
Apr 25 12:39:55 PM PDT 24 |
84573167 ps |
| T949 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2918145191 |
|
|
Apr 25 12:40:20 PM PDT 24 |
Apr 25 12:40:23 PM PDT 24 |
66473874 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2226970590 |
|
|
Apr 25 12:39:56 PM PDT 24 |
Apr 25 12:39:59 PM PDT 24 |
482054091 ps |
| T93 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2450964889 |
|
|
Apr 25 12:39:58 PM PDT 24 |
Apr 25 12:40:00 PM PDT 24 |
49675426 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3361385874 |
|
|
Apr 25 12:40:28 PM PDT 24 |
Apr 25 12:40:31 PM PDT 24 |
54687362 ps |
| T951 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3881538627 |
|
|
Apr 25 12:40:00 PM PDT 24 |
Apr 25 12:40:03 PM PDT 24 |
38048342 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1894547151 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:56 PM PDT 24 |
35747629 ps |
| T953 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2216599796 |
|
|
Apr 25 12:40:08 PM PDT 24 |
Apr 25 12:40:17 PM PDT 24 |
66928810 ps |
| T954 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3457151951 |
|
|
Apr 25 12:40:01 PM PDT 24 |
Apr 25 12:40:03 PM PDT 24 |
28892287 ps |
| T135 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2593931441 |
|
|
Apr 25 12:39:50 PM PDT 24 |
Apr 25 12:39:55 PM PDT 24 |
1167044586 ps |
| T138 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3247091175 |
|
|
Apr 25 12:40:06 PM PDT 24 |
Apr 25 12:40:09 PM PDT 24 |
173900665 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.133008565 |
|
|
Apr 25 12:40:08 PM PDT 24 |
Apr 25 12:40:11 PM PDT 24 |
50464808 ps |
| T94 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1516635716 |
|
|
Apr 25 12:40:07 PM PDT 24 |
Apr 25 12:40:11 PM PDT 24 |
863803417 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1765091871 |
|
|
Apr 25 12:39:49 PM PDT 24 |
Apr 25 12:39:53 PM PDT 24 |
231384356 ps |
| T957 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2006494381 |
|
|
Apr 25 12:40:00 PM PDT 24 |
Apr 25 12:40:03 PM PDT 24 |
33828866 ps |
| T958 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.573073623 |
|
|
Apr 25 12:40:02 PM PDT 24 |
Apr 25 12:40:04 PM PDT 24 |
87053892 ps |
| T959 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3269119803 |
|
|
Apr 25 12:40:00 PM PDT 24 |
Apr 25 12:40:03 PM PDT 24 |
58055921 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3584728266 |
|
|
Apr 25 12:39:52 PM PDT 24 |
Apr 25 12:39:55 PM PDT 24 |
14478539 ps |
| T100 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2819542806 |
|
|
Apr 25 12:39:52 PM PDT 24 |
Apr 25 12:39:55 PM PDT 24 |
19508816 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3775287400 |
|
|
Apr 25 12:40:02 PM PDT 24 |
Apr 25 12:40:05 PM PDT 24 |
35853958 ps |
| T962 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.501066948 |
|
|
Apr 25 12:40:09 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
35116458 ps |
| T963 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3887068260 |
|
|
Apr 25 12:39:59 PM PDT 24 |
Apr 25 12:40:03 PM PDT 24 |
105409124 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1012373710 |
|
|
Apr 25 12:39:57 PM PDT 24 |
Apr 25 12:39:59 PM PDT 24 |
24928355 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.999613745 |
|
|
Apr 25 12:40:04 PM PDT 24 |
Apr 25 12:40:07 PM PDT 24 |
14253797 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2190828486 |
|
|
Apr 25 12:40:21 PM PDT 24 |
Apr 25 12:40:24 PM PDT 24 |
18447098 ps |
| T141 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4203936958 |
|
|
Apr 25 12:40:12 PM PDT 24 |
Apr 25 12:40:16 PM PDT 24 |
226589717 ps |
| T967 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.133195220 |
|
|
Apr 25 12:40:04 PM PDT 24 |
Apr 25 12:40:09 PM PDT 24 |
42981524 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4022792452 |
|
|
Apr 25 12:40:04 PM PDT 24 |
Apr 25 12:40:09 PM PDT 24 |
261052073 ps |
| T969 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2160025519 |
|
|
Apr 25 12:40:06 PM PDT 24 |
Apr 25 12:40:09 PM PDT 24 |
89496010 ps |
| T95 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2218627689 |
|
|
Apr 25 12:40:07 PM PDT 24 |
Apr 25 12:40:11 PM PDT 24 |
413170598 ps |
| T96 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3716825359 |
|
|
Apr 25 12:40:15 PM PDT 24 |
Apr 25 12:40:20 PM PDT 24 |
916514669 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.718903489 |
|
|
Apr 25 12:39:51 PM PDT 24 |
Apr 25 12:39:58 PM PDT 24 |
52819188 ps |
| T97 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.995746609 |
|
|
Apr 25 12:40:07 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
1538263037 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1154580801 |
|
|
Apr 25 12:39:48 PM PDT 24 |
Apr 25 12:39:53 PM PDT 24 |
392663307 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1322920906 |
|
|
Apr 25 12:40:04 PM PDT 24 |
Apr 25 12:40:08 PM PDT 24 |
129185340 ps |
| T973 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4063485387 |
|
|
Apr 25 12:40:00 PM PDT 24 |
Apr 25 12:40:04 PM PDT 24 |
37361866 ps |
| T974 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1186473385 |
|
|
Apr 25 12:40:37 PM PDT 24 |
Apr 25 12:40:39 PM PDT 24 |
51234896 ps |
| T975 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2281081633 |
|
|
Apr 25 12:40:08 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
130431980 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3724735102 |
|
|
Apr 25 12:39:59 PM PDT 24 |
Apr 25 12:40:02 PM PDT 24 |
116410662 ps |
| T142 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4048400426 |
|
|
Apr 25 12:40:07 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
912072418 ps |
| T977 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3285733599 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:57 PM PDT 24 |
689068282 ps |
| T101 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3739238530 |
|
|
Apr 25 12:40:09 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
13318498 ps |
| T978 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4224379661 |
|
|
Apr 25 12:40:00 PM PDT 24 |
Apr 25 12:40:02 PM PDT 24 |
33353048 ps |
| T979 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2174842186 |
|
|
Apr 25 12:39:47 PM PDT 24 |
Apr 25 12:39:50 PM PDT 24 |
20077437 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1969764671 |
|
|
Apr 25 12:40:35 PM PDT 24 |
Apr 25 12:40:37 PM PDT 24 |
48834700 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.712050131 |
|
|
Apr 25 12:39:52 PM PDT 24 |
Apr 25 12:39:55 PM PDT 24 |
20552008 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3200514434 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:56 PM PDT 24 |
25720221 ps |
| T983 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1441195493 |
|
|
Apr 25 12:40:06 PM PDT 24 |
Apr 25 12:40:09 PM PDT 24 |
186844161 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3732482807 |
|
|
Apr 25 12:39:55 PM PDT 24 |
Apr 25 12:39:58 PM PDT 24 |
102031314 ps |
| T985 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4247042200 |
|
|
Apr 25 12:40:00 PM PDT 24 |
Apr 25 12:40:07 PM PDT 24 |
531760536 ps |
| T143 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1932338250 |
|
|
Apr 25 12:40:03 PM PDT 24 |
Apr 25 12:40:06 PM PDT 24 |
219181994 ps |
| T986 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3255946241 |
|
|
Apr 25 12:39:55 PM PDT 24 |
Apr 25 12:39:58 PM PDT 24 |
16718244 ps |
| T987 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2886701082 |
|
|
Apr 25 12:39:58 PM PDT 24 |
Apr 25 12:39:59 PM PDT 24 |
14808700 ps |
| T98 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2331696772 |
|
|
Apr 25 12:39:55 PM PDT 24 |
Apr 25 12:39:58 PM PDT 24 |
51038490 ps |
| T988 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1565792370 |
|
|
Apr 25 12:40:07 PM PDT 24 |
Apr 25 12:40:10 PM PDT 24 |
31692275 ps |
| T144 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3566811962 |
|
|
Apr 25 12:40:05 PM PDT 24 |
Apr 25 12:40:09 PM PDT 24 |
279696682 ps |
| T989 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.907022141 |
|
|
Apr 25 12:40:05 PM PDT 24 |
Apr 25 12:40:07 PM PDT 24 |
37897122 ps |
| T146 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4132955561 |
|
|
Apr 25 12:40:02 PM PDT 24 |
Apr 25 12:40:06 PM PDT 24 |
217857216 ps |
| T990 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3258171597 |
|
|
Apr 25 12:40:04 PM PDT 24 |
Apr 25 12:40:09 PM PDT 24 |
1523969683 ps |
| T136 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.371320092 |
|
|
Apr 25 12:40:00 PM PDT 24 |
Apr 25 12:40:03 PM PDT 24 |
81735871 ps |
| T991 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3238575304 |
|
|
Apr 25 12:40:08 PM PDT 24 |
Apr 25 12:40:14 PM PDT 24 |
2138123595 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1036205884 |
|
|
Apr 25 12:39:58 PM PDT 24 |
Apr 25 12:40:00 PM PDT 24 |
27312351 ps |
| T993 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3934216119 |
|
|
Apr 25 12:40:36 PM PDT 24 |
Apr 25 12:40:40 PM PDT 24 |
363329639 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4135366116 |
|
|
Apr 25 12:40:05 PM PDT 24 |
Apr 25 12:40:10 PM PDT 24 |
640925992 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1512147134 |
|
|
Apr 25 12:40:08 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
222294407 ps |
| T995 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2298177285 |
|
|
Apr 25 12:40:09 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
60652664 ps |
| T996 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1959145793 |
|
|
Apr 25 12:40:07 PM PDT 24 |
Apr 25 12:40:10 PM PDT 24 |
39327411 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1406276186 |
|
|
Apr 25 12:39:59 PM PDT 24 |
Apr 25 12:40:01 PM PDT 24 |
41126813 ps |
| T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.305690777 |
|
|
Apr 25 12:40:02 PM PDT 24 |
Apr 25 12:40:05 PM PDT 24 |
13311592 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2489558872 |
|
|
Apr 25 12:39:56 PM PDT 24 |
Apr 25 12:39:58 PM PDT 24 |
33130051 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4152287489 |
|
|
Apr 25 12:39:59 PM PDT 24 |
Apr 25 12:40:07 PM PDT 24 |
108439471 ps |
| T1001 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.242369300 |
|
|
Apr 25 12:40:08 PM PDT 24 |
Apr 25 12:40:12 PM PDT 24 |
54844797 ps |
| T140 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2173394944 |
|
|
Apr 25 12:39:48 PM PDT 24 |
Apr 25 12:39:52 PM PDT 24 |
811528761 ps |
| T1002 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.256913669 |
|
|
Apr 25 12:40:01 PM PDT 24 |
Apr 25 12:40:05 PM PDT 24 |
25845823 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1882469388 |
|
|
Apr 25 12:39:53 PM PDT 24 |
Apr 25 12:39:57 PM PDT 24 |
133703656 ps |
| T1004 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2753437822 |
|
|
Apr 25 12:40:07 PM PDT 24 |
Apr 25 12:40:13 PM PDT 24 |
533746030 ps |
| T1005 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.592567014 |
|
|
Apr 25 12:39:52 PM PDT 24 |
Apr 25 12:39:56 PM PDT 24 |
19050807 ps |