Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14724674	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59880415

1

T2

281

T3

136628

T4

222650

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37206746	1			T2	768		T3	74965		T4	122015
values[0x0]	17226394	1			T2	260		T3	36332		T4	59211
values[0x1]	20171949	1			T2	510		T3	38841		T4	63349

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7336261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67268828

1

T2

890

T3

143453

T4

233617

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	307214	1			T3	226		T4	949		T5	6
valid_sources[0x01]	261821	1			T3	77		T4	951		T5	9
valid_sources[0x02]	299066	1			T3	282		T4	910		T5	6
valid_sources[0x03]	294634	1			T3	451		T4	994		T5	8
valid_sources[0x04]	303567	1			T2	123		T3	613		T4	1023
valid_sources[0x05]	308513	1			T3	786		T4	966		T5	2
valid_sources[0x06]	278905	1			T3	1314		T4	983		T12	387
valid_sources[0x07]	294580	1			T3	657		T4	987		T5	8
valid_sources[0x08]	268480	1			T3	98		T4	972		T5	2
valid_sources[0x09]	254433	1			T3	587		T4	998		T5	9
valid_sources[0x0a]	311520	1			T3	565		T4	944		T5	2
valid_sources[0x0b]	267244	1			T3	633		T4	940		T5	1
valid_sources[0x0c]	299661	1			T3	534		T4	891		T5	1
valid_sources[0x0d]	287004	1			T3	463		T4	947		T5	3
valid_sources[0x0e]	305336	1			T3	247		T4	891		T5	2
valid_sources[0x0f]	262731	1			T3	679		T4	979		T5	7
valid_sources[0x10]	268032	1			T3	587		T4	909		T12	385
valid_sources[0x11]	258851	1			T3	288		T4	978		T5	1
valid_sources[0x12]	299317	1			T3	1163		T4	922		T5	2
valid_sources[0x13]	347447	1			T3	1152		T4	915		T12	291
valid_sources[0x14]	302510	1			T3	441		T4	925		T5	5
valid_sources[0x15]	287354	1			T3	673		T4	926		T5	10
valid_sources[0x16]	262129	1			T2	156		T4	891		T5	1
valid_sources[0x17]	343254	1			T4	869		T5	1		T12	341
valid_sources[0x18]	284240	1			T3	791		T4	911		T5	3
valid_sources[0x19]	339282	1			T3	384		T4	942		T12	403
valid_sources[0x1a]	288329	1			T3	897		T4	931		T5	1
valid_sources[0x1b]	274416	1			T3	471		T4	968		T12	336
valid_sources[0x1c]	294953	1			T3	373		T4	1027		T5	14
valid_sources[0x1d]	300190	1			T3	35		T4	930		T5	4
valid_sources[0x1e]	273250	1			T2	11		T3	643		T4	970
valid_sources[0x1f]	324194	1			T3	856		T4	995		T5	1
valid_sources[0x20]	295343	1			T3	66		T4	975		T5	10
valid_sources[0x21]	248121	1			T3	828		T4	940		T5	1
valid_sources[0x22]	269386	1			T3	972		T4	999		T12	376
valid_sources[0x23]	253942	1			T2	41		T3	1167		T4	997
valid_sources[0x24]	256250	1			T3	68		T4	953		T5	6
valid_sources[0x25]	345135	1			T3	970		T4	1052		T5	13
valid_sources[0x26]	314892	1			T3	399		T4	958		T5	4
valid_sources[0x27]	280872	1			T3	1514		T4	928		T5	1
valid_sources[0x28]	271277	1			T3	1038		T4	946		T5	1
valid_sources[0x29]	262992	1			T3	133		T4	1001		T5	4
valid_sources[0x2a]	279014	1			T3	490		T4	869		T5	8
valid_sources[0x2b]	272376	1			T3	771		T4	1059		T5	5
valid_sources[0x2c]	293518	1			T2	147		T3	858		T4	928
valid_sources[0x2d]	263576	1			T3	612		T4	997		T5	2
valid_sources[0x2e]	282757	1			T3	1193		T4	998		T5	1
valid_sources[0x2f]	259446	1			T3	716		T4	907		T5	1
valid_sources[0x30]	317990	1			T3	417		T4	940		T5	2
valid_sources[0x31]	315546	1			T3	405		T4	931		T5	2
valid_sources[0x32]	273017	1			T3	460		T4	1008		T5	1
valid_sources[0x33]	285595	1			T3	415		T4	977		T5	2
valid_sources[0x34]	275261	1			T3	383		T4	900		T12	391
valid_sources[0x35]	260906	1			T3	288		T4	997		T12	416
valid_sources[0x36]	259922	1			T3	25		T4	951		T5	7
valid_sources[0x37]	264991	1			T3	462		T4	956		T5	3
valid_sources[0x38]	286680	1			T3	575		T4	978		T5	3
valid_sources[0x39]	254979	1			T3	291		T4	890		T5	3
valid_sources[0x3a]	315864	1			T2	147		T3	117		T4	1041
valid_sources[0x3b]	309678	1			T2	38		T3	380		T4	940
valid_sources[0x3c]	257425	1			T3	383		T4	960		T5	3
valid_sources[0x3d]	248536	1			T3	992		T4	943		T5	3
valid_sources[0x3e]	345793	1			T3	574		T4	990		T5	4
valid_sources[0x3f]	295266	1			T3	1063		T4	1092		T5	7
valid_sources[0x40]	286021	1			T3	139		T4	888		T5	3
valid_sources[0x41]	249785	1			T3	261		T4	903		T5	11
valid_sources[0x42]	251462	1			T3	648		T4	979		T5	3
valid_sources[0x43]	298874	1			T3	740		T4	1070		T5	1
valid_sources[0x44]	263907	1			T3	554		T4	906		T12	398
valid_sources[0x45]	307094	1			T2	23		T3	491		T4	903
valid_sources[0x46]	283055	1			T3	300		T4	976		T5	4
valid_sources[0x47]	277784	1			T3	1030		T4	990		T5	5
valid_sources[0x48]	351262	1			T2	153		T3	750		T4	938
valid_sources[0x49]	298925	1			T3	425		T4	977		T5	12
valid_sources[0x4a]	267844	1			T3	1200		T4	948		T5	6
valid_sources[0x4b]	320258	1			T3	836		T4	967		T5	4
valid_sources[0x4c]	296813	1			T3	643		T4	937		T5	3
valid_sources[0x4d]	305374	1			T3	509		T4	974		T5	3
valid_sources[0x4e]	324548	1			T2	121		T3	783		T4	1011
valid_sources[0x4f]	286929	1			T3	334		T4	1026		T5	2
valid_sources[0x50]	320197	1			T3	416		T4	967		T5	6
valid_sources[0x51]	262397	1			T3	817		T4	975		T5	1
valid_sources[0x52]	258677	1			T3	993		T4	951		T12	308
valid_sources[0x53]	344705	1			T3	268		T4	992		T5	4
valid_sources[0x54]	278106	1			T3	459		T4	980		T12	348
valid_sources[0x55]	265981	1			T3	992		T4	995		T5	7
valid_sources[0x56]	280673	1			T3	878		T4	917		T5	4
valid_sources[0x57]	277140	1			T3	633		T4	938		T5	3
valid_sources[0x58]	258073	1			T3	699		T4	932		T5	5
valid_sources[0x59]	287360	1			T3	533		T4	918		T5	1
valid_sources[0x5a]	268096	1			T3	471		T4	994		T5	1
valid_sources[0x5b]	308576	1			T3	298		T4	980		T5	2
valid_sources[0x5c]	299492	1			T3	605		T4	958		T5	9
valid_sources[0x5d]	265351	1			T3	355		T4	948		T12	317
valid_sources[0x5e]	292121	1			T3	770		T4	941		T12	273
valid_sources[0x5f]	269001	1			T3	766		T4	1000		T5	1
valid_sources[0x60]	258686	1			T3	316		T4	968		T5	5
valid_sources[0x61]	280233	1			T3	641		T4	948		T5	1
valid_sources[0x62]	260234	1			T2	29		T3	1467		T4	942
valid_sources[0x63]	290099	1			T2	29		T3	932		T4	935
valid_sources[0x64]	276807	1			T3	525		T4	971		T5	3
valid_sources[0x65]	288875	1			T3	911		T4	1006		T5	4
valid_sources[0x66]	317587	1			T3	377		T4	936		T5	5
valid_sources[0x67]	422691	1			T3	604		T4	890		T5	2
valid_sources[0x68]	275667	1			T3	333		T4	917		T5	1
valid_sources[0x69]	250624	1			T3	205		T4	918		T5	1
valid_sources[0x6a]	301419	1			T3	472		T4	965		T5	7
valid_sources[0x6b]	333238	1			T3	545		T4	947		T5	8
valid_sources[0x6c]	274448	1			T3	686		T4	912		T5	9
valid_sources[0x6d]	291544	1			T3	581		T4	957		T5	12
valid_sources[0x6e]	287057	1			T2	9		T3	863		T4	933
valid_sources[0x6f]	249611	1			T3	834		T4	952		T5	3
valid_sources[0x70]	273815	1			T3	602		T4	997		T5	2
valid_sources[0x71]	283771	1			T3	622		T4	953		T5	6
valid_sources[0x72]	283254	1			T3	311		T4	963		T5	4
valid_sources[0x73]	275814	1			T3	852		T4	942		T12	349
valid_sources[0x74]	255224	1			T2	59		T3	680		T4	982
valid_sources[0x75]	291636	1			T3	48		T4	1035		T12	466
valid_sources[0x76]	308766	1			T3	596		T4	927		T5	4
valid_sources[0x77]	346497	1			T3	160		T4	976		T5	8
valid_sources[0x78]	251861	1			T3	49		T4	979		T5	1
valid_sources[0x79]	261979	1			T3	632		T4	959		T5	1
valid_sources[0x7a]	281048	1			T3	993		T4	973		T5	9
valid_sources[0x7b]	283914	1			T3	634		T4	930		T5	3
valid_sources[0x7c]	294971	1			T3	516		T4	992		T5	5
valid_sources[0x7d]	341311	1			T3	379		T4	993		T5	8
valid_sources[0x7e]	288227	1			T3	447		T4	1018		T5	3
valid_sources[0x7f]	270499	1			T3	258		T4	911		T5	7
valid_sources[0x80]	354481	1			T3	430		T4	967		T5	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29846786

1

T2

140

T3

68245

T4

111160

values[0x0]

all_enables

biggest_size

15017802

1

T2

77

T3

34292

T4

55816

values[0x1]

all_enables

biggest_size

15015827

1

T2

64

T3

34091

T4

55674

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35006	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

125688

1

T3

8

T11

1

T4

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47613	1			T3	10		T16	1510		T18	11
values[0x0]	54965	1			T2	1		T3	19		T11	1
values[0x1]	58116	1			T1	1		T3	23		T11	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26941	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

133753

1

T3

16

T11

1

T4

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	532	1			T16	27		T39	1		T126	1
valid_sources[0x01]	659	1			T16	31		T23	2		T39	1
valid_sources[0x02]	600	1			T16	25		T79	1		T8	1
valid_sources[0x03]	469	1			T16	31		T37	1		T25	25
valid_sources[0x04]	812	1			T16	20		T23	1		T34	1
valid_sources[0x05]	552	1			T3	2		T16	9		T39	1
valid_sources[0x06]	585	1			T16	24		T51	1		T9	1
valid_sources[0x07]	511	1			T16	19		T40	1		T9	1
valid_sources[0x08]	722	1			T16	33		T9	1		T25	34
valid_sources[0x09]	800	1			T4	1		T16	27		T23	1
valid_sources[0x0a]	583	1			T16	21		T7	1		T127	2
valid_sources[0x0b]	781	1			T16	31		T128	2		T25	32
valid_sources[0x0c]	506	1			T16	19		T18	3		T51	1
valid_sources[0x0d]	570	1			T2	1		T16	25		T7	1
valid_sources[0x0e]	678	1			T6	1		T16	14		T34	1
valid_sources[0x0f]	571	1			T16	14		T39	1		T22	5
valid_sources[0x10]	571	1			T16	29		T23	1		T34	1
valid_sources[0x11]	630	1			T16	35		T7	2		T120	1
valid_sources[0x12]	611	1			T16	14		T23	8		T8	1
valid_sources[0x13]	721	1			T13	1		T16	18		T37	1
valid_sources[0x14]	594	1			T16	15		T39	2		T25	25
valid_sources[0x15]	565	1			T16	28		T18	2		T7	1
valid_sources[0x16]	561	1			T16	21		T23	5		T126	1
valid_sources[0x17]	567	1			T3	2		T16	28		T126	1
valid_sources[0x18]	701	1			T16	21		T23	7		T39	1
valid_sources[0x19]	680	1			T15	1		T16	22		T39	1
valid_sources[0x1a]	717	1			T16	14		T39	1		T7	1
valid_sources[0x1b]	645	1			T12	1		T16	12		T123	1
valid_sources[0x1c]	670	1			T16	12		T23	6		T39	2
valid_sources[0x1d]	1003	1			T16	25		T9	1		T25	34
valid_sources[0x1e]	639	1			T16	11		T34	1		T37	1
valid_sources[0x1f]	526	1			T16	9		T23	1		T39	3
valid_sources[0x20]	939	1			T16	18		T18	2		T51	1
valid_sources[0x21]	583	1			T16	33		T7	1		T129	1
valid_sources[0x22]	539	1			T16	29		T119	2		T40	1
valid_sources[0x23]	634	1			T16	31		T39	2		T34	1
valid_sources[0x24]	822	1			T16	15		T39	1		T119	1
valid_sources[0x25]	647	1			T16	26		T37	1		T64	4
valid_sources[0x26]	704	1			T16	34		T9	1		T25	32
valid_sources[0x27]	763	1			T16	21		T18	1		T9	1
valid_sources[0x28]	515	1			T16	32		T126	1		T51	1
valid_sources[0x29]	870	1			T16	26		T23	5		T39	2
valid_sources[0x2a]	493	1			T16	21		T37	1		T130	1
valid_sources[0x2b]	553	1			T5	1		T16	21		T51	1
valid_sources[0x2c]	521	1			T16	39		T39	6		T129	1
valid_sources[0x2d]	815	1			T15	1		T16	43		T51	1
valid_sources[0x2e]	839	1			T16	30		T39	2		T9	1
valid_sources[0x2f]	564	1			T12	3		T16	22		T7	1
valid_sources[0x30]	516	1			T16	33		T18	1		T23	1
valid_sources[0x31]	607	1			T13	1		T16	25		T10	3
valid_sources[0x32]	961	1			T16	20		T126	1		T51	1
valid_sources[0x33]	595	1			T16	24		T37	2		T120	1
valid_sources[0x34]	472	1			T16	29		T119	1		T131	1
valid_sources[0x35]	628	1			T3	5		T16	8		T51	1
valid_sources[0x36]	590	1			T16	36		T23	2		T9	2
valid_sources[0x37]	528	1			T3	2		T16	4		T27	1
valid_sources[0x38]	487	1			T12	1		T16	25		T10	1
valid_sources[0x39]	668	1			T16	12		T34	1		T51	2
valid_sources[0x3a]	570	1			T16	24		T10	5		T40	1
valid_sources[0x3b]	509	1			T16	36		T39	1		T34	1
valid_sources[0x3c]	626	1			T16	29		T37	1		T51	1
valid_sources[0x3d]	825	1			T3	1		T16	31		T132	2
valid_sources[0x3e]	720	1			T4	1		T16	46		T23	1
valid_sources[0x3f]	445	1			T16	19		T23	2		T10	4
valid_sources[0x40]	568	1			T16	14		T23	12		T37	1
valid_sources[0x41]	906	1			T16	16		T18	1		T7	2
valid_sources[0x42]	685	1			T12	1		T16	23		T25	27
valid_sources[0x43]	820	1			T3	1		T16	15		T34	1
valid_sources[0x44]	544	1			T16	20		T29	1		T9	1
valid_sources[0x45]	605	1			T16	37		T7	1		T133	7
valid_sources[0x46]	554	1			T16	16		T7	1		T37	3
valid_sources[0x47]	707	1			T16	23		T119	1		T79	2
valid_sources[0x48]	535	1			T16	17		T23	1		T40	1
valid_sources[0x49]	488	1			T16	10		T23	1		T7	2
valid_sources[0x4a]	738	1			T16	23		T51	2		T9	1
valid_sources[0x4b]	535	1			T16	20		T48	1		T23	3
valid_sources[0x4c]	480	1			T16	11		T37	1		T51	4
valid_sources[0x4d]	546	1			T16	10		T39	1		T37	1
valid_sources[0x4e]	675	1			T12	3		T16	12		T39	1
valid_sources[0x4f]	719	1			T16	16		T134	1		T135	18
valid_sources[0x50]	510	1			T4	1		T16	35		T51	2
valid_sources[0x51]	648	1			T16	26		T25	26		T136	1
valid_sources[0x52]	639	1			T16	25		T23	7		T80	3
valid_sources[0x53]	651	1			T3	2		T16	15		T23	1
valid_sources[0x54]	536	1			T16	35		T34	1		T9	1
valid_sources[0x55]	993	1			T16	23		T119	2		T10	1
valid_sources[0x56]	638	1			T16	31		T18	7		T9	1
valid_sources[0x57]	699	1			T16	39		T39	3		T7	1
valid_sources[0x58]	569	1			T16	33		T23	1		T7	1
valid_sources[0x59]	770	1			T4	1		T16	36		T39	1
valid_sources[0x5a]	658	1			T16	26		T39	3		T37	1
valid_sources[0x5b]	597	1			T16	19		T119	1		T37	1
valid_sources[0x5c]	496	1			T16	16		T7	2		T51	4
valid_sources[0x5d]	724	1			T16	26		T137	1		T25	31
valid_sources[0x5e]	614	1			T16	19		T122	6		T25	39
valid_sources[0x5f]	587	1			T16	14		T7	1		T34	1
valid_sources[0x60]	641	1			T4	2		T16	22		T21	1
valid_sources[0x61]	627	1			T12	1		T16	23		T37	1
valid_sources[0x62]	599	1			T16	31		T23	4		T39	1
valid_sources[0x63]	604	1			T3	2		T16	14		T34	1
valid_sources[0x64]	505	1			T3	12		T16	35		T18	3
valid_sources[0x65]	498	1			T16	13		T25	25		T41	17
valid_sources[0x66]	709	1			T16	6		T39	3		T9	1
valid_sources[0x67]	647	1			T16	18		T39	2		T120	1
valid_sources[0x68]	523	1			T16	10		T34	2		T126	1
valid_sources[0x69]	662	1			T16	30		T23	4		T37	1
valid_sources[0x6a]	884	1			T16	54		T18	3		T9	1
valid_sources[0x6b]	539	1			T16	28		T37	1		T130	1
valid_sources[0x6c]	811	1			T16	17		T37	3		T9	1
valid_sources[0x6d]	625	1			T16	21		T21	1		T39	2
valid_sources[0x6e]	849	1			T16	8		T39	1		T51	2
valid_sources[0x6f]	682	1			T12	1		T16	6		T34	1
valid_sources[0x70]	688	1			T16	14		T7	1		T51	1
valid_sources[0x71]	601	1			T16	17		T18	2		T23	2
valid_sources[0x72]	555	1			T16	13		T126	1		T25	27
valid_sources[0x73]	573	1			T16	31		T51	1		T25	24
valid_sources[0x74]	502	1			T16	8		T39	2		T7	1
valid_sources[0x75]	765	1			T16	28		T39	1		T37	1
valid_sources[0x76]	966	1			T16	21		T24	58		T7	1
valid_sources[0x77]	557	1			T16	13		T9	1		T25	8
valid_sources[0x78]	698	1			T16	25		T9	1		T25	37
valid_sources[0x79]	631	1			T3	2		T16	13		T18	1
valid_sources[0x7a]	560	1			T16	18		T23	2		T39	1
valid_sources[0x7b]	704	1			T16	53		T23	3		T64	3
valid_sources[0x7c]	735	1			T16	27		T34	2		T37	2
valid_sources[0x7d]	626	1			T16	34		T37	1		T138	1
valid_sources[0x7e]	541	1			T16	14		T34	2		T51	1
valid_sources[0x7f]	705	1			T16	24		T18	5		T34	2
valid_sources[0x80]	493	1			T16	40		T34	1		T37	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

34825

1

T3

4

T16

1377

T18

7

values[0x0]

all_enables

biggest_size

46656

1

T3

4

T11

1

T4

5

values[0x1]

all_enables

biggest_size

44207

1

T4

4

T12

2

T16

2108