Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14376722

1

T2

1257

T3

10850

T4

21925

full_word

54697028

1

T2

281

T3

109274

T4

222650

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69073410	1			T2	1538		T3	120124		T4	244575
auto[TlIntgErrCmd]	122	1			T87	11		T88	6		T89	3
auto[TlIntgErrData]	109	1			T87	4		T88	9		T89	8
auto[TlIntgErrBoth]	109	1			T87	5		T88	5		T89	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31626148

1

T2

768

T3

44951

T4

122015

auto[1]

37447602

1

T2

770

T3

75173

T4

122560

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6883687	1			T2	628		T3	4060		T4	10855
auto[TlIntgErrNone]	partial	auto[1]	7492723	1			T2	629		T3	6790		T4	11070
auto[TlIntgErrNone]	full_word	auto[0]	24742309	1			T2	140		T3	40891		T4	111160
auto[TlIntgErrNone]	full_word	auto[1]	29954691	1			T2	141		T3	68383		T4	111490
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T87	7		T88	1		T89	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T87	4		T88	5		T89	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T116	1		T117	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T110	1		T116	2		T115	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T87	2		T88	4		T89	4
auto[TlIntgErrData]	partial	auto[1]	51	1			T87	1		T88	5		T89	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T87	1		T89	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T110	1		T118	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T87	2		T88	3		T89	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T87	3		T88	2		T89	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T89	1		T108	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T89	1		T108	1		T112	1