Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	729775	1			T4	9977		T6	6		T15	8142
auto[1]	11192888	1			T2	20		T3	3857		T4	7047
auto[2]	589724	1			T4	6512		T6	8		T15	7164
auto[3]	11052822	1			T2	24		T3	3888		T4	3468

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15042641	1			T2	7		T3	6424		T4	20854
auto[1]	2283530	1			T2	8		T3	625		T4	2453
auto[2]	2264806	1			T2	12		T3	637		T4	3314
auto[3]	3974232	1			T2	17		T3	59		T4	383

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9486536

1

T2

44

T3

7738

T4

26981

auto[1]

14078673

1

T3

7

T4

23

T12

52

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	239641	1			T4	8236		T6	6		T39	1225
auto[0]	auto[0]	auto[1]	24318	1			T4	829		T39	107		T37	60
auto[0]	auto[0]	auto[2]	24539	1			T4	818		T15	1		T39	121
auto[0]	auto[0]	auto[3]	7082	1			T4	88		T15	3		T39	13
auto[0]	auto[1]	auto[0]	3676138	1			T2	4		T3	3197		T4	5464
auto[0]	auto[1]	auto[1]	376687	1			T2	3		T3	308		T4	950
auto[0]	auto[1]	auto[2]	366755	1			T2	7		T3	311		T4	524
auto[0]	auto[1]	auto[3]	69130	1			T2	6		T3	36		T4	102
auto[0]	auto[2]	auto[0]	206319	1			T4	5054		T6	7		T39	811
auto[0]	auto[2]	auto[1]	20938	1			T4	481		T39	77		T37	42
auto[0]	auto[2]	auto[2]	20334	1			T4	890		T6	1		T39	138
auto[0]	auto[2]	auto[3]	5664	1			T4	83		T15	1		T39	11
auto[0]	auto[3]	auto[0]	3639712	1			T2	3		T3	3220		T4	2079
auto[0]	auto[3]	auto[1]	363723	1			T2	5		T3	317		T4	192
auto[0]	auto[3]	auto[2]	372441	1			T2	5		T3	326		T4	1081
auto[0]	auto[3]	auto[3]	73115	1			T2	11		T3	23		T4	110
auto[1]	auto[0]	auto[0]	14554	1			T4	5		T15	233		T37	5
auto[1]	auto[0]	auto[1]	64734	1			T15	1224		T9	5		T81	3841
auto[1]	auto[0]	auto[2]	64211	1			T4	1		T15	1231		T9	1
auto[1]	auto[0]	auto[3]	290696	1			T15	5450		T67	2		T81	17261
auto[1]	auto[1]	auto[0]	3627504	1			T3	5		T4	7		T12	23
auto[1]	auto[1]	auto[1]	708149	1			T12	5		T15	1402		T17	4
auto[1]	auto[1]	auto[2]	675974	1			T12	1		T14	1		T15	787
auto[1]	auto[1]	auto[3]	1692551	1			T15	6305		T50	522		T34	1
auto[1]	auto[2]	auto[0]	12966	1			T4	4		T15	151		T123	1
auto[1]	auto[2]	auto[1]	57225	1			T15	708		T9	1		T107	1
auto[1]	auto[2]	auto[2]	48420	1			T15	1165		T9	1		T81	2574
auto[1]	auto[2]	auto[3]	217858	1			T15	5139		T9	1		T81	11535
auto[1]	auto[3]	auto[0]	3625807	1			T3	2		T4	5		T12	20
auto[1]	auto[3]	auto[1]	667756	1			T4	1		T12	1		T14	1
auto[1]	auto[3]	auto[2]	692132	1			T12	2		T14	1		T15	1378
auto[1]	auto[3]	auto[3]	1618136	1			T15	6190		T17	1		T50	536