Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	313191941	119490	0	0
ctrl_regwen_rd_A	313191941	7747	0	0
exec_rd_A	313191941	7002	0	0
exec_regwen_rd_A	313191941	7789	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313191941	119490	0	0
T16	213101	6852	0	0
T17	128151	0	0	0
T18	196925	0	0	0
T21	917	0	0	0
T23	513721	0	0	0
T24	867994	0	0	0
T25	0	7489	0	0
T26	0	1622	0	0
T39	200087	0	0	0
T41	0	6639	0	0
T42	0	1205	0	0
T43	0	2439	0	0
T44	0	493	0	0
T45	0	3612	0	0
T46	0	419	0	0
T47	0	1865	0	0
T48	5484	0	0	0
T49	11865	0	0	0
T50	184743	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313191941	7747	0	0
T45	134216	599	0	0
T47	0	512	0	0
T90	0	308	0	0
T91	0	592	0	0
T92	0	486	0	0
T93	0	199	0	0
T94	0	329	0	0
T95	0	1305	0	0
T96	0	292	0	0
T97	0	389	0	0
T98	33295	0	0	0
T99	153237	0	0	0
T100	68244	0	0	0
T101	1139	0	0	0
T102	49222	0	0	0
T103	209024	0	0	0
T104	7000	0	0	0
T105	3179	0	0	0
T106	5857	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313191941	7002	0	0
T45	134216	508	0	0
T47	0	320	0	0
T90	0	312	0	0
T91	0	593	0	0
T92	0	590	0	0
T93	0	195	0	0
T94	0	262	0	0
T95	0	1207	0	0
T96	0	334	0	0
T97	0	327	0	0
T98	33295	0	0	0
T99	153237	0	0	0
T100	68244	0	0	0
T101	1139	0	0	0
T102	49222	0	0	0
T103	209024	0	0	0
T104	7000	0	0	0
T105	3179	0	0	0
T106	5857	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313191941	7789	0	0
T45	134216	592	0	0
T47	0	471	0	0
T90	0	309	0	0
T91	0	531	0	0
T92	0	604	0	0
T93	0	161	0	0
T94	0	281	0	0
T95	0	1296	0	0
T96	0	432	0	0
T97	0	393	0	0
T98	33295	0	0	0
T99	153237	0	0	0
T100	68244	0	0	0
T101	1139	0	0	0
T102	49222	0	0	0
T103	209024	0	0	0
T104	7000	0	0	0
T105	3179	0	0	0
T106	5857	0	0	0