Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13646627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

56265161

1

T1

116061

T2

739641

T3

2787

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34850217	1			T1	63918		T2	403302		T3	1499
values[0x0]	16167134	1			T1	30632		T2	195427		T3	748
values[0x1]	18894437	1			T1	33177		T2	208739		T3	835

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6799452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63112336

1

T1

121975

T2

773784

T3

2930

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	247293	1			T1	452		T2	3183		T7	539
valid_sources[0x01]	275529	1			T1	492		T2	3209		T7	600
valid_sources[0x02]	238870	1			T1	434		T2	3207		T7	581
valid_sources[0x03]	282556	1			T1	422		T2	3136		T7	583
valid_sources[0x04]	265922	1			T1	471		T2	3201		T7	607
valid_sources[0x05]	275402	1			T1	441		T2	3283		T7	561
valid_sources[0x06]	243608	1			T1	492		T2	3114		T7	611
valid_sources[0x07]	304155	1			T1	467		T2	3069		T7	654
valid_sources[0x08]	330276	1			T1	499		T2	3064		T7	514
valid_sources[0x09]	382270	1			T1	486		T2	3047		T7	552
valid_sources[0x0a]	270301	1			T1	585		T2	3190		T7	545
valid_sources[0x0b]	264408	1			T1	541		T2	3148		T7	534
valid_sources[0x0c]	302327	1			T1	516		T2	3137		T7	581
valid_sources[0x0d]	307806	1			T1	550		T2	3130		T7	562
valid_sources[0x0e]	264641	1			T1	571		T2	3246		T7	606
valid_sources[0x0f]	238479	1			T1	502		T2	3243		T7	560
valid_sources[0x10]	271925	1			T1	473		T2	3084		T7	629
valid_sources[0x11]	325941	1			T1	482		T2	3116		T7	547
valid_sources[0x12]	239765	1			T1	432		T2	3311		T7	672
valid_sources[0x13]	247589	1			T1	507		T2	3084		T7	649
valid_sources[0x14]	250760	1			T1	435		T2	3121		T7	566
valid_sources[0x15]	273263	1			T1	564		T2	3082		T7	595
valid_sources[0x16]	261278	1			T1	445		T2	2963		T7	549
valid_sources[0x17]	262191	1			T1	483		T2	2983		T7	470
valid_sources[0x18]	258584	1			T1	599		T2	3105		T7	530
valid_sources[0x19]	283763	1			T1	547		T2	3150		T7	518
valid_sources[0x1a]	287275	1			T1	593		T2	3141		T7	483
valid_sources[0x1b]	247619	1			T1	512		T2	3254		T7	583
valid_sources[0x1c]	244922	1			T1	469		T2	3214		T7	574
valid_sources[0x1d]	248833	1			T1	581		T2	3199		T7	511
valid_sources[0x1e]	268149	1			T1	510		T2	3206		T7	558
valid_sources[0x1f]	248612	1			T1	428		T2	3030		T7	535
valid_sources[0x20]	267001	1			T1	507		T2	3127		T7	620
valid_sources[0x21]	271851	1			T1	485		T2	3191		T7	524
valid_sources[0x22]	266650	1			T1	538		T2	3195		T7	546
valid_sources[0x23]	259093	1			T1	519		T2	3068		T7	549
valid_sources[0x24]	255726	1			T1	486		T2	3119		T7	554
valid_sources[0x25]	330369	1			T1	528		T2	3237		T7	538
valid_sources[0x26]	277808	1			T1	448		T2	3093		T7	533
valid_sources[0x27]	270670	1			T1	520		T2	3005		T7	568
valid_sources[0x28]	324759	1			T1	499		T2	3287		T7	500
valid_sources[0x29]	338735	1			T1	478		T2	3030		T7	599
valid_sources[0x2a]	306181	1			T1	548		T2	3155		T7	573
valid_sources[0x2b]	269737	1			T1	606		T2	3177		T7	585
valid_sources[0x2c]	253446	1			T1	534		T2	3051		T7	556
valid_sources[0x2d]	275361	1			T1	460		T2	3054		T7	575
valid_sources[0x2e]	253477	1			T1	563		T2	3108		T7	584
valid_sources[0x2f]	258073	1			T1	503		T2	3151		T7	500
valid_sources[0x30]	288218	1			T1	557		T2	3081		T7	521
valid_sources[0x31]	269497	1			T1	386		T2	3190		T7	574
valid_sources[0x32]	302824	1			T1	523		T2	3093		T7	546
valid_sources[0x33]	344705	1			T1	415		T2	3078		T7	498
valid_sources[0x34]	255447	1			T1	541		T2	3054		T7	565
valid_sources[0x35]	262473	1			T1	537		T2	3226		T7	585
valid_sources[0x36]	285930	1			T1	507		T2	3180		T7	542
valid_sources[0x37]	276300	1			T1	567		T2	3258		T7	625
valid_sources[0x38]	259705	1			T1	527		T2	3307		T7	613
valid_sources[0x39]	254759	1			T1	476		T2	3195		T7	585
valid_sources[0x3a]	259975	1			T1	459		T2	3207		T7	523
valid_sources[0x3b]	258800	1			T1	571		T2	3138		T7	589
valid_sources[0x3c]	247981	1			T1	486		T2	2977		T7	520
valid_sources[0x3d]	303548	1			T1	544		T2	3030		T7	558
valid_sources[0x3e]	237671	1			T1	473		T2	3214		T7	472
valid_sources[0x3f]	302743	1			T1	488		T2	3155		T7	531
valid_sources[0x40]	287287	1			T1	545		T2	3278		T7	590
valid_sources[0x41]	351341	1			T1	445		T2	3174		T7	557
valid_sources[0x42]	289995	1			T1	431		T2	3281		T7	500
valid_sources[0x43]	264340	1			T1	498		T2	3198		T3	3066
valid_sources[0x44]	303511	1			T1	490		T2	3208		T7	566
valid_sources[0x45]	316897	1			T1	490		T2	3213		T7	567
valid_sources[0x46]	289631	1			T1	426		T2	3186		T7	549
valid_sources[0x47]	328338	1			T1	571		T2	3212		T7	559
valid_sources[0x48]	249720	1			T1	537		T2	3140		T7	590
valid_sources[0x49]	293969	1			T1	524		T2	3168		T7	549
valid_sources[0x4a]	253202	1			T1	570		T2	3166		T7	561
valid_sources[0x4b]	292122	1			T1	408		T2	3161		T7	580
valid_sources[0x4c]	291498	1			T1	533		T2	3058		T7	576
valid_sources[0x4d]	252933	1			T1	522		T2	3118		T7	537
valid_sources[0x4e]	265355	1			T1	494		T2	3075		T7	538
valid_sources[0x4f]	269141	1			T1	452		T2	3176		T7	566
valid_sources[0x50]	274884	1			T1	519		T2	3106		T7	541
valid_sources[0x51]	266790	1			T1	473		T2	3088		T7	575
valid_sources[0x52]	277537	1			T1	509		T2	3180		T7	654
valid_sources[0x53]	277684	1			T1	422		T2	3290		T7	621
valid_sources[0x54]	281236	1			T1	515		T2	3221		T7	542
valid_sources[0x55]	256598	1			T1	534		T2	3110		T7	548
valid_sources[0x56]	251767	1			T1	423		T2	3181		T7	590
valid_sources[0x57]	245768	1			T1	626		T2	3152		T7	527
valid_sources[0x58]	251491	1			T1	561		T2	3140		T7	636
valid_sources[0x59]	307617	1			T1	529		T2	3195		T7	526
valid_sources[0x5a]	293358	1			T1	522		T2	3210		T7	600
valid_sources[0x5b]	257003	1			T1	482		T2	3018		T7	542
valid_sources[0x5c]	301206	1			T1	578		T2	3263		T7	493
valid_sources[0x5d]	265509	1			T1	416		T2	3221		T7	593
valid_sources[0x5e]	271041	1			T1	511		T2	3110		T7	566
valid_sources[0x5f]	248389	1			T1	460		T2	3102		T7	593
valid_sources[0x60]	261373	1			T1	544		T2	3185		T7	542
valid_sources[0x61]	288017	1			T1	520		T2	3127		T7	515
valid_sources[0x62]	248496	1			T1	516		T2	3077		T7	573
valid_sources[0x63]	280599	1			T1	515		T2	3118		T7	535
valid_sources[0x64]	253004	1			T1	491		T2	3208		T7	649
valid_sources[0x65]	322780	1			T1	487		T2	3011		T7	548
valid_sources[0x66]	297248	1			T1	529		T2	3023		T7	542
valid_sources[0x67]	270753	1			T1	468		T2	3115		T7	593
valid_sources[0x68]	292980	1			T1	509		T2	3342		T7	567
valid_sources[0x69]	258282	1			T1	586		T2	3188		T7	570
valid_sources[0x6a]	253388	1			T1	522		T2	3236		T7	541
valid_sources[0x6b]	286173	1			T1	404		T2	3183		T7	523
valid_sources[0x6c]	257685	1			T1	475		T2	3271		T7	554
valid_sources[0x6d]	266542	1			T1	451		T2	3183		T7	628
valid_sources[0x6e]	273520	1			T1	419		T2	3178		T7	547
valid_sources[0x6f]	239706	1			T1	510		T2	3057		T7	564
valid_sources[0x70]	301637	1			T1	491		T2	3264		T7	561
valid_sources[0x71]	273497	1			T1	508		T2	3108		T7	526
valid_sources[0x72]	271553	1			T1	535		T2	3105		T7	538
valid_sources[0x73]	256629	1			T1	541		T2	3217		T7	522
valid_sources[0x74]	271678	1			T1	481		T2	3067		T7	541
valid_sources[0x75]	239440	1			T1	617		T2	3031		T7	575
valid_sources[0x76]	240651	1			T1	534		T2	3151		T7	579
valid_sources[0x77]	256672	1			T1	540		T2	3080		T7	498
valid_sources[0x78]	275369	1			T1	390		T2	3187		T7	592
valid_sources[0x79]	278058	1			T1	516		T2	3048		T7	533
valid_sources[0x7a]	275591	1			T1	481		T2	3011		T7	663
valid_sources[0x7b]	285721	1			T1	519		T2	3082		T7	532
valid_sources[0x7c]	289707	1			T1	566		T2	3216		T7	582
valid_sources[0x7d]	257592	1			T1	538		T2	3206		T7	619
valid_sources[0x7e]	253603	1			T1	447		T2	3077		T7	500
valid_sources[0x7f]	243138	1			T1	485		T2	3325		T7	573
valid_sources[0x80]	250666	1			T1	566		T2	3186		T7	561

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28031344

1

T1

58025

T2

369318

T3

1338

values[0x0]

all_enables

biggest_size

14117410

1

T1

28894

T2

185465

T3

710

values[0x1]

all_enables

biggest_size

14116407

1

T1

29142

T2

184858

T3

739

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32757	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124511

1

T2

68

T3

1

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46451	1			T2	31		T4	32		T11	13
values[0x0]	53779	1			T1	1		T2	110		T3	1
values[0x1]	57038	1			T1	3		T2	117		T7	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25482	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

131786

1

T1

1

T2

85

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	486	1			T58	2		T27	5		T28	12
valid_sources[0x01]	469	1			T2	1		T9	1		T27	7
valid_sources[0x02]	655	1			T1	4		T27	4		T26	2
valid_sources[0x03]	808	1			T27	6		T26	2		T28	20
valid_sources[0x04]	442	1			T19	1		T27	1		T26	1
valid_sources[0x05]	630	1			T2	1		T11	6		T58	1
valid_sources[0x06]	614	1			T2	2		T11	4		T27	2
valid_sources[0x07]	564	1			T15	4		T58	3		T26	1
valid_sources[0x08]	629	1			T2	1		T56	1		T27	3
valid_sources[0x09]	674	1			T27	1		T26	1		T28	18
valid_sources[0x0a]	532	1			T15	13		T27	2		T46	1
valid_sources[0x0b]	670	1			T2	1		T15	1		T27	2
valid_sources[0x0c]	750	1			T27	1		T26	2		T28	15
valid_sources[0x0d]	546	1			T27	1		T26	1		T28	9
valid_sources[0x0e]	578	1			T2	1		T29	5		T75	2
valid_sources[0x0f]	496	1			T27	4		T26	3		T125	1
valid_sources[0x10]	804	1			T5	1		T28	38		T48	11
valid_sources[0x11]	535	1			T27	4		T28	19		T48	14
valid_sources[0x12]	524	1			T6	22		T58	1		T30	2
valid_sources[0x13]	682	1			T2	1		T58	4		T27	5
valid_sources[0x14]	623	1			T2	2		T23	44		T27	2
valid_sources[0x15]	493	1			T28	10		T48	9		T126	1
valid_sources[0x16]	621	1			T5	3		T27	5		T26	1
valid_sources[0x17]	485	1			T27	3		T28	9		T127	1
valid_sources[0x18]	527	1			T19	1		T27	3		T46	1
valid_sources[0x19]	626	1			T2	1		T5	1		T27	3
valid_sources[0x1a]	572	1			T2	2		T8	7		T15	1
valid_sources[0x1b]	742	1			T27	1		T28	10		T48	14
valid_sources[0x1c]	479	1			T5	2		T28	31		T80	1
valid_sources[0x1d]	584	1			T2	8		T57	1		T27	3
valid_sources[0x1e]	968	1			T2	2		T27	5		T28	21
valid_sources[0x1f]	528	1			T14	1		T30	1		T27	1
valid_sources[0x20]	620	1			T27	5		T26	3		T28	18
valid_sources[0x21]	645	1			T27	3		T124	2		T26	2
valid_sources[0x22]	683	1			T2	2		T11	2		T58	2
valid_sources[0x23]	570	1			T11	4		T27	1		T26	1
valid_sources[0x24]	564	1			T27	4		T46	1		T26	2
valid_sources[0x25]	622	1			T27	3		T26	2		T28	7
valid_sources[0x26]	444	1			T27	1		T26	2		T28	15
valid_sources[0x27]	567	1			T2	2		T10	1		T27	3
valid_sources[0x28]	550	1			T15	43		T26	6		T28	13
valid_sources[0x29]	571	1			T27	1		T46	3		T26	3
valid_sources[0x2a]	673	1			T27	7		T124	4		T26	3
valid_sources[0x2b]	463	1			T46	1		T26	1		T28	21
valid_sources[0x2c]	491	1			T73	1		T27	2		T28	16
valid_sources[0x2d]	635	1			T2	1		T30	1		T27	4
valid_sources[0x2e]	822	1			T27	5		T125	1		T28	18
valid_sources[0x2f]	581	1			T55	4		T26	2		T28	20
valid_sources[0x30]	657	1			T2	2		T20	1		T27	3
valid_sources[0x31]	563	1			T27	1		T124	10		T26	1
valid_sources[0x32]	555	1			T5	1		T27	6		T26	2
valid_sources[0x33]	557	1			T27	1		T28	8		T83	1
valid_sources[0x34]	520	1			T4	3		T27	1		T26	1
valid_sources[0x35]	545	1			T2	2		T27	4		T46	3
valid_sources[0x36]	655	1			T2	3		T4	11		T30	5
valid_sources[0x37]	654	1			T2	5		T30	3		T27	5
valid_sources[0x38]	531	1			T27	1		T28	18		T128	7
valid_sources[0x39]	680	1			T4	13		T27	2		T28	23
valid_sources[0x3a]	543	1			T2	1		T56	3		T27	4
valid_sources[0x3b]	660	1			T58	1		T27	2		T26	1
valid_sources[0x3c]	513	1			T2	3		T9	1		T27	3
valid_sources[0x3d]	599	1			T2	10		T30	2		T75	5
valid_sources[0x3e]	699	1			T30	6		T74	1		T27	4
valid_sources[0x3f]	534	1			T27	1		T26	2		T28	36
valid_sources[0x40]	642	1			T27	1		T26	3		T125	1
valid_sources[0x41]	595	1			T15	1		T27	1		T28	13
valid_sources[0x42]	516	1			T4	1		T58	1		T27	2
valid_sources[0x43]	580	1			T15	39		T72	1		T74	2
valid_sources[0x44]	558	1			T27	4		T28	16		T48	23
valid_sources[0x45]	557	1			T6	11		T27	5		T26	7
valid_sources[0x46]	466	1			T15	1		T27	1		T26	1
valid_sources[0x47]	434	1			T2	2		T15	3		T32	1
valid_sources[0x48]	505	1			T2	1		T5	1		T56	1
valid_sources[0x49]	524	1			T2	1		T27	2		T46	1
valid_sources[0x4a]	618	1			T2	6		T15	7		T75	1
valid_sources[0x4b]	575	1			T30	6		T27	5		T28	10
valid_sources[0x4c]	618	1			T27	1		T26	2		T28	29
valid_sources[0x4d]	731	1			T2	15		T30	1		T26	2
valid_sources[0x4e]	658	1			T30	1		T27	4		T26	2
valid_sources[0x4f]	571	1			T27	4		T26	1		T129	4
valid_sources[0x50]	429	1			T2	1		T26	1		T28	4
valid_sources[0x51]	612	1			T2	1		T29	4		T30	1
valid_sources[0x52]	753	1			T15	2		T27	4		T26	1
valid_sources[0x53]	709	1			T58	1		T27	1		T28	19
valid_sources[0x54]	486	1			T27	2		T28	17		T48	17
valid_sources[0x55]	574	1			T5	1		T27	1		T26	1
valid_sources[0x56]	593	1			T2	8		T29	1		T30	5
valid_sources[0x57]	522	1			T2	7		T6	3		T27	5
valid_sources[0x58]	597	1			T27	4		T46	2		T47	1
valid_sources[0x59]	449	1			T2	2		T30	8		T27	3
valid_sources[0x5a]	768	1			T15	294		T27	1		T46	2
valid_sources[0x5b]	726	1			T11	1		T45	6		T27	3
valid_sources[0x5c]	652	1			T9	2		T46	1		T28	13
valid_sources[0x5d]	533	1			T15	44		T6	7		T27	1
valid_sources[0x5e]	826	1			T2	1		T9	1		T19	1
valid_sources[0x5f]	605	1			T27	3		T26	3		T28	14
valid_sources[0x60]	478	1			T2	1		T27	3		T46	2
valid_sources[0x61]	752	1			T56	1		T27	1		T26	2
valid_sources[0x62]	550	1			T4	12		T27	4		T47	1
valid_sources[0x63]	571	1			T27	3		T26	4		T28	6
valid_sources[0x64]	746	1			T2	3		T30	6		T27	3
valid_sources[0x65]	671	1			T29	1		T30	1		T27	2
valid_sources[0x66]	636	1			T30	1		T27	1		T46	1
valid_sources[0x67]	494	1			T15	3		T130	20		T27	2
valid_sources[0x68]	540	1			T2	1		T27	5		T26	2
valid_sources[0x69]	508	1			T30	1		T27	2		T28	26
valid_sources[0x6a]	486	1			T2	3		T27	5		T46	1
valid_sources[0x6b]	578	1			T27	4		T26	2		T131	1
valid_sources[0x6c]	654	1			T15	3		T30	2		T27	4
valid_sources[0x6d]	574	1			T27	1		T26	1		T47	1
valid_sources[0x6e]	676	1			T6	1		T30	3		T27	3
valid_sources[0x6f]	624	1			T27	1		T131	1		T28	32
valid_sources[0x70]	920	1			T27	2		T26	2		T28	20
valid_sources[0x71]	453	1			T2	9		T27	1		T26	1
valid_sources[0x72]	587	1			T30	3		T27	2		T26	1
valid_sources[0x73]	707	1			T11	17		T15	1		T30	3
valid_sources[0x74]	488	1			T58	1		T27	8		T26	2
valid_sources[0x75]	584	1			T9	1		T30	1		T27	4
valid_sources[0x76]	668	1			T2	7		T27	1		T28	30
valid_sources[0x77]	677	1			T15	1		T27	2		T26	2
valid_sources[0x78]	463	1			T28	21		T109	2		T128	1
valid_sources[0x79]	536	1			T27	3		T28	19		T48	15
valid_sources[0x7a]	666	1			T9	1		T15	100		T71	2
valid_sources[0x7b]	531	1			T27	4		T26	4		T28	12
valid_sources[0x7c]	862	1			T2	2		T5	2		T15	3
valid_sources[0x7d]	483	1			T29	1		T27	2		T132	1
valid_sources[0x7e]	562	1			T27	5		T26	1		T28	11
valid_sources[0x7f]	726	1			T2	5		T11	13		T59	4
valid_sources[0x80]	484	1			T56	2		T23	4		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

34518

1

T2

13

T4

15

T11

7

values[0x0]

all_enables

biggest_size

45962

1

T2

34

T3

1

T7

1

values[0x1]

all_enables

biggest_size

44031

1

T2

21

T7

2

T9

2