Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13347559

1

T1

11666

T2

54366

T3

295

full_word

51588932

1

T1

116061

T2

606951

T3

2787

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64936211	1			T1	127727		T2	661317		T3	3082
auto[TlIntgErrCmd]	85	1			T100	4		T101	6		T102	7
auto[TlIntgErrData]	98	1			T100	4		T101	6		T102	8
auto[TlIntgErrBoth]	97	1			T100	2		T101	8		T102	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29832061

1

T1

63918

T2

257151

T3

1499

auto[1]

35104430

1

T1

63809

T2

404166

T3

1583

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6393365	1			T1	5893		T2	20523		T3	161
auto[TlIntgErrNone]	partial	auto[1]	6953945	1			T1	5773		T2	33843		T3	134
auto[TlIntgErrNone]	full_word	auto[0]	23438566	1			T1	58025		T2	236628		T3	1338
auto[TlIntgErrNone]	full_word	auto[1]	28150335	1			T1	58036		T2	370323		T3	1449
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T100	1		T101	3		T102	3
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T100	3		T101	2		T102	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T113	2		T118	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T101	1		T102	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T100	2		T101	3		T102	4
auto[TlIntgErrData]	partial	auto[1]	39	1			T100	1		T101	2		T102	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T100	1		T119	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T101	1		T110	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T100	1		T101	2		T102	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T100	1		T101	6		T102	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T116	1		T117	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T113	1		T117	1		T121	1