Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	634741	1			T2	9119		T4	23		T12	32712
auto[1]	10395845	1			T1	53615		T2	2031		T7	32096
auto[2]	514743	1			T2	8131		T4	35		T12	27827
auto[3]	10288909	1			T1	53565		T2	1288		T3	1

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13815032	1			T1	88595		T2	16032		T3	1
auto[1]	2121612	1			T1	8833		T2	2163		T7	5530
auto[2]	2110327	1			T1	8920		T2	2134		T7	5405
auto[3]	3787267	1			T1	832		T2	240		T7	533

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7984258

1

T2

20547

T3

1

T7

64218

auto[1]

13849980

1

T1

107180

T2

22

T7

72

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	211493	1			T2	7567		T4	21		T15	3
auto[0]	auto[0]	auto[1]	22194	1			T2	713		T4	2		T15	1
auto[0]	auto[0]	auto[2]	22090	1			T2	758		T22	193		T23	92
auto[0]	auto[0]	auto[3]	9437	1			T2	72		T59	2		T22	20
auto[0]	auto[1]	auto[0]	3069458	1			T2	1161		T7	26373		T4	5
auto[0]	auto[1]	auto[1]	319716	1			T2	717		T7	2777		T4	3
auto[0]	auto[1]	auto[2]	310285	1			T2	96		T7	2657		T10	32
auto[0]	auto[1]	auto[3]	69499	1			T2	53		T7	251		T10	7
auto[0]	auto[2]	auto[0]	173349	1			T2	6738		T4	30		T15	7
auto[0]	auto[2]	auto[1]	18527	1			T2	676		T4	3		T15	1
auto[0]	auto[2]	auto[2]	19369	1			T2	650		T4	2		T22	138
auto[0]	auto[2]	auto[3]	7527	1			T2	61		T59	2		T22	21
auto[0]	auto[3]	auto[0]	3034618	1			T2	547		T3	1		T7	26392
auto[0]	auto[3]	auto[1]	306461	1			T2	55		T7	2744		T10	17
auto[0]	auto[3]	auto[2]	317811	1			T2	629		T7	2743		T4	3
auto[0]	auto[3]	auto[3]	72424	1			T2	54		T7	281		T10	5
auto[1]	auto[0]	auto[0]	12383	1			T2	9		T12	1138		T55	591
auto[1]	auto[0]	auto[1]	55315	1			T12	4859		T55	2708		T59	3822
auto[1]	auto[0]	auto[2]	55226	1			T12	4939		T55	2746		T59	3844
auto[1]	auto[0]	auto[3]	246603	1			T12	21776		T55	12426		T59	17153
auto[1]	auto[1]	auto[0]	3652024	1			T1	44294		T2	4		T7	29
auto[1]	auto[1]	auto[1]	691123	1			T1	4382		T7	6		T11	1
auto[1]	auto[1]	auto[2]	664107	1			T1	4529		T7	2		T12	751
auto[1]	auto[1]	auto[3]	1619633	1			T1	410		T7	1		T12	21980
auto[1]	auto[2]	auto[0]	11388	1			T2	4		T12	996		T55	615
auto[1]	auto[2]	auto[1]	49662	1			T2	2		T12	4418		T55	2574
auto[1]	auto[2]	auto[2]	43018	1			T12	4110		T55	1910		T59	2569
auto[1]	auto[2]	auto[3]	191903	1			T12	18303		T55	8354		T59	11506
auto[1]	auto[3]	auto[0]	3650319	1			T1	44301		T2	2		T7	28
auto[1]	auto[3]	auto[1]	658614	1			T1	4451		T7	3		T12	365
auto[1]	auto[3]	auto[2]	678421	1			T1	4391		T2	1		T7	3
auto[1]	auto[3]	auto[3]	1570241	1			T1	422		T12	18911		T60	571