Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	301192992	114160	0	0
ctrl_regwen_rd_A	301192992	5092	0	0
exec_rd_A	301192992	4617	0	0
exec_regwen_rd_A	301192992	5013	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301192992	114160	0	0
T6	60824	0	0	0
T15	24970	577	0	0
T19	1191	0	0	0
T20	949	0	0	0
T27	0	431	0	0
T28	0	3914	0	0
T29	928958	0	0	0
T48	0	5538	0	0
T49	0	885	0	0
T50	0	4229	0	0
T51	0	1033	0	0
T52	0	2524	0	0
T53	0	1278	0	0
T54	0	2867	0	0
T55	126086	0	0	0
T56	104810	0	0	0
T57	9004	0	0	0
T58	88168	0	0	0
T59	172075	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301192992	5092	0	0
T6	60824	0	0	0
T15	24970	194	0	0
T19	1191	0	0	0
T20	949	0	0	0
T27	0	67	0	0
T29	928958	0	0	0
T52	0	261	0	0
T53	0	257	0	0
T55	126086	0	0	0
T56	104810	0	0	0
T57	9004	0	0	0
T58	88168	0	0	0
T59	172075	0	0	0
T103	0	450	0	0
T104	0	601	0	0
T105	0	348	0	0
T106	0	602	0	0
T107	0	74	0	0
T108	0	361	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301192992	4617	0	0
T6	60824	0	0	0
T15	24970	225	0	0
T19	1191	0	0	0
T20	949	0	0	0
T27	0	37	0	0
T29	928958	0	0	0
T52	0	259	0	0
T53	0	249	0	0
T55	126086	0	0	0
T56	104810	0	0	0
T57	9004	0	0	0
T58	88168	0	0	0
T59	172075	0	0	0
T103	0	273	0	0
T104	0	611	0	0
T105	0	313	0	0
T106	0	473	0	0
T107	0	85	0	0
T108	0	243	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301192992	5013	0	0
T6	60824	0	0	0
T15	24970	203	0	0
T19	1191	0	0	0
T20	949	0	0	0
T27	0	53	0	0
T29	928958	0	0	0
T52	0	250	0	0
T53	0	298	0	0
T55	126086	0	0	0
T56	104810	0	0	0
T57	9004	0	0	0
T58	88168	0	0	0
T59	172075	0	0	0
T103	0	407	0	0
T104	0	560	0	0
T105	0	430	0	0
T106	0	531	0	0
T107	0	55	0	0
T108	0	417	0	0