Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14106215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61033691

1

T1

3071

T2

417

T3

25569

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37456674	1			T1	1024		T2	1088		T3	70309
values[0x0]	17435557	1			T1	1033		T2	389		T3	23562
values[0x1]	20247675	1			T1	1014		T2	734		T3	46635

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7029110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68110796

1

T1

3071

T2

1327

T3

83241

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	276481	1			T1	18		T3	575		T4	764
valid_sources[0x01]	245877	1			T1	28		T2	8		T3	546
valid_sources[0x02]	271178	1			T1	7		T3	507		T4	833
valid_sources[0x03]	296793	1			T1	7		T2	9		T3	577
valid_sources[0x04]	272677	1			T1	9		T2	24		T3	562
valid_sources[0x05]	296523	1			T1	10		T3	536		T4	807
valid_sources[0x06]	334939	1			T1	17		T3	524		T4	846
valid_sources[0x07]	253951	1			T1	18		T2	28		T3	538
valid_sources[0x08]	296510	1			T1	11		T2	15		T3	534
valid_sources[0x09]	257047	1			T1	12		T3	564		T4	862
valid_sources[0x0a]	284698	1			T1	15		T2	44		T3	530
valid_sources[0x0b]	313575	1			T1	15		T3	537		T4	815
valid_sources[0x0c]	297875	1			T1	7		T3	530		T4	884
valid_sources[0x0d]	259593	1			T1	14		T3	615		T4	761
valid_sources[0x0e]	284515	1			T1	12		T3	529		T4	789
valid_sources[0x0f]	273075	1			T1	20		T3	536		T4	685
valid_sources[0x10]	289159	1			T1	8		T3	527		T4	786
valid_sources[0x11]	331345	1			T1	9		T3	568		T4	794
valid_sources[0x12]	294722	1			T1	10		T3	541		T4	693
valid_sources[0x13]	267088	1			T1	13		T3	567		T4	733
valid_sources[0x14]	326399	1			T1	18		T3	570		T4	727
valid_sources[0x15]	251364	1			T1	13		T2	1		T3	555
valid_sources[0x16]	279317	1			T1	11		T3	537		T4	820
valid_sources[0x17]	324336	1			T1	7		T3	613		T4	975
valid_sources[0x18]	300419	1			T1	19		T3	564		T4	987
valid_sources[0x19]	280628	1			T1	14		T2	7		T3	582
valid_sources[0x1a]	332512	1			T1	14		T2	13		T3	575
valid_sources[0x1b]	301835	1			T1	17		T2	6		T3	496
valid_sources[0x1c]	286372	1			T1	14		T2	2		T3	551
valid_sources[0x1d]	251693	1			T1	14		T2	38		T3	584
valid_sources[0x1e]	310264	1			T1	8		T3	585		T4	1001
valid_sources[0x1f]	252677	1			T1	15		T2	4		T3	624
valid_sources[0x20]	314761	1			T1	9		T2	7		T3	537
valid_sources[0x21]	309144	1			T1	18		T2	1		T3	523
valid_sources[0x22]	266893	1			T1	11		T2	21		T3	552
valid_sources[0x23]	331497	1			T1	6		T2	1		T3	590
valid_sources[0x24]	303777	1			T1	16		T2	8		T3	555
valid_sources[0x25]	289701	1			T1	14		T2	34		T3	546
valid_sources[0x26]	258835	1			T1	10		T2	14		T3	569
valid_sources[0x27]	288749	1			T1	11		T2	13		T3	581
valid_sources[0x28]	270165	1			T1	13		T3	533		T4	655
valid_sources[0x29]	304246	1			T1	14		T2	8		T3	553
valid_sources[0x2a]	300865	1			T1	8		T2	40		T3	584
valid_sources[0x2b]	271285	1			T1	16		T3	614		T4	967
valid_sources[0x2c]	289932	1			T1	7		T2	24		T3	567
valid_sources[0x2d]	272289	1			T1	13		T2	4		T3	525
valid_sources[0x2e]	321490	1			T1	13		T2	32		T3	520
valid_sources[0x2f]	369628	1			T1	13		T2	3		T3	572
valid_sources[0x30]	345548	1			T1	20		T3	549		T4	894
valid_sources[0x31]	329121	1			T1	15		T3	556		T4	1040
valid_sources[0x32]	346721	1			T1	12		T3	555		T4	1224
valid_sources[0x33]	271878	1			T1	13		T2	2		T3	538
valid_sources[0x34]	323311	1			T1	17		T3	534		T4	654
valid_sources[0x35]	288285	1			T1	16		T2	3		T3	555
valid_sources[0x36]	283922	1			T1	11		T3	525		T4	833
valid_sources[0x37]	275949	1			T1	9		T3	578		T4	992
valid_sources[0x38]	278176	1			T1	9		T3	529		T4	879
valid_sources[0x39]	377852	1			T1	12		T3	513		T4	871
valid_sources[0x3a]	275066	1			T1	13		T2	3		T3	551
valid_sources[0x3b]	260035	1			T1	12		T2	22		T3	557
valid_sources[0x3c]	301397	1			T1	11		T3	509		T4	865
valid_sources[0x3d]	259122	1			T1	9		T3	527		T4	706
valid_sources[0x3e]	262973	1			T1	9		T2	3		T3	583
valid_sources[0x3f]	371725	1			T1	11		T3	526		T4	858
valid_sources[0x40]	294914	1			T1	8		T3	543		T4	703
valid_sources[0x41]	301396	1			T1	9		T3	537		T4	997
valid_sources[0x42]	251905	1			T1	15		T2	44		T3	488
valid_sources[0x43]	334238	1			T1	5		T3	508		T4	1104
valid_sources[0x44]	305831	1			T1	4		T2	50		T3	566
valid_sources[0x45]	346739	1			T1	10		T3	553		T4	679
valid_sources[0x46]	342447	1			T1	9		T3	516		T4	1040
valid_sources[0x47]	288020	1			T1	14		T3	531		T4	760
valid_sources[0x48]	276363	1			T1	12		T3	514		T4	644
valid_sources[0x49]	266684	1			T1	6		T3	536		T4	760
valid_sources[0x4a]	253130	1			T1	14		T2	37		T3	560
valid_sources[0x4b]	256477	1			T1	9		T3	574		T4	1164
valid_sources[0x4c]	262879	1			T1	5		T3	583		T4	674
valid_sources[0x4d]	250232	1			T1	15		T3	590		T4	612
valid_sources[0x4e]	285851	1			T1	9		T3	528		T4	857
valid_sources[0x4f]	280232	1			T1	10		T2	12		T3	538
valid_sources[0x50]	306802	1			T1	9		T2	4		T3	538
valid_sources[0x51]	246107	1			T1	11		T3	504		T4	951
valid_sources[0x52]	276926	1			T1	7		T2	2		T3	567
valid_sources[0x53]	348572	1			T1	12		T2	4		T3	558
valid_sources[0x54]	259767	1			T1	12		T3	504		T4	719
valid_sources[0x55]	274854	1			T1	13		T2	32		T3	555
valid_sources[0x56]	255803	1			T1	9		T3	556		T4	710
valid_sources[0x57]	256974	1			T1	10		T2	64		T3	569
valid_sources[0x58]	280329	1			T1	16		T3	549		T4	661
valid_sources[0x59]	259789	1			T1	21		T3	478		T4	933
valid_sources[0x5a]	323975	1			T1	11		T3	540		T4	863
valid_sources[0x5b]	304404	1			T1	18		T2	64		T3	569
valid_sources[0x5c]	290472	1			T1	15		T3	600		T4	697
valid_sources[0x5d]	278595	1			T1	12		T3	564		T4	669
valid_sources[0x5e]	302404	1			T1	16		T3	570		T4	572
valid_sources[0x5f]	280446	1			T1	14		T2	38		T3	575
valid_sources[0x60]	264336	1			T1	13		T2	12		T3	548
valid_sources[0x61]	252438	1			T1	9		T3	540		T4	1096
valid_sources[0x62]	287079	1			T1	15		T2	18		T3	531
valid_sources[0x63]	295706	1			T1	8		T2	1		T3	525
valid_sources[0x64]	309343	1			T1	5		T3	511		T4	914
valid_sources[0x65]	258825	1			T1	6		T3	572		T4	717
valid_sources[0x66]	269492	1			T1	12		T2	7		T3	571
valid_sources[0x67]	400955	1			T1	11		T2	6		T3	527
valid_sources[0x68]	313540	1			T1	7		T3	538		T4	671
valid_sources[0x69]	283007	1			T1	16		T2	5		T3	535
valid_sources[0x6a]	296619	1			T1	17		T3	569		T4	947
valid_sources[0x6b]	310080	1			T1	9		T2	2		T3	575
valid_sources[0x6c]	265527	1			T1	26		T2	19		T3	570
valid_sources[0x6d]	301035	1			T1	10		T3	535		T4	899
valid_sources[0x6e]	296114	1			T1	9		T2	20		T3	546
valid_sources[0x6f]	269318	1			T1	10		T3	534		T4	706
valid_sources[0x70]	352377	1			T1	11		T2	42		T3	509
valid_sources[0x71]	273482	1			T1	9		T3	522		T4	883
valid_sources[0x72]	260334	1			T1	13		T2	45		T3	588
valid_sources[0x73]	252568	1			T1	6		T2	16		T3	538
valid_sources[0x74]	265494	1			T1	8		T2	25		T3	561
valid_sources[0x75]	243177	1			T1	15		T3	566		T4	862
valid_sources[0x76]	270916	1			T1	11		T3	576		T4	731
valid_sources[0x77]	243739	1			T1	7		T3	530		T4	790
valid_sources[0x78]	363869	1			T1	23		T3	577		T4	664
valid_sources[0x79]	320692	1			T1	16		T3	610		T4	880
valid_sources[0x7a]	284841	1			T1	5		T2	31		T3	529
valid_sources[0x7b]	321427	1			T1	9		T3	544		T4	952
valid_sources[0x7c]	284150	1			T1	4		T2	6		T3	496
valid_sources[0x7d]	284847	1			T1	11		T2	16		T3	608
valid_sources[0x7e]	260451	1			T1	14		T3	521		T4	569
valid_sources[0x7f]	294348	1			T1	13		T2	31		T3	566
valid_sources[0x80]	276099	1			T1	11		T3	556		T4	806

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30409868

1

T1

1024

T2

193

T3

12685

values[0x0]

all_enables

biggest_size

15317577

1

T1

1033

T2

106

T3

6435

values[0x1]

all_enables

biggest_size

15306246

1

T1

1014

T2

118

T3

6449

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32807	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124567

1

T4

5

T5

2

T11

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46146	1			T13	13		T18	283		T19	14
values[0x0]	53722	1			T4	7		T6	1		T5	2
values[0x1]	57506	1			T2	2		T3	6		T4	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25016	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

132358

1

T2

1

T3

2

T4

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	508	1			T23	3		T18	5		T16	8
valid_sources[0x01]	573	1			T18	6		T19	2		T16	10
valid_sources[0x02]	469	1			T13	1		T18	4		T19	1
valid_sources[0x03]	1036	1			T18	3		T19	1		T16	2
valid_sources[0x04]	505	1			T18	2		T19	1		T16	10
valid_sources[0x05]	562	1			T13	1		T18	3		T16	8
valid_sources[0x06]	585	1			T18	5		T16	7		T36	1
valid_sources[0x07]	541	1			T18	3		T19	1		T16	12
valid_sources[0x08]	568	1			T18	2		T19	1		T16	11
valid_sources[0x09]	566	1			T18	3		T16	14		T26	1
valid_sources[0x0a]	533	1			T13	1		T18	6		T19	1
valid_sources[0x0b]	572	1			T18	3		T16	14		T43	14
valid_sources[0x0c]	566	1			T18	6		T19	1		T16	9
valid_sources[0x0d]	544	1			T18	3		T16	9		T7	10
valid_sources[0x0e]	718	1			T4	1		T18	2		T16	10
valid_sources[0x0f]	582	1			T3	6		T18	6		T16	11
valid_sources[0x10]	534	1			T18	6		T52	2		T16	5
valid_sources[0x11]	695	1			T18	1		T16	10		T36	1
valid_sources[0x12]	544	1			T18	5		T16	19		T8	1
valid_sources[0x13]	616	1			T18	6		T19	1		T16	10
valid_sources[0x14]	587	1			T18	6		T16	14		T26	17
valid_sources[0x15]	667	1			T13	1		T18	2		T16	7
valid_sources[0x16]	585	1			T13	1		T18	3		T16	11
valid_sources[0x17]	486	1			T18	1		T16	10		T26	1
valid_sources[0x18]	782	1			T18	5		T19	1		T16	11
valid_sources[0x19]	576	1			T18	8		T16	14		T43	17
valid_sources[0x1a]	575	1			T23	1		T18	3		T16	10
valid_sources[0x1b]	874	1			T13	1		T18	2		T16	7
valid_sources[0x1c]	679	1			T13	2		T18	9		T16	7
valid_sources[0x1d]	633	1			T18	2		T16	11		T36	1
valid_sources[0x1e]	514	1			T13	1		T18	4		T16	12
valid_sources[0x1f]	567	1			T23	3		T18	4		T16	7
valid_sources[0x20]	629	1			T18	5		T16	8		T36	1
valid_sources[0x21]	689	1			T5	1		T23	2		T18	4
valid_sources[0x22]	527	1			T18	2		T16	10		T36	1
valid_sources[0x23]	878	1			T18	6		T16	8		T43	10
valid_sources[0x24]	496	1			T18	1		T16	7		T7	48
valid_sources[0x25]	494	1			T13	1		T18	4		T16	8
valid_sources[0x26]	691	1			T18	4		T16	6		T36	2
valid_sources[0x27]	686	1			T13	3		T18	3		T16	9
valid_sources[0x28]	553	1			T18	1		T16	2		T35	2
valid_sources[0x29]	454	1			T18	7		T16	11		T43	15
valid_sources[0x2a]	560	1			T18	8		T16	12		T43	16
valid_sources[0x2b]	525	1			T18	5		T19	1		T16	18
valid_sources[0x2c]	612	1			T18	7		T16	9		T40	1
valid_sources[0x2d]	644	1			T4	1		T13	1		T18	5
valid_sources[0x2e]	476	1			T18	3		T16	9		T26	4
valid_sources[0x2f]	566	1			T18	4		T16	7		T43	26
valid_sources[0x30]	580	1			T18	4		T19	1		T16	8
valid_sources[0x31]	637	1			T4	1		T18	6		T16	8
valid_sources[0x32]	1062	1			T18	7		T16	10		T26	1
valid_sources[0x33]	501	1			T18	4		T16	1		T43	18
valid_sources[0x34]	591	1			T13	1		T18	5		T16	17
valid_sources[0x35]	547	1			T18	2		T19	1		T16	12
valid_sources[0x36]	577	1			T6	1		T18	1		T16	9
valid_sources[0x37]	614	1			T18	5		T16	6		T8	1
valid_sources[0x38]	732	1			T18	4		T16	4		T8	1
valid_sources[0x39]	640	1			T18	6		T19	1		T16	6
valid_sources[0x3a]	524	1			T13	2		T18	6		T19	1
valid_sources[0x3b]	794	1			T18	1		T16	11		T36	1
valid_sources[0x3c]	679	1			T18	5		T16	7		T36	1
valid_sources[0x3d]	575	1			T18	3		T19	1		T16	16
valid_sources[0x3e]	654	1			T18	5		T16	6		T43	23
valid_sources[0x3f]	523	1			T4	1		T16	10		T8	1
valid_sources[0x40]	623	1			T18	6		T19	2		T16	13
valid_sources[0x41]	564	1			T18	4		T16	8		T43	13
valid_sources[0x42]	611	1			T18	5		T19	1		T16	13
valid_sources[0x43]	622	1			T18	4		T16	7		T8	1
valid_sources[0x44]	719	1			T4	1		T18	6		T16	10
valid_sources[0x45]	743	1			T18	9		T16	10		T8	1
valid_sources[0x46]	475	1			T13	1		T18	4		T16	5
valid_sources[0x47]	660	1			T18	7		T16	5		T26	1
valid_sources[0x48]	558	1			T18	9		T52	2		T16	14
valid_sources[0x49]	803	1			T18	8		T16	7		T15	1
valid_sources[0x4a]	507	1			T18	8		T16	15		T43	11
valid_sources[0x4b]	454	1			T18	5		T19	3		T16	7
valid_sources[0x4c]	515	1			T18	7		T16	4		T36	1
valid_sources[0x4d]	651	1			T4	1		T18	4		T16	11
valid_sources[0x4e]	509	1			T13	1		T18	3		T19	1
valid_sources[0x4f]	508	1			T4	1		T18	5		T16	8
valid_sources[0x50]	534	1			T18	3		T16	9		T43	18
valid_sources[0x51]	685	1			T13	1		T18	4		T16	7
valid_sources[0x52]	537	1			T18	2		T16	10		T15	1
valid_sources[0x53]	714	1			T18	2		T16	8		T43	8
valid_sources[0x54]	744	1			T18	9		T16	11		T26	1
valid_sources[0x55]	630	1			T13	1		T18	3		T16	9
valid_sources[0x56]	596	1			T13	1		T18	6		T16	11
valid_sources[0x57]	488	1			T13	1		T18	4		T16	5
valid_sources[0x58]	591	1			T18	7		T19	1		T16	12
valid_sources[0x59]	548	1			T18	5		T16	9		T43	13
valid_sources[0x5a]	535	1			T13	2		T18	4		T16	15
valid_sources[0x5b]	581	1			T13	1		T18	2		T16	4
valid_sources[0x5c]	575	1			T18	8		T16	10		T26	43
valid_sources[0x5d]	462	1			T18	2		T16	9		T8	1
valid_sources[0x5e]	642	1			T18	5		T16	5		T43	10
valid_sources[0x5f]	947	1			T13	1		T18	10		T16	5
valid_sources[0x60]	534	1			T18	5		T16	7		T15	2
valid_sources[0x61]	578	1			T18	7		T16	5		T8	1
valid_sources[0x62]	509	1			T18	5		T16	6		T8	1
valid_sources[0x63]	649	1			T18	8		T16	7		T7	42
valid_sources[0x64]	518	1			T23	1		T18	5		T16	10
valid_sources[0x65]	591	1			T13	1		T18	5		T16	7
valid_sources[0x66]	558	1			T4	1		T18	5		T19	1
valid_sources[0x67]	624	1			T18	7		T16	7		T35	1
valid_sources[0x68]	668	1			T18	3		T19	1		T16	10
valid_sources[0x69]	530	1			T18	7		T16	9		T43	19
valid_sources[0x6a]	489	1			T18	4		T16	10		T43	17
valid_sources[0x6b]	723	1			T18	3		T16	8		T43	17
valid_sources[0x6c]	623	1			T18	1		T19	1		T16	17
valid_sources[0x6d]	825	1			T18	6		T16	7		T27	2
valid_sources[0x6e]	607	1			T18	2		T16	7		T36	1
valid_sources[0x6f]	468	1			T13	1		T18	3		T16	7
valid_sources[0x70]	607	1			T18	8		T16	11		T15	1
valid_sources[0x71]	551	1			T4	1		T18	5		T16	7
valid_sources[0x72]	723	1			T18	1		T19	1		T16	5
valid_sources[0x73]	861	1			T13	1		T18	3		T16	7
valid_sources[0x74]	547	1			T18	7		T16	14		T36	1
valid_sources[0x75]	558	1			T18	5		T16	10		T26	1
valid_sources[0x76]	717	1			T13	1		T18	1		T16	9
valid_sources[0x77]	559	1			T18	4		T16	5		T43	12
valid_sources[0x78]	600	1			T4	1		T18	1		T19	1
valid_sources[0x79]	542	1			T13	1		T18	4		T16	6
valid_sources[0x7a]	597	1			T13	1		T18	3		T16	7
valid_sources[0x7b]	475	1			T18	3		T16	7		T43	15
valid_sources[0x7c]	764	1			T18	5		T19	1		T16	14
valid_sources[0x7d]	758	1			T18	7		T16	13		T8	1
valid_sources[0x7e]	524	1			T18	5		T16	13		T43	8
valid_sources[0x7f]	496	1			T13	1		T18	5		T16	5
valid_sources[0x80]	864	1			T18	2		T19	1		T16	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

34575

1

T13

8

T18

252

T19

10

values[0x0]

all_enables

biggest_size

45866

1

T4

3

T5

2

T13

9

values[0x1]

all_enables

biggest_size

44126

1

T4

2

T11

1

T13

3