Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13775036

1

T2

1794

T3

114937

T4

19394

full_word

55977689

1

T1

3071

T2

417

T3

25569

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69752435	1			T1	3071		T2	2211		T3	140506
auto[TlIntgErrCmd]	91	1			T96	3		T97	7		T98	4
auto[TlIntgErrData]	94	1			T96	5		T97	4		T98	1
auto[TlIntgErrBoth]	105	1			T96	2		T97	9		T98	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32028722

1

T1

1024

T2

1088

T3

70309

auto[1]

37724003

1

T1

2047

T2

1123

T3

70197

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6586398	1			T2	895		T3	57624		T4	9717
auto[TlIntgErrNone]	partial	auto[1]	7188382	1			T2	899		T3	57313		T4	9677
auto[TlIntgErrNone]	full_word	auto[0]	25442200	1			T1	1024		T2	193		T3	12685
auto[TlIntgErrNone]	full_word	auto[1]	30535455	1			T1	2047		T2	224		T3	12884
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T96	3		T97	3		T98	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T97	2		T98	3		T120	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T120	1		T121	1		T127	2
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T97	2		T126	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T96	3		T97	3		T98	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T96	2		T97	1		T120	7
auto[TlIntgErrData]	full_word	auto[0]	4	1			T125	1		T129	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T120	1		T123	1		T131	2
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T96	2		T97	3		T120	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T97	5		T98	5		T120	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T125	1		T121	2		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T97	1		T132	1		T130	1