Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	676513	1			T3	8689		T5	15898		T15	4731
auto[1]	9617850	1			T3	9235		T4	2753		T6	1230
auto[2]	568899	1			T3	8740		T5	13767		T15	2992
auto[3]	9527370	1			T3	9402		T4	2837		T6	1244

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13250277	1			T3	681		T4	3921		T6	2028
auto[1]	1965651	1			T3	3941		T4	780		T6	225
auto[2]	1962212	1			T3	5183		T4	759		T6	205
auto[3]	3212492	1			T3	26261		T4	130		T6	16

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7959716

1

T4

5584

T6

2474

T11

4300

auto[1]

12430916

1

T3

36066

T4

6

T5

54766

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	362239	1			T15	3912		T34	5		T43	872
auto[0]	auto[0]	auto[1]	36529	1			T15	402		T43	75		T137	49
auto[0]	auto[0]	auto[2]	36645	1			T15	372		T43	75		T137	51
auto[0]	auto[0]	auto[3]	7905	1			T15	42		T43	7		T137	237
auto[0]	auto[1]	auto[0]	2919412	1			T4	1919		T6	1028		T11	1402
auto[0]	auto[1]	auto[1]	323157	1			T4	585		T6	108		T11	362
auto[0]	auto[1]	auto[2]	294530	1			T4	186		T6	89		T11	311
auto[0]	auto[1]	auto[3]	64326	1			T4	59		T6	5		T11	86
auto[0]	auto[2]	auto[0]	306807	1			T15	2277		T34	2		T8	1
auto[0]	auto[2]	auto[1]	31266	1			T15	270		T43	54		T137	41
auto[0]	auto[2]	auto[2]	30188	1			T15	396		T43	104		T137	33
auto[0]	auto[2]	auto[3]	6211	1			T15	47		T43	12		T137	148
auto[0]	auto[3]	auto[0]	2865386	1			T4	1998		T6	1000		T11	1400
auto[0]	auto[3]	auto[1]	289388	1			T4	194		T6	117		T11	331
auto[0]	auto[3]	auto[2]	318572	1			T4	572		T6	116		T11	331
auto[0]	auto[3]	auto[3]	67155	1			T4	71		T6	11		T11	77
auto[1]	auto[0]	auto[0]	7992	1			T3	287		T5	537		T15	3
auto[1]	auto[0]	auto[1]	34745	1			T3	1323		T5	2340		T135	1
auto[1]	auto[0]	auto[2]	34653	1			T3	1290		T5	2379		T135	2
auto[1]	auto[0]	auto[3]	155805	1			T3	5789		T5	10642		T136	12899
auto[1]	auto[1]	auto[0]	3388540	1			T3	174		T4	2		T5	71
auto[1]	auto[1]	auto[1]	622241	1			T3	1488		T4	1		T5	2440
auto[1]	auto[1]	auto[2]	602104	1			T3	873		T4	1		T5	375
auto[1]	auto[1]	auto[3]	1403540	1			T3	6700		T5	10684		T11	1
auto[1]	auto[2]	auto[0]	6963	1			T3	163		T5	483		T15	2
auto[1]	auto[2]	auto[1]	29808	1			T3	833		T5	2206		T135	1
auto[1]	auto[2]	auto[2]	28696	1			T3	1376		T5	1987		T43	1
auto[1]	auto[2]	auto[3]	128960	1			T3	6368		T5	9091		T136	10777
auto[1]	auto[3]	auto[0]	3392938	1			T3	57		T4	2		T5	47
auto[1]	auto[3]	auto[1]	598517	1			T3	297		T5	187		T14	1
auto[1]	auto[3]	auto[2]	616824	1			T3	1644		T5	2020		T52	4773
auto[1]	auto[3]	auto[3]	1378590	1			T3	7404		T5	9277		T52	470