Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	369735658	124960	0	0
ctrl_regwen_rd_A	369735658	5405	0	0
exec_rd_A	369735658	4437	0	0
exec_regwen_rd_A	369735658	4961	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735658	124960	0	0
T7	515457	0	0	0
T10	43695	0	0	0
T15	156013	0	0	0
T16	56086	2029	0	0
T18	24810	1302	0	0
T19	107234	0	0	0
T26	0	3894	0	0
T30	2481	0	0	0
T41	26298	0	0	0
T43	0	4763	0	0
T46	0	675	0	0
T47	0	8048	0	0
T48	0	1959	0	0
T49	0	2340	0	0
T50	0	2686	0	0
T51	0	1653	0	0
T52	167858	0	0	0
T53	222878	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735658	5405	0	0
T49	74116	495	0	0
T99	0	221	0	0
T100	0	137	0	0
T101	0	425	0	0
T102	0	299	0	0
T103	0	356	0	0
T104	0	309	0	0
T105	0	558	0	0
T106	0	169	0	0
T107	0	279	0	0
T108	12515	0	0	0
T109	66267	0	0	0
T110	7851	0	0	0
T111	60313	0	0	0
T112	169636	0	0	0
T113	4923	0	0	0
T114	84435	0	0	0
T115	14278	0	0	0
T116	927494	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735658	4437	0	0
T49	74116	306	0	0
T99	0	137	0	0
T100	0	126	0	0
T101	0	359	0	0
T102	0	281	0	0
T103	0	249	0	0
T104	0	278	0	0
T105	0	572	0	0
T106	0	142	0	0
T107	0	171	0	0
T108	12515	0	0	0
T109	66267	0	0	0
T110	7851	0	0	0
T111	60313	0	0	0
T112	169636	0	0	0
T113	4923	0	0	0
T114	84435	0	0	0
T115	14278	0	0	0
T116	927494	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735658	4961	0	0
T49	74116	347	0	0
T99	0	183	0	0
T100	0	146	0	0
T101	0	382	0	0
T102	0	306	0	0
T103	0	378	0	0
T104	0	230	0	0
T105	0	651	0	0
T106	0	172	0	0
T107	0	182	0	0
T108	12515	0	0	0
T109	66267	0	0	0
T110	7851	0	0	0
T111	60313	0	0	0
T112	169636	0	0	0
T113	4923	0	0	0
T114	84435	0	0	0
T115	14278	0	0	0
T116	927494	0	0	0