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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total test records in report: 1033
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T796 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1689560804 May 05 02:05:49 PM PDT 24 May 05 02:21:19 PM PDT 24 3068913735 ps
T797 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1275260548 May 05 02:00:20 PM PDT 24 May 05 02:01:45 PM PDT 24 1240567361 ps
T798 /workspace/coverage/default/0.sram_ctrl_alert_test.2328276091 May 05 01:58:25 PM PDT 24 May 05 01:58:26 PM PDT 24 55656944 ps
T799 /workspace/coverage/default/12.sram_ctrl_executable.3963781339 May 05 01:59:23 PM PDT 24 May 05 02:18:41 PM PDT 24 14883969245 ps
T800 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2402106731 May 05 01:58:49 PM PDT 24 May 05 02:04:10 PM PDT 24 13823980112 ps
T801 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.717040761 May 05 02:06:45 PM PDT 24 May 05 02:08:02 PM PDT 24 1767751165 ps
T802 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3722942996 May 05 01:58:39 PM PDT 24 May 05 02:04:47 PM PDT 24 33155942365 ps
T803 /workspace/coverage/default/39.sram_ctrl_mem_walk.16463238 May 05 02:04:38 PM PDT 24 May 05 02:04:43 PM PDT 24 1017917549 ps
T804 /workspace/coverage/default/31.sram_ctrl_lc_escalation.2147876252 May 05 02:02:44 PM PDT 24 May 05 02:02:54 PM PDT 24 3720311727 ps
T805 /workspace/coverage/default/36.sram_ctrl_ram_cfg.831777599 May 05 02:03:54 PM PDT 24 May 05 02:03:55 PM PDT 24 30305930 ps
T806 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.969919997 May 05 02:05:17 PM PDT 24 May 05 02:24:03 PM PDT 24 3533504229 ps
T807 /workspace/coverage/default/0.sram_ctrl_smoke.2666307437 May 05 01:58:19 PM PDT 24 May 05 01:58:29 PM PDT 24 450045596 ps
T808 /workspace/coverage/default/33.sram_ctrl_executable.3516440524 May 05 02:03:13 PM PDT 24 May 05 02:16:46 PM PDT 24 2801407730 ps
T809 /workspace/coverage/default/2.sram_ctrl_stress_all.1235771201 May 05 01:58:32 PM PDT 24 May 05 02:56:57 PM PDT 24 58589789743 ps
T810 /workspace/coverage/default/43.sram_ctrl_alert_test.2042586153 May 05 02:05:35 PM PDT 24 May 05 02:05:36 PM PDT 24 15673627 ps
T811 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2424120010 May 05 02:05:03 PM PDT 24 May 05 02:07:16 PM PDT 24 573196805 ps
T812 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.15052432 May 05 01:58:54 PM PDT 24 May 05 02:01:55 PM PDT 24 8330884225 ps
T813 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1900240231 May 05 02:02:29 PM PDT 24 May 05 02:03:07 PM PDT 24 106011097 ps
T814 /workspace/coverage/default/27.sram_ctrl_mem_walk.4210900082 May 05 02:01:52 PM PDT 24 May 05 02:02:02 PM PDT 24 664872540 ps
T815 /workspace/coverage/default/26.sram_ctrl_mem_walk.3932525463 May 05 02:01:40 PM PDT 24 May 05 02:01:48 PM PDT 24 180115131 ps
T816 /workspace/coverage/default/0.sram_ctrl_bijection.1548035524 May 05 01:58:27 PM PDT 24 May 05 01:58:44 PM PDT 24 1111152410 ps
T817 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.339372774 May 05 01:59:29 PM PDT 24 May 05 02:00:33 PM PDT 24 505646166 ps
T818 /workspace/coverage/default/45.sram_ctrl_regwen.4143771932 May 05 02:06:01 PM PDT 24 May 05 02:08:08 PM PDT 24 3782891847 ps
T819 /workspace/coverage/default/39.sram_ctrl_lc_escalation.1009873299 May 05 02:04:34 PM PDT 24 May 05 02:04:41 PM PDT 24 1674479041 ps
T820 /workspace/coverage/default/13.sram_ctrl_multiple_keys.1226030856 May 05 01:59:26 PM PDT 24 May 05 02:12:05 PM PDT 24 36527128104 ps
T821 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1180334677 May 05 01:59:51 PM PDT 24 May 05 02:09:45 PM PDT 24 8772089222 ps
T822 /workspace/coverage/default/46.sram_ctrl_ram_cfg.3107724603 May 05 02:06:11 PM PDT 24 May 05 02:06:13 PM PDT 24 340562240 ps
T823 /workspace/coverage/default/1.sram_ctrl_alert_test.3862578485 May 05 01:58:28 PM PDT 24 May 05 01:58:30 PM PDT 24 27775980 ps
T824 /workspace/coverage/default/45.sram_ctrl_partial_access.1232374320 May 05 02:05:57 PM PDT 24 May 05 02:06:12 PM PDT 24 751804824 ps
T825 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4288456416 May 05 02:04:19 PM PDT 24 May 05 02:11:32 PM PDT 24 103909168025 ps
T826 /workspace/coverage/default/10.sram_ctrl_alert_test.3643771212 May 05 01:59:18 PM PDT 24 May 05 01:59:19 PM PDT 24 25796114 ps
T827 /workspace/coverage/default/29.sram_ctrl_multiple_keys.1493488714 May 05 02:02:11 PM PDT 24 May 05 02:15:12 PM PDT 24 13220129346 ps
T828 /workspace/coverage/default/10.sram_ctrl_lc_escalation.4118478606 May 05 01:59:13 PM PDT 24 May 05 01:59:19 PM PDT 24 1416912211 ps
T829 /workspace/coverage/default/23.sram_ctrl_executable.1597655995 May 05 02:01:01 PM PDT 24 May 05 02:02:25 PM PDT 24 4882374877 ps
T830 /workspace/coverage/default/15.sram_ctrl_bijection.1860544366 May 05 01:59:42 PM PDT 24 May 05 02:00:19 PM PDT 24 2365696255 ps
T831 /workspace/coverage/default/47.sram_ctrl_regwen.2183170361 May 05 02:06:29 PM PDT 24 May 05 02:12:32 PM PDT 24 1829220970 ps
T832 /workspace/coverage/default/37.sram_ctrl_max_throughput.3376187209 May 05 02:04:05 PM PDT 24 May 05 02:05:27 PM PDT 24 127785126 ps
T833 /workspace/coverage/default/4.sram_ctrl_mem_walk.1403691506 May 05 01:58:44 PM PDT 24 May 05 01:58:50 PM PDT 24 240534641 ps
T834 /workspace/coverage/default/44.sram_ctrl_partial_access.1465029275 May 05 02:05:43 PM PDT 24 May 05 02:05:50 PM PDT 24 1626683253 ps
T835 /workspace/coverage/default/38.sram_ctrl_lc_escalation.2544999825 May 05 02:04:19 PM PDT 24 May 05 02:04:24 PM PDT 24 721563064 ps
T836 /workspace/coverage/default/15.sram_ctrl_lc_escalation.3207620668 May 05 01:59:45 PM PDT 24 May 05 01:59:53 PM PDT 24 2279300672 ps
T837 /workspace/coverage/default/48.sram_ctrl_mem_walk.3104855873 May 05 02:06:46 PM PDT 24 May 05 02:06:56 PM PDT 24 1334200056 ps
T838 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3900361050 May 05 02:02:00 PM PDT 24 May 05 02:08:31 PM PDT 24 19261259204 ps
T839 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.171642902 May 05 01:59:44 PM PDT 24 May 05 02:05:18 PM PDT 24 27078394318 ps
T840 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2423398752 May 05 02:01:17 PM PDT 24 May 05 02:01:22 PM PDT 24 288898757 ps
T841 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.331349924 May 05 02:01:01 PM PDT 24 May 05 02:03:14 PM PDT 24 1336687612 ps
T842 /workspace/coverage/default/25.sram_ctrl_ram_cfg.650094002 May 05 02:01:28 PM PDT 24 May 05 02:01:29 PM PDT 24 29889477 ps
T843 /workspace/coverage/default/16.sram_ctrl_smoke.3864708044 May 05 01:59:48 PM PDT 24 May 05 02:00:05 PM PDT 24 795536674 ps
T844 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3601258823 May 05 02:00:23 PM PDT 24 May 05 02:02:21 PM PDT 24 3946525251 ps
T845 /workspace/coverage/default/17.sram_ctrl_regwen.3751386509 May 05 02:00:01 PM PDT 24 May 05 02:26:30 PM PDT 24 22675038489 ps
T846 /workspace/coverage/default/45.sram_ctrl_ram_cfg.3034583894 May 05 02:06:02 PM PDT 24 May 05 02:06:04 PM PDT 24 51201242 ps
T847 /workspace/coverage/default/13.sram_ctrl_ram_cfg.3032784318 May 05 01:59:35 PM PDT 24 May 05 01:59:36 PM PDT 24 50636033 ps
T848 /workspace/coverage/default/2.sram_ctrl_regwen.4015979678 May 05 01:58:34 PM PDT 24 May 05 02:06:06 PM PDT 24 6831352897 ps
T849 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2343253349 May 05 01:58:19 PM PDT 24 May 05 01:58:46 PM PDT 24 137438744 ps
T850 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1596968639 May 05 01:58:41 PM PDT 24 May 05 01:58:46 PM PDT 24 845900302 ps
T851 /workspace/coverage/default/4.sram_ctrl_executable.3648203808 May 05 01:58:43 PM PDT 24 May 05 02:09:10 PM PDT 24 53945583252 ps
T852 /workspace/coverage/default/3.sram_ctrl_partial_access.3607094959 May 05 01:58:40 PM PDT 24 May 05 01:58:57 PM PDT 24 3528244963 ps
T853 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.894989332 May 05 01:59:17 PM PDT 24 May 05 02:03:34 PM PDT 24 1256770408 ps
T854 /workspace/coverage/default/46.sram_ctrl_bijection.1514370044 May 05 02:06:07 PM PDT 24 May 05 02:06:57 PM PDT 24 1504298970 ps
T855 /workspace/coverage/default/34.sram_ctrl_multiple_keys.1376573841 May 05 02:03:19 PM PDT 24 May 05 02:05:27 PM PDT 24 2318420270 ps
T856 /workspace/coverage/default/18.sram_ctrl_alert_test.2228993828 May 05 02:00:17 PM PDT 24 May 05 02:00:18 PM PDT 24 11208643 ps
T857 /workspace/coverage/default/5.sram_ctrl_max_throughput.1853955723 May 05 01:58:51 PM PDT 24 May 05 01:58:53 PM PDT 24 58902559 ps
T858 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2146406892 May 05 02:03:34 PM PDT 24 May 05 02:24:15 PM PDT 24 4423802739 ps
T859 /workspace/coverage/default/44.sram_ctrl_multiple_keys.44606664 May 05 02:05:39 PM PDT 24 May 05 02:21:11 PM PDT 24 33008598446 ps
T860 /workspace/coverage/default/28.sram_ctrl_lc_escalation.2115343878 May 05 02:02:00 PM PDT 24 May 05 02:02:08 PM PDT 24 1203184182 ps
T861 /workspace/coverage/default/46.sram_ctrl_regwen.860394696 May 05 02:06:14 PM PDT 24 May 05 02:37:23 PM PDT 24 104259645741 ps
T862 /workspace/coverage/default/13.sram_ctrl_smoke.709409601 May 05 01:59:26 PM PDT 24 May 05 01:59:43 PM PDT 24 3125646035 ps
T863 /workspace/coverage/default/14.sram_ctrl_executable.428259487 May 05 01:59:38 PM PDT 24 May 05 02:09:27 PM PDT 24 12159711121 ps
T864 /workspace/coverage/default/0.sram_ctrl_mem_walk.2601064769 May 05 01:58:26 PM PDT 24 May 05 01:58:37 PM PDT 24 1327386938 ps
T865 /workspace/coverage/default/36.sram_ctrl_max_throughput.53628089 May 05 02:03:50 PM PDT 24 May 05 02:03:52 PM PDT 24 38003871 ps
T866 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1983790313 May 05 02:05:06 PM PDT 24 May 05 02:05:12 PM PDT 24 219529425 ps
T867 /workspace/coverage/default/42.sram_ctrl_alert_test.3982424196 May 05 02:05:22 PM PDT 24 May 05 02:05:22 PM PDT 24 19756504 ps
T868 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.100422643 May 05 02:02:21 PM PDT 24 May 05 02:02:24 PM PDT 24 88316433 ps
T869 /workspace/coverage/default/28.sram_ctrl_max_throughput.3852987327 May 05 02:02:00 PM PDT 24 May 05 02:04:01 PM PDT 24 286350541 ps
T870 /workspace/coverage/default/12.sram_ctrl_bijection.415090062 May 05 01:59:22 PM PDT 24 May 05 02:00:05 PM PDT 24 772667928 ps
T871 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2935032464 May 05 02:04:45 PM PDT 24 May 05 02:09:12 PM PDT 24 11702653450 ps
T872 /workspace/coverage/default/43.sram_ctrl_bijection.1294415405 May 05 02:05:23 PM PDT 24 May 05 02:06:13 PM PDT 24 2637745137 ps
T873 /workspace/coverage/default/2.sram_ctrl_max_throughput.910849275 May 05 01:58:31 PM PDT 24 May 05 01:58:46 PM PDT 24 291881650 ps
T874 /workspace/coverage/default/37.sram_ctrl_lc_escalation.891568303 May 05 02:04:05 PM PDT 24 May 05 02:04:10 PM PDT 24 466555734 ps
T875 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2909067366 May 05 01:59:42 PM PDT 24 May 05 01:59:48 PM PDT 24 558979156 ps
T876 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2035936485 May 05 02:02:15 PM PDT 24 May 05 02:16:03 PM PDT 24 2993257304 ps
T877 /workspace/coverage/default/18.sram_ctrl_multiple_keys.3058382342 May 05 02:00:04 PM PDT 24 May 05 02:24:10 PM PDT 24 19375507530 ps
T878 /workspace/coverage/default/49.sram_ctrl_stress_all.1931117869 May 05 02:07:03 PM PDT 24 May 05 03:41:22 PM PDT 24 128676188636 ps
T879 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2395702076 May 05 02:03:13 PM PDT 24 May 05 02:04:45 PM PDT 24 10760094293 ps
T880 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2433644401 May 05 01:58:25 PM PDT 24 May 05 02:03:41 PM PDT 24 70898794312 ps
T881 /workspace/coverage/default/3.sram_ctrl_smoke.1342753833 May 05 01:58:38 PM PDT 24 May 05 02:00:21 PM PDT 24 1336080606 ps
T882 /workspace/coverage/default/40.sram_ctrl_bijection.3848638079 May 05 02:04:42 PM PDT 24 May 05 02:05:22 PM PDT 24 1966044504 ps
T883 /workspace/coverage/default/48.sram_ctrl_max_throughput.2514567619 May 05 02:06:40 PM PDT 24 May 05 02:06:51 PM PDT 24 254034865 ps
T884 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1561861967 May 05 02:00:09 PM PDT 24 May 05 02:01:41 PM PDT 24 171512760 ps
T885 /workspace/coverage/default/34.sram_ctrl_alert_test.270127751 May 05 02:03:44 PM PDT 24 May 05 02:03:45 PM PDT 24 13362337 ps
T886 /workspace/coverage/default/13.sram_ctrl_alert_test.1609719317 May 05 01:59:32 PM PDT 24 May 05 01:59:33 PM PDT 24 27013254 ps
T887 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1794584885 May 05 02:01:34 PM PDT 24 May 05 02:01:53 PM PDT 24 2637055632 ps
T888 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2217590830 May 05 01:59:48 PM PDT 24 May 05 02:06:06 PM PDT 24 3356605971 ps
T889 /workspace/coverage/default/8.sram_ctrl_ram_cfg.2992556426 May 05 01:59:03 PM PDT 24 May 05 01:59:04 PM PDT 24 27971516 ps
T890 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.729656260 May 05 02:06:11 PM PDT 24 May 05 02:21:35 PM PDT 24 22275174091 ps
T891 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1668434880 May 05 02:05:58 PM PDT 24 May 05 02:06:01 PM PDT 24 47712010 ps
T892 /workspace/coverage/default/12.sram_ctrl_regwen.2416330933 May 05 01:59:24 PM PDT 24 May 05 02:11:11 PM PDT 24 2013564923 ps
T893 /workspace/coverage/default/10.sram_ctrl_stress_all.1935406150 May 05 01:59:18 PM PDT 24 May 05 02:53:42 PM PDT 24 262223740650 ps
T894 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2811249165 May 05 02:06:18 PM PDT 24 May 05 02:06:21 PM PDT 24 101961920 ps
T895 /workspace/coverage/default/22.sram_ctrl_alert_test.3659772989 May 05 02:00:56 PM PDT 24 May 05 02:00:57 PM PDT 24 51703479 ps
T896 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1005579924 May 05 02:00:33 PM PDT 24 May 05 02:04:15 PM PDT 24 9991746961 ps
T897 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1471992472 May 05 01:59:46 PM PDT 24 May 05 02:01:13 PM PDT 24 544463815 ps
T898 /workspace/coverage/default/24.sram_ctrl_regwen.520630981 May 05 02:01:17 PM PDT 24 May 05 02:03:41 PM PDT 24 1791675939 ps
T899 /workspace/coverage/default/27.sram_ctrl_partial_access.2941063044 May 05 02:01:47 PM PDT 24 May 05 02:02:03 PM PDT 24 1045647193 ps
T900 /workspace/coverage/default/43.sram_ctrl_max_throughput.392858065 May 05 02:05:29 PM PDT 24 May 05 02:06:11 PM PDT 24 114478860 ps
T901 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1755912641 May 05 02:00:53 PM PDT 24 May 05 02:00:59 PM PDT 24 2263816461 ps
T902 /workspace/coverage/default/1.sram_ctrl_stress_all.2885731950 May 05 01:58:29 PM PDT 24 May 05 02:11:48 PM PDT 24 16135389332 ps
T903 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1316806262 May 05 02:03:49 PM PDT 24 May 05 02:09:53 PM PDT 24 2849397345 ps
T904 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2708363743 May 05 01:58:33 PM PDT 24 May 05 01:59:15 PM PDT 24 528099345 ps
T905 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2996144110 May 05 02:05:21 PM PDT 24 May 05 02:05:23 PM PDT 24 79034062 ps
T906 /workspace/coverage/default/15.sram_ctrl_stress_all.68927769 May 05 01:59:47 PM PDT 24 May 05 02:16:42 PM PDT 24 56157876348 ps
T907 /workspace/coverage/default/7.sram_ctrl_mem_walk.2977067469 May 05 01:58:59 PM PDT 24 May 05 01:59:04 PM PDT 24 148348666 ps
T908 /workspace/coverage/default/33.sram_ctrl_stress_all.197401764 May 05 02:03:13 PM PDT 24 May 05 02:51:34 PM PDT 24 43029629602 ps
T909 /workspace/coverage/default/33.sram_ctrl_ram_cfg.1990969429 May 05 02:03:13 PM PDT 24 May 05 02:03:15 PM PDT 24 34394008 ps
T910 /workspace/coverage/default/38.sram_ctrl_partial_access.3440872586 May 05 02:04:14 PM PDT 24 May 05 02:04:44 PM PDT 24 3143783713 ps
T911 /workspace/coverage/default/35.sram_ctrl_mem_walk.407532651 May 05 02:03:43 PM PDT 24 May 05 02:03:52 PM PDT 24 470179964 ps
T912 /workspace/coverage/default/14.sram_ctrl_multiple_keys.3229192768 May 05 01:59:34 PM PDT 24 May 05 02:13:54 PM PDT 24 34817088439 ps
T913 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2591962235 May 05 02:01:51 PM PDT 24 May 05 02:02:43 PM PDT 24 520608643 ps
T914 /workspace/coverage/default/27.sram_ctrl_bijection.3407367900 May 05 02:01:45 PM PDT 24 May 05 02:02:14 PM PDT 24 5245331768 ps
T915 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.853748268 May 05 01:59:45 PM PDT 24 May 05 02:00:29 PM PDT 24 4125202721 ps
T916 /workspace/coverage/default/5.sram_ctrl_partial_access.3797980836 May 05 01:58:48 PM PDT 24 May 05 01:58:56 PM PDT 24 76175495 ps
T917 /workspace/coverage/default/45.sram_ctrl_bijection.70670405 May 05 02:06:00 PM PDT 24 May 05 02:06:36 PM PDT 24 6641068589 ps
T918 /workspace/coverage/default/7.sram_ctrl_bijection.618342769 May 05 01:58:52 PM PDT 24 May 05 02:00:13 PM PDT 24 10876539743 ps
T919 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.962142725 May 05 02:06:53 PM PDT 24 May 05 02:08:06 PM PDT 24 812750519 ps
T920 /workspace/coverage/default/32.sram_ctrl_ram_cfg.377038530 May 05 02:03:00 PM PDT 24 May 05 02:03:01 PM PDT 24 86514096 ps
T921 /workspace/coverage/default/13.sram_ctrl_executable.271956588 May 05 01:59:33 PM PDT 24 May 05 02:24:44 PM PDT 24 13430661814 ps
T922 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1737761486 May 05 02:03:02 PM PDT 24 May 05 02:20:47 PM PDT 24 30991200857 ps
T923 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.503897569 May 05 01:59:50 PM PDT 24 May 05 02:04:57 PM PDT 24 16906709431 ps
T924 /workspace/coverage/default/48.sram_ctrl_bijection.1848671329 May 05 02:06:41 PM PDT 24 May 05 02:07:11 PM PDT 24 7810250768 ps
T925 /workspace/coverage/default/9.sram_ctrl_partial_access.425247032 May 05 01:59:02 PM PDT 24 May 05 01:59:16 PM PDT 24 555063914 ps
T926 /workspace/coverage/default/19.sram_ctrl_stress_all.2891061993 May 05 02:00:24 PM PDT 24 May 05 03:32:02 PM PDT 24 372986368555 ps
T927 /workspace/coverage/default/31.sram_ctrl_stress_all.1875593792 May 05 02:02:50 PM PDT 24 May 05 02:53:51 PM PDT 24 103010923426 ps
T928 /workspace/coverage/default/28.sram_ctrl_multiple_keys.509152620 May 05 02:01:56 PM PDT 24 May 05 02:07:06 PM PDT 24 3572492809 ps
T929 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1132135753 May 05 02:06:39 PM PDT 24 May 05 02:06:44 PM PDT 24 168499506 ps
T930 /workspace/coverage/default/6.sram_ctrl_multiple_keys.1398984238 May 05 01:58:53 PM PDT 24 May 05 02:18:45 PM PDT 24 44827264523 ps
T931 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1167911061 May 05 01:59:14 PM PDT 24 May 05 01:59:42 PM PDT 24 576619390 ps
T932 /workspace/coverage/default/18.sram_ctrl_bijection.4252478008 May 05 02:00:04 PM PDT 24 May 05 02:01:07 PM PDT 24 1075727692 ps
T933 /workspace/coverage/default/35.sram_ctrl_lc_escalation.1495626084 May 05 02:03:44 PM PDT 24 May 05 02:03:46 PM PDT 24 171084388 ps
T934 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.819320076 May 05 02:04:48 PM PDT 24 May 05 02:25:58 PM PDT 24 20900566374 ps
T935 /workspace/coverage/default/39.sram_ctrl_multiple_keys.600532928 May 05 02:04:25 PM PDT 24 May 05 02:08:41 PM PDT 24 6430672250 ps
T936 /workspace/coverage/default/22.sram_ctrl_regwen.3582521915 May 05 02:00:52 PM PDT 24 May 05 02:22:04 PM PDT 24 11892919230 ps
T937 /workspace/coverage/default/14.sram_ctrl_regwen.3329758499 May 05 01:59:37 PM PDT 24 May 05 02:09:20 PM PDT 24 7523907614 ps
T938 /workspace/coverage/default/16.sram_ctrl_partial_access.4003520514 May 05 01:59:51 PM PDT 24 May 05 01:59:54 PM PDT 24 37098474 ps
T939 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2286997432 May 05 02:03:24 PM PDT 24 May 05 02:05:42 PM PDT 24 602811489 ps
T940 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1574232105 May 05 02:02:27 PM PDT 24 May 05 02:06:51 PM PDT 24 3405919174 ps
T941 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3620866178 May 05 02:03:28 PM PDT 24 May 05 02:09:05 PM PDT 24 960788295 ps
T942 /workspace/coverage/default/6.sram_ctrl_regwen.1810407196 May 05 01:58:54 PM PDT 24 May 05 01:59:15 PM PDT 24 383180049 ps
T943 /workspace/coverage/default/34.sram_ctrl_stress_all.2514898763 May 05 02:03:43 PM PDT 24 May 05 02:34:31 PM PDT 24 9431891784 ps
T944 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3172774743 May 05 01:55:05 PM PDT 24 May 05 01:55:07 PM PDT 24 313343589 ps
T84 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.83654057 May 05 01:55:09 PM PDT 24 May 05 01:55:11 PM PDT 24 13770125 ps
T56 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1454480052 May 05 01:55:14 PM PDT 24 May 05 01:55:16 PM PDT 24 26374351 ps
T85 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.541547803 May 05 01:55:12 PM PDT 24 May 05 01:55:14 PM PDT 24 228001657 ps
T945 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4215930642 May 05 01:55:05 PM PDT 24 May 05 01:55:07 PM PDT 24 117020631 ps
T946 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2222197653 May 05 01:55:13 PM PDT 24 May 05 01:55:14 PM PDT 24 29061710 ps
T57 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2973808513 May 05 01:55:07 PM PDT 24 May 05 01:55:10 PM PDT 24 831322076 ps
T947 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.646063079 May 05 01:55:18 PM PDT 24 May 05 01:55:22 PM PDT 24 39941839 ps
T93 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.609099732 May 05 01:54:56 PM PDT 24 May 05 01:54:57 PM PDT 24 16380333 ps
T96 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1877337625 May 05 01:55:17 PM PDT 24 May 05 01:55:20 PM PDT 24 258141482 ps
T58 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3479355134 May 05 01:55:07 PM PDT 24 May 05 01:55:09 PM PDT 24 21036411 ps
T94 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3413526885 May 05 01:55:13 PM PDT 24 May 05 01:55:14 PM PDT 24 17961745 ps
T95 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3744974006 May 05 01:55:01 PM PDT 24 May 05 01:55:02 PM PDT 24 19567457 ps
T59 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.181332457 May 05 01:54:55 PM PDT 24 May 05 01:54:58 PM PDT 24 2021994080 ps
T86 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3854390227 May 05 01:55:07 PM PDT 24 May 05 01:55:08 PM PDT 24 38711808 ps
T87 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.822376997 May 05 01:55:14 PM PDT 24 May 05 01:55:15 PM PDT 24 16587757 ps
T948 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.707562576 May 05 01:55:04 PM PDT 24 May 05 01:55:07 PM PDT 24 82820753 ps
T949 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4280572264 May 05 01:54:59 PM PDT 24 May 05 01:55:00 PM PDT 24 334806460 ps
T60 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3859142154 May 05 01:55:12 PM PDT 24 May 05 01:55:17 PM PDT 24 4500133543 ps
T97 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3959503030 May 05 01:55:02 PM PDT 24 May 05 01:55:05 PM PDT 24 1908240731 ps
T88 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3162497978 May 05 01:55:12 PM PDT 24 May 05 01:55:13 PM PDT 24 34556925 ps
T950 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.630982924 May 05 01:55:17 PM PDT 24 May 05 01:55:19 PM PDT 24 106204162 ps
T61 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3111362692 May 05 01:55:22 PM PDT 24 May 05 01:55:26 PM PDT 24 427655623 ps
T951 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2951632253 May 05 01:55:12 PM PDT 24 May 05 01:55:15 PM PDT 24 130694725 ps
T952 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3366505044 May 05 01:55:09 PM PDT 24 May 05 01:55:12 PM PDT 24 286347260 ps
T62 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1244110925 May 05 01:55:05 PM PDT 24 May 05 01:55:07 PM PDT 24 309195773 ps
T953 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3424514540 May 05 01:55:04 PM PDT 24 May 05 01:55:07 PM PDT 24 100874037 ps
T63 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.40462132 May 05 01:55:10 PM PDT 24 May 05 01:55:12 PM PDT 24 13118420 ps
T954 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.775577305 May 05 01:55:23 PM PDT 24 May 05 01:55:25 PM PDT 24 17116415 ps
T955 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3545872148 May 05 01:55:04 PM PDT 24 May 05 01:55:06 PM PDT 24 119553643 ps
T956 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.441925030 May 05 01:55:05 PM PDT 24 May 05 01:55:07 PM PDT 24 33108074 ps
T957 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.164815696 May 05 01:55:10 PM PDT 24 May 05 01:55:14 PM PDT 24 687710602 ps
T958 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1441292943 May 05 01:55:04 PM PDT 24 May 05 01:55:06 PM PDT 24 21436824 ps
T98 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1174858572 May 05 01:55:04 PM PDT 24 May 05 01:55:05 PM PDT 24 307863967 ps
T959 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.29718682 May 05 01:55:21 PM PDT 24 May 05 01:55:23 PM PDT 24 21102625 ps
T960 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3579063120 May 05 01:55:04 PM PDT 24 May 05 01:55:05 PM PDT 24 37496749 ps
T961 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1670470706 May 05 01:55:20 PM PDT 24 May 05 01:55:23 PM PDT 24 53043427 ps
T120 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.419255689 May 05 01:55:07 PM PDT 24 May 05 01:55:10 PM PDT 24 171077097 ps
T64 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2164858723 May 05 01:55:01 PM PDT 24 May 05 01:55:02 PM PDT 24 33877259 ps
T125 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1234921505 May 05 01:55:08 PM PDT 24 May 05 01:55:10 PM PDT 24 630426566 ps
T65 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1019473018 May 05 01:55:16 PM PDT 24 May 05 01:55:17 PM PDT 24 15786212 ps
T962 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.688577029 May 05 01:55:08 PM PDT 24 May 05 01:55:10 PM PDT 24 92644560 ps
T963 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.17791912 May 05 01:55:09 PM PDT 24 May 05 01:55:10 PM PDT 24 24416461 ps
T964 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4284839727 May 05 01:55:19 PM PDT 24 May 05 01:55:20 PM PDT 24 35115070 ps
T66 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3786590688 May 05 01:55:22 PM PDT 24 May 05 01:55:27 PM PDT 24 406084631 ps
T126 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3948416401 May 05 01:55:20 PM PDT 24 May 05 01:55:23 PM PDT 24 393598346 ps
T965 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.398420032 May 05 01:55:05 PM PDT 24 May 05 01:55:07 PM PDT 24 348970939 ps
T67 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2727359660 May 05 01:55:06 PM PDT 24 May 05 01:55:08 PM PDT 24 610339742 ps
T966 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3398442374 May 05 01:55:03 PM PDT 24 May 05 01:55:04 PM PDT 24 18718952 ps
T121 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1816328284 May 05 01:55:11 PM PDT 24 May 05 01:55:14 PM PDT 24 327843664 ps
T76 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.88222372 May 05 01:55:06 PM PDT 24 May 05 01:55:10 PM PDT 24 565283439 ps
T967 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2694662336 May 05 01:55:18 PM PDT 24 May 05 01:55:20 PM PDT 24 104941832 ps
T128 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1006801809 May 05 01:55:12 PM PDT 24 May 05 01:55:14 PM PDT 24 327974879 ps
T968 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2034061443 May 05 01:55:11 PM PDT 24 May 05 01:55:12 PM PDT 24 59654721 ps
T969 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2535388971 May 05 01:55:05 PM PDT 24 May 05 01:55:06 PM PDT 24 34713900 ps
T970 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3761360994 May 05 01:55:18 PM PDT 24 May 05 01:55:19 PM PDT 24 99696074 ps
T82 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1523220125 May 05 01:55:03 PM PDT 24 May 05 01:55:04 PM PDT 24 15008000 ps
T971 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2400927476 May 05 01:55:02 PM PDT 24 May 05 01:55:03 PM PDT 24 26196752 ps
T972 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1241886491 May 05 01:55:10 PM PDT 24 May 05 01:55:12 PM PDT 24 14779818 ps
T973 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.815546574 May 05 01:55:13 PM PDT 24 May 05 01:55:16 PM PDT 24 111672527 ps
T974 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1530016083 May 05 01:55:03 PM PDT 24 May 05 01:55:04 PM PDT 24 13292952 ps
T122 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1939272340 May 05 01:55:06 PM PDT 24 May 05 01:55:09 PM PDT 24 490719759 ps
T123 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2511701667 May 05 01:55:15 PM PDT 24 May 05 01:55:18 PM PDT 24 176472598 ps
T975 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4290786607 May 05 01:54:55 PM PDT 24 May 05 01:54:56 PM PDT 24 15772928 ps
T77 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1314839446 May 05 01:55:23 PM PDT 24 May 05 01:55:27 PM PDT 24 434698151 ps
T129 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1557136434 May 05 01:55:19 PM PDT 24 May 05 01:55:22 PM PDT 24 726360171 ps
T124 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3192959433 May 05 01:55:19 PM PDT 24 May 05 01:55:21 PM PDT 24 129534378 ps
T976 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2931775531 May 05 01:54:56 PM PDT 24 May 05 01:54:58 PM PDT 24 70078386 ps
T83 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.674162811 May 05 01:55:18 PM PDT 24 May 05 01:55:19 PM PDT 24 32687927 ps
T977 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1932786324 May 05 01:54:56 PM PDT 24 May 05 01:54:59 PM PDT 24 30276564 ps
T78 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2686539616 May 05 01:55:21 PM PDT 24 May 05 01:55:26 PM PDT 24 3116731638 ps
T978 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.489134818 May 05 01:55:24 PM PDT 24 May 05 01:55:26 PM PDT 24 112750750 ps
T979 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2010162310 May 05 01:55:19 PM PDT 24 May 05 01:55:20 PM PDT 24 68634938 ps
T980 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2805433322 May 05 01:55:16 PM PDT 24 May 05 01:55:18 PM PDT 24 956625708 ps
T132 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3315628863 May 05 01:55:05 PM PDT 24 May 05 01:55:06 PM PDT 24 371612008 ps
T981 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2367004390 May 05 01:55:04 PM PDT 24 May 05 01:55:06 PM PDT 24 54959290 ps
T982 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1761813838 May 05 01:55:00 PM PDT 24 May 05 01:55:02 PM PDT 24 850543819 ps
T983 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.122192064 May 05 01:55:03 PM PDT 24 May 05 01:55:04 PM PDT 24 28599368 ps
T984 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1326143276 May 05 01:55:12 PM PDT 24 May 05 01:55:13 PM PDT 24 17919536 ps
T985 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2558404031 May 05 01:55:08 PM PDT 24 May 05 01:55:09 PM PDT 24 78236998 ps
T75 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.811555909 May 05 01:55:02 PM PDT 24 May 05 01:55:03 PM PDT 24 26652933 ps
T79 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1009974831 May 05 01:55:01 PM PDT 24 May 05 01:55:02 PM PDT 24 22079705 ps
T986 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.308264654 May 05 01:55:08 PM PDT 24 May 05 01:55:09 PM PDT 24 34572682 ps
T987 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4269872834 May 05 01:55:03 PM PDT 24 May 05 01:55:04 PM PDT 24 18532468 ps
T988 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1100606977 May 05 01:55:09 PM PDT 24 May 05 01:55:11 PM PDT 24 57036124 ps
T989 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.31549695 May 05 01:55:12 PM PDT 24 May 05 01:55:15 PM PDT 24 42887723 ps
T990 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.997118454 May 05 01:55:19 PM PDT 24 May 05 01:55:24 PM PDT 24 376912683 ps
T991 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3196335232 May 05 01:55:15 PM PDT 24 May 05 01:55:18 PM PDT 24 58413996 ps
T80 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3183934912 May 05 01:55:15 PM PDT 24 May 05 01:55:17 PM PDT 24 836523068 ps
T992 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.36141379 May 05 01:55:06 PM PDT 24 May 05 01:55:08 PM PDT 24 39058927 ps
T993 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4240360614 May 05 01:55:08 PM PDT 24 May 05 01:55:09 PM PDT 24 32880689 ps
T131 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1863655415 May 05 01:55:04 PM PDT 24 May 05 01:55:06 PM PDT 24 137501019 ps
T81 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2931720771 May 05 01:55:11 PM PDT 24 May 05 01:55:13 PM PDT 24 766390865 ps
T994 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2519053164 May 05 01:55:09 PM PDT 24 May 05 01:55:10 PM PDT 24 10800867 ps
T127 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2190261901 May 05 01:55:05 PM PDT 24 May 05 01:55:06 PM PDT 24 274998526 ps
T995 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1511924397 May 05 01:55:17 PM PDT 24 May 05 01:55:19 PM PDT 24 135157109 ps
T996 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2657782128 May 05 01:55:06 PM PDT 24 May 05 01:55:10 PM PDT 24 341972587 ps
T997 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.393436983 May 05 01:55:13 PM PDT 24 May 05 01:55:14 PM PDT 24 12095526 ps
T998 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2219474254 May 05 01:54:58 PM PDT 24 May 05 01:55:00 PM PDT 24 76664602 ps
T999 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1458428822 May 05 01:55:17 PM PDT 24 May 05 01:55:20 PM PDT 24 2802090201 ps
T1000 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1174219789 May 05 01:55:14 PM PDT 24 May 05 01:55:18 PM PDT 24 1771578922 ps
T1001 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.267821850 May 05 01:54:54 PM PDT 24 May 05 01:54:55 PM PDT 24 30473359 ps
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