Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13925679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

56829281

1

T1

6142

T2

161534

T3

171015

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35274602	1			T1	2048		T2	89031		T3	94073
values[0x0]	16347849	1			T1	1967		T2	42451		T3	45164
values[0x1]	19132509	1			T1	2127		T2	46224		T3	48808

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6936901	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63818059

1

T1

6142

T2

169635

T3

179606

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	308731	1			T1	5		T2	715		T3	675
valid_sources[0x01]	242331	1			T1	27		T2	716		T3	758
valid_sources[0x02]	267930	1			T1	3		T2	697		T3	752
valid_sources[0x03]	249307	1			T1	27		T2	711		T3	748
valid_sources[0x04]	271045	1			T1	26		T2	684		T3	708
valid_sources[0x05]	238657	1			T1	2		T2	716		T3	731
valid_sources[0x06]	253902	1			T1	43		T2	707		T3	762
valid_sources[0x07]	261868	1			T1	60		T2	683		T3	677
valid_sources[0x08]	295730	1			T1	6		T2	697		T3	748
valid_sources[0x09]	291415	1			T1	32		T2	670		T3	723
valid_sources[0x0a]	297289	1			T1	30		T2	735		T3	730
valid_sources[0x0b]	383274	1			T1	32		T2	684		T3	770
valid_sources[0x0c]	258283	1			T1	20		T2	674		T3	774
valid_sources[0x0d]	239428	1			T1	4		T2	692		T3	676
valid_sources[0x0e]	253445	1			T1	25		T2	676		T3	767
valid_sources[0x0f]	315175	1			T1	27		T2	708		T3	756
valid_sources[0x10]	244489	1			T1	34		T2	711		T3	685
valid_sources[0x11]	255602	1			T1	41		T2	628		T3	699
valid_sources[0x12]	317341	1			T1	18		T2	715		T3	788
valid_sources[0x13]	272616	1			T1	22		T2	671		T3	741
valid_sources[0x14]	275923	1			T1	23		T2	682		T3	750
valid_sources[0x15]	254326	1			T1	41		T2	707		T3	729
valid_sources[0x16]	299876	1			T1	19		T2	682		T3	670
valid_sources[0x17]	302758	1			T1	39		T2	726		T3	727
valid_sources[0x18]	302664	1			T1	20		T2	711		T3	713
valid_sources[0x19]	298839	1			T1	26		T2	687		T3	784
valid_sources[0x1a]	254126	1			T1	41		T2	672		T3	719
valid_sources[0x1b]	239994	1			T1	10		T2	708		T3	721
valid_sources[0x1c]	271408	1			T1	21		T2	714		T3	748
valid_sources[0x1d]	346141	1			T1	8		T2	677		T3	725
valid_sources[0x1e]	261776	1			T1	16		T2	687		T3	700
valid_sources[0x1f]	306112	1			T1	8		T2	743		T3	780
valid_sources[0x20]	241346	1			T1	16		T2	640		T3	821
valid_sources[0x21]	296101	1			T1	10		T2	702		T3	823
valid_sources[0x22]	255854	1			T1	23		T2	693		T3	733
valid_sources[0x23]	235906	1			T1	22		T2	717		T3	665
valid_sources[0x24]	274799	1			T1	29		T2	691		T3	731
valid_sources[0x25]	286917	1			T1	37		T2	645		T3	704
valid_sources[0x26]	300170	1			T1	20		T2	704		T3	732
valid_sources[0x27]	309222	1			T1	39		T2	686		T3	788
valid_sources[0x28]	274632	1			T1	9		T2	671		T3	754
valid_sources[0x29]	333037	1			T1	11		T2	690		T3	699
valid_sources[0x2a]	325885	1			T1	21		T2	673		T3	642
valid_sources[0x2b]	255813	1			T1	29		T2	722		T3	762
valid_sources[0x2c]	253921	1			T1	10		T2	672		T3	686
valid_sources[0x2d]	249787	1			T1	14		T2	718		T3	739
valid_sources[0x2e]	249503	1			T1	14		T2	679		T3	728
valid_sources[0x2f]	251715	1			T1	40		T2	743		T3	698
valid_sources[0x30]	260861	1			T1	51		T2	690		T3	747
valid_sources[0x31]	290250	1			T1	39		T2	656		T3	670
valid_sources[0x32]	240546	1			T1	50		T2	682		T3	803
valid_sources[0x33]	272426	1			T1	13		T2	722		T3	781
valid_sources[0x34]	288837	1			T1	25		T2	728		T3	699
valid_sources[0x35]	277091	1			T1	24		T2	685		T3	836
valid_sources[0x36]	240197	1			T1	30		T2	669		T3	752
valid_sources[0x37]	322815	1			T1	46		T2	705		T3	715
valid_sources[0x38]	246292	1			T1	21		T2	692		T3	697
valid_sources[0x39]	275748	1			T1	24		T2	679		T3	725
valid_sources[0x3a]	247130	1			T1	41		T2	672		T3	673
valid_sources[0x3b]	290566	1			T1	29		T2	698		T3	735
valid_sources[0x3c]	324069	1			T1	4		T2	711		T3	763
valid_sources[0x3d]	252324	1			T1	19		T2	716		T3	706
valid_sources[0x3e]	269532	1			T1	38		T2	641		T3	758
valid_sources[0x3f]	270626	1			T1	23		T2	710		T3	749
valid_sources[0x40]	317566	1			T1	15		T2	719		T3	777
valid_sources[0x41]	272981	1			T1	31		T2	663		T3	722
valid_sources[0x42]	276603	1			T1	25		T2	716		T3	738
valid_sources[0x43]	297363	1			T1	6		T2	676		T3	631
valid_sources[0x44]	279096	1			T1	27		T2	739		T3	722
valid_sources[0x45]	311547	1			T1	34		T2	723		T3	805
valid_sources[0x46]	253034	1			T1	33		T2	665		T3	739
valid_sources[0x47]	245228	1			T1	39		T2	652		T3	633
valid_sources[0x48]	297553	1			T1	20		T2	679		T3	748
valid_sources[0x49]	309903	1			T1	13		T2	698		T3	768
valid_sources[0x4a]	260300	1			T1	26		T2	683		T3	756
valid_sources[0x4b]	248275	1			T1	27		T2	670		T3	756
valid_sources[0x4c]	245760	1			T1	31		T2	669		T3	736
valid_sources[0x4d]	285285	1			T1	15		T2	733		T3	725
valid_sources[0x4e]	261643	1			T1	21		T2	678		T3	768
valid_sources[0x4f]	253711	1			T1	40		T2	674		T3	723
valid_sources[0x50]	271446	1			T2	682		T3	716		T4	1400
valid_sources[0x51]	243520	1			T1	18		T2	696		T3	693
valid_sources[0x52]	255431	1			T1	17		T2	703		T3	701
valid_sources[0x53]	269604	1			T1	27		T2	651		T3	709
valid_sources[0x54]	364553	1			T1	27		T2	724		T3	704
valid_sources[0x55]	277938	1			T1	9		T2	620		T3	714
valid_sources[0x56]	378311	1			T1	13		T2	675		T3	727
valid_sources[0x57]	265348	1			T1	9		T2	689		T3	733
valid_sources[0x58]	280950	1			T1	18		T2	689		T3	776
valid_sources[0x59]	258183	1			T1	23		T2	677		T3	788
valid_sources[0x5a]	257326	1			T1	30		T2	717		T3	671
valid_sources[0x5b]	280395	1			T1	27		T2	678		T3	726
valid_sources[0x5c]	297317	1			T1	19		T2	725		T3	804
valid_sources[0x5d]	283470	1			T1	28		T2	727		T3	725
valid_sources[0x5e]	296698	1			T1	13		T2	699		T3	756
valid_sources[0x5f]	282889	1			T1	12		T2	681		T3	783
valid_sources[0x60]	289235	1			T1	25		T2	742		T3	727
valid_sources[0x61]	280819	1			T1	40		T2	711		T3	812
valid_sources[0x62]	253724	1			T1	21		T2	753		T3	788
valid_sources[0x63]	274572	1			T1	20		T2	680		T3	741
valid_sources[0x64]	285732	1			T1	25		T2	831		T3	753
valid_sources[0x65]	276780	1			T1	12		T2	668		T3	679
valid_sources[0x66]	248383	1			T1	11		T2	664		T3	707
valid_sources[0x67]	273102	1			T1	20		T2	698		T3	738
valid_sources[0x68]	251274	1			T1	20		T2	692		T3	722
valid_sources[0x69]	313887	1			T1	35		T2	717		T3	703
valid_sources[0x6a]	296103	1			T1	10		T2	685		T3	743
valid_sources[0x6b]	284284	1			T1	32		T2	714		T3	734
valid_sources[0x6c]	235305	1			T1	12		T2	671		T3	753
valid_sources[0x6d]	287758	1			T1	24		T2	701		T3	754
valid_sources[0x6e]	246876	1			T1	8		T2	691		T3	865
valid_sources[0x6f]	244887	1			T1	31		T2	730		T3	710
valid_sources[0x70]	285862	1			T1	17		T2	659		T3	737
valid_sources[0x71]	296090	1			T1	36		T2	702		T3	715
valid_sources[0x72]	253050	1			T1	26		T2	733		T3	740
valid_sources[0x73]	311407	1			T1	19		T2	690		T3	736
valid_sources[0x74]	249325	1			T1	36		T2	716		T3	798
valid_sources[0x75]	321079	1			T1	22		T2	717		T3	784
valid_sources[0x76]	254240	1			T1	26		T2	733		T3	760
valid_sources[0x77]	260028	1			T1	9		T2	694		T3	730
valid_sources[0x78]	235046	1			T1	24		T2	699		T3	743
valid_sources[0x79]	258920	1			T1	8		T2	741		T3	762
valid_sources[0x7a]	267715	1			T1	47		T2	669		T3	716
valid_sources[0x7b]	267827	1			T1	26		T2	718		T3	708
valid_sources[0x7c]	258959	1			T1	17		T2	733		T3	730
valid_sources[0x7d]	309534	1			T1	23		T2	683		T3	691
valid_sources[0x7e]	263608	1			T1	31		T2	665		T3	770
valid_sources[0x7f]	301117	1			T1	15		T2	652		T3	737
valid_sources[0x80]	303061	1			T1	43		T2	628		T3	779

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28315718

1

T1

2048

T2

80874

T3

85596

values[0x0]

all_enables

biggest_size

14257490

1

T1

1967

T2

40004

T3

42582

values[0x1]

all_enables

biggest_size

14256073

1

T1

2127

T2

40656

T3

42837

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

137791

1

T2

26

T3

1

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50375	1			T2	19		T7	20		T13	1019
values[0x0]	58843	1			T2	40		T3	1		T4	4
values[0x1]	62564	1			T2	35		T3	6		T4	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145835

1

T2

31

T3

2

T4

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	558	1			T13	25		T27	1		T115	2
valid_sources[0x01]	512	1			T2	2		T13	18		T6	1
valid_sources[0x02]	480	1			T13	26		T28	2		T71	1
valid_sources[0x03]	829	1			T13	3		T8	1		T138	1
valid_sources[0x04]	829	1			T2	2		T13	17		T53	1
valid_sources[0x05]	757	1			T13	18		T139	1		T53	3
valid_sources[0x06]	530	1			T13	14		T43	2		T44	5
valid_sources[0x07]	565	1			T13	17		T27	1		T36	1
valid_sources[0x08]	804	1			T13	22		T27	1		T15	241
valid_sources[0x09]	583	1			T13	15		T140	1		T53	2
valid_sources[0x0a]	828	1			T13	13		T9	2		T28	3
valid_sources[0x0b]	833	1			T13	39		T141	14		T43	6
valid_sources[0x0c]	634	1			T3	1		T13	11		T27	1
valid_sources[0x0d]	400	1			T13	15		T50	2		T115	1
valid_sources[0x0e]	661	1			T13	3		T42	1		T139	1
valid_sources[0x0f]	598	1			T13	7		T8	1		T27	3
valid_sources[0x10]	787	1			T13	23		T27	1		T53	1
valid_sources[0x11]	528	1			T13	6		T8	1		T21	4
valid_sources[0x12]	456	1			T13	20		T27	1		T53	1
valid_sources[0x13]	540	1			T13	3		T53	1		T28	2
valid_sources[0x14]	492	1			T11	24		T13	30		T8	1
valid_sources[0x15]	532	1			T13	28		T28	2		T126	3
valid_sources[0x16]	548	1			T13	11		T53	1		T28	1
valid_sources[0x17]	639	1			T13	13		T14	36		T21	1
valid_sources[0x18]	536	1			T3	1		T13	12		T9	7
valid_sources[0x19]	631	1			T13	17		T28	4		T43	27
valid_sources[0x1a]	836	1			T3	1		T13	8		T15	221
valid_sources[0x1b]	778	1			T13	9		T14	10		T53	1
valid_sources[0x1c]	1066	1			T13	25		T27	2		T28	108
valid_sources[0x1d]	547	1			T2	5		T13	29		T27	2
valid_sources[0x1e]	574	1			T2	1		T13	12		T43	2
valid_sources[0x1f]	707	1			T13	4		T28	4		T142	2
valid_sources[0x20]	426	1			T13	25		T43	15		T44	7
valid_sources[0x21]	802	1			T5	2		T13	49		T27	2
valid_sources[0x22]	674	1			T13	4		T94	1		T43	28
valid_sources[0x23]	539	1			T13	20		T27	1		T28	3
valid_sources[0x24]	1001	1			T13	26		T27	1		T115	1
valid_sources[0x25]	753	1			T13	8		T8	1		T21	3
valid_sources[0x26]	704	1			T13	9		T52	25		T28	208
valid_sources[0x27]	1006	1			T7	96		T13	13		T9	6
valid_sources[0x28]	461	1			T13	9		T28	1		T43	9
valid_sources[0x29]	434	1			T13	10		T27	1		T9	3
valid_sources[0x2a]	748	1			T4	7		T13	16		T143	1
valid_sources[0x2b]	607	1			T13	14		T27	1		T127	20
valid_sources[0x2c]	849	1			T13	8		T27	1		T15	73
valid_sources[0x2d]	527	1			T116	6		T43	19		T72	3
valid_sources[0x2e]	588	1			T13	9		T28	4		T43	25
valid_sources[0x2f]	624	1			T13	9		T27	2		T21	2
valid_sources[0x30]	516	1			T13	7		T8	1		T27	1
valid_sources[0x31]	491	1			T13	15		T21	2		T35	2
valid_sources[0x32]	440	1			T13	2		T28	6		T43	20
valid_sources[0x33]	694	1			T2	1		T13	16		T27	1
valid_sources[0x34]	495	1			T13	16		T144	1		T115	2
valid_sources[0x35]	573	1			T13	25		T28	2		T43	18
valid_sources[0x36]	508	1			T13	3		T27	1		T44	5
valid_sources[0x37]	756	1			T13	10		T8	2		T27	1
valid_sources[0x38]	606	1			T13	8		T116	3		T43	29
valid_sources[0x39]	600	1			T2	1		T13	11		T27	1
valid_sources[0x3a]	652	1			T13	18		T27	1		T52	13
valid_sources[0x3b]	773	1			T13	18		T15	215		T36	1
valid_sources[0x3c]	616	1			T13	15		T8	1		T39	1
valid_sources[0x3d]	573	1			T2	5		T13	9		T27	3
valid_sources[0x3e]	718	1			T2	5		T13	14		T145	1
valid_sources[0x3f]	631	1			T13	7		T42	1		T43	14
valid_sources[0x40]	500	1			T13	5		T143	1		T26	7
valid_sources[0x41]	750	1			T13	49		T35	1		T28	1
valid_sources[0x42]	520	1			T13	5		T27	1		T94	3
valid_sources[0x43]	467	1			T28	1		T43	37		T44	8
valid_sources[0x44]	523	1			T13	4		T115	3		T116	2
valid_sources[0x45]	592	1			T13	19		T27	1		T91	1
valid_sources[0x46]	451	1			T13	11		T115	1		T146	3
valid_sources[0x47]	621	1			T13	9		T27	1		T140	1
valid_sources[0x48]	1010	1			T13	14		T53	2		T28	86
valid_sources[0x49]	680	1			T13	11		T9	8		T140	1
valid_sources[0x4a]	556	1			T13	27		T21	1		T91	1
valid_sources[0x4b]	594	1			T13	18		T53	1		T28	1
valid_sources[0x4c]	639	1			T13	1		T36	1		T43	12
valid_sources[0x4d]	839	1			T13	15		T27	1		T16	9
valid_sources[0x4e]	1142	1			T13	3		T6	5		T8	1
valid_sources[0x4f]	662	1			T13	12		T15	151		T28	3
valid_sources[0x50]	567	1			T13	5		T28	80		T147	1
valid_sources[0x51]	507	1			T2	5		T13	20		T42	1
valid_sources[0x52]	727	1			T13	5		T43	18		T44	8
valid_sources[0x53]	525	1			T2	2		T13	21		T65	5
valid_sources[0x54]	708	1			T13	6		T21	2		T28	2
valid_sources[0x55]	605	1			T13	13		T8	1		T15	3
valid_sources[0x56]	519	1			T13	40		T43	21		T44	9
valid_sources[0x57]	903	1			T13	25		T51	8		T27	1
valid_sources[0x58]	782	1			T13	15		T27	1		T148	2
valid_sources[0x59]	546	1			T2	5		T13	36		T28	1
valid_sources[0x5a]	614	1			T13	8		T9	8		T28	1
valid_sources[0x5b]	466	1			T13	2		T27	1		T115	2
valid_sources[0x5c]	978	1			T13	38		T43	29		T44	4
valid_sources[0x5d]	694	1			T13	22		T115	4		T28	2
valid_sources[0x5e]	886	1			T13	10		T145	1		T142	1
valid_sources[0x5f]	884	1			T13	35		T27	1		T28	195
valid_sources[0x60]	660	1			T13	21		T27	1		T28	221
valid_sources[0x61]	480	1			T13	14		T8	1		T27	1
valid_sources[0x62]	509	1			T13	13		T15	1		T43	11
valid_sources[0x63]	823	1			T13	8		T15	317		T43	28
valid_sources[0x64]	749	1			T13	37		T28	169		T141	23
valid_sources[0x65]	557	1			T2	1		T13	18		T139	1
valid_sources[0x66]	558	1			T13	41		T53	2		T116	1
valid_sources[0x67]	575	1			T3	1		T13	7		T42	2
valid_sources[0x68]	517	1			T13	9		T27	1		T28	2
valid_sources[0x69]	624	1			T13	11		T142	1		T43	7
valid_sources[0x6a]	666	1			T3	2		T13	30		T8	2
valid_sources[0x6b]	540	1			T13	17		T133	4		T43	26
valid_sources[0x6c]	1037	1			T13	15		T8	1		T36	1
valid_sources[0x6d]	491	1			T13	9		T27	1		T71	1
valid_sources[0x6e]	773	1			T13	9		T53	1		T28	76
valid_sources[0x6f]	764	1			T2	3		T13	23		T27	1
valid_sources[0x70]	766	1			T13	13		T14	8		T27	1
valid_sources[0x71]	1083	1			T13	15		T28	266		T43	3
valid_sources[0x72]	757	1			T13	13		T27	1		T9	7
valid_sources[0x73]	687	1			T13	8		T8	1		T35	2
valid_sources[0x74]	833	1			T13	28		T70	1		T28	2
valid_sources[0x75]	574	1			T13	16		T140	1		T28	1
valid_sources[0x76]	520	1			T13	8		T8	2		T27	1
valid_sources[0x77]	764	1			T13	26		T27	2		T15	5
valid_sources[0x78]	642	1			T13	35		T21	3		T28	5
valid_sources[0x79]	730	1			T13	7		T9	5		T21	2
valid_sources[0x7a]	654	1			T13	28		T8	1		T27	1
valid_sources[0x7b]	1004	1			T13	41		T27	1		T53	2
valid_sources[0x7c]	615	1			T13	6		T115	2		T28	88
valid_sources[0x7d]	776	1			T13	14		T28	153		T43	29
valid_sources[0x7e]	672	1			T13	14		T8	1		T40	1
valid_sources[0x7f]	1097	1			T13	33		T16	1		T142	1
valid_sources[0x80]	600	1			T13	9		T15	81		T28	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37860

1

T2

8

T7

10

T13

968

values[0x0]

all_enables

biggest_size

50855

1

T2

9

T4

2

T7

9

values[0x1]

all_enables

biggest_size

49076

1

T2

9

T3

1

T7

7