Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13660045

1

T2

12928

T3

17030

T4

31142

full_word

52321140

1

T1

6142

T2

129213

T3

171015

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65980885	1			T1	6142		T2	142141		T3	188045
auto[TlIntgErrCmd]	108	1			T95	4		T96	3		T97	7
auto[TlIntgErrData]	92	1			T95	2		T96	5		T97	5
auto[TlIntgErrBoth]	100	1			T95	4		T96	2		T97	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30423890

1

T1

2048

T2

53466

T3

94073

auto[1]

35557295

1

T1

4094

T2

88675

T3

93972

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6551901	1			T2	4913		T3	8477		T4	15446
auto[TlIntgErrNone]	partial	auto[1]	7107865	1			T2	8015		T3	8553		T4	15696
auto[TlIntgErrNone]	full_word	auto[0]	23871856	1			T1	2048		T2	48553		T3	85596
auto[TlIntgErrNone]	full_word	auto[1]	28449263	1			T1	4094		T2	80660		T3	85419
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T95	1		T96	2		T97	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T95	3		T97	3		T118	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T121	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T96	1		T97	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T96	2		T97	3		T118	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T95	1		T96	2		T97	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T95	1		T96	1		T118	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T118	1		T124	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T95	2		T97	2		T118	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T95	2		T96	1		T97	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T96	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T97	1		-	-		-	-