Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	611510	1			T14	1136		T15	59		T16	14737
auto[1]	10617157	1			T2	2808		T3	79210		T4	142697
auto[2]	501574	1			T14	1030		T15	37		T16	13222
auto[3]	10516996	1			T2	2823		T3	78985		T4	143370

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14417758	1			T2	4657		T3	130872		T4	238419
auto[1]	2127549	1			T2	464		T3	12989		T4	22848
auto[2]	2119081	1			T2	464		T3	13033		T4	22760
auto[3]	3582849	1			T2	46		T3	1301		T4	2040

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8601809

1

T2

5624

T3

24

T4

37

auto[1]

13645428

1

T2

7

T3

158171

T4

286030

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	215007	1			T14	928		T15	50		T16	12185
auto[0]	auto[0]	auto[1]	21734	1			T14	92		T15	5		T16	1213
auto[0]	auto[0]	auto[2]	21938	1			T14	103		T15	4		T16	1212
auto[0]	auto[0]	auto[3]	6079	1			T14	13		T16	110		T42	4
auto[0]	auto[1]	auto[0]	3322027	1			T2	2319		T3	8		T4	13
auto[0]	auto[1]	auto[1]	341963	1			T2	223		T7	598		T10	3125
auto[0]	auto[1]	auto[2]	334746	1			T2	243		T3	5		T4	3
auto[0]	auto[1]	auto[3]	77236	1			T2	20		T7	51		T10	287
auto[0]	auto[2]	auto[0]	182071	1			T14	864		T15	26		T16	11172
auto[0]	auto[2]	auto[1]	18749	1			T14	89		T15	4		T16	1118
auto[0]	auto[2]	auto[2]	18014	1			T14	70		T15	7		T16	834
auto[0]	auto[2]	auto[3]	4707	1			T14	6		T16	89		T42	5
auto[0]	auto[3]	auto[0]	3287261	1			T2	2332		T3	11		T4	19
auto[0]	auto[3]	auto[1]	330915	1			T2	241		T4	1		T7	711
auto[0]	auto[3]	auto[2]	338817	1			T2	220		T4	1		T7	615
auto[0]	auto[3]	auto[3]	80545	1			T2	26		T7	62		T10	279
auto[1]	auto[0]	auto[0]	11483	1			T16	13		T133	2		T134	2
auto[1]	auto[0]	auto[1]	51667	1			T16	3		T132	1889		T135	1
auto[1]	auto[0]	auto[2]	51731	1			T16	1		T134	1		T128	1
auto[1]	auto[0]	auto[3]	231871	1			T70	1		T134	1		T132	8642
auto[1]	auto[1]	auto[0]	3693818	1			T2	2		T3	65622		T4	118971
auto[1]	auto[1]	auto[1]	674396	1			T3	6435		T4	10816		T10	8
auto[1]	auto[1]	auto[2]	649062	1			T2	1		T3	6478		T4	11869
auto[1]	auto[1]	auto[3]	1523909	1			T3	662		T4	1025		T10	1
auto[1]	auto[2]	auto[0]	10400	1			T14	1		T16	8		T133	2
auto[1]	auto[2]	auto[1]	45382	1			T134	1		T132	1722		T136	4406
auto[1]	auto[2]	auto[2]	40420	1			T16	1		T134	2		T128	1
auto[1]	auto[2]	auto[3]	181831	1			T132	5898		T137	2		T136	14732
auto[1]	auto[3]	auto[0]	3695691	1			T2	4		T3	65231		T4	119416
auto[1]	auto[3]	auto[1]	642743	1			T3	6554		T4	12031		T7	1
auto[1]	auto[3]	auto[2]	664353	1			T3	6550		T4	10887		T7	1
auto[1]	auto[3]	auto[3]	1476671	1			T3	639		T4	1015		T6	856