Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	290516455	128962	0	0
ctrl_regwen_rd_A	290516455	6411	0	0
exec_rd_A	290516455	5588	0	0
exec_regwen_rd_A	290516455	6109	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290516455	128962	0	0
T6	337965	0	0	0
T8	34284	0	0	0
T13	133642	3913	0	0
T15	0	2438	0	0
T17	33479	0	0	0
T18	33207	0	0	0
T19	65323	0	0	0
T20	9257	0	0	0
T28	0	8695	0	0
T30	2246	0	0	0
T43	0	4345	0	0
T44	0	1580	0	0
T45	0	3738	0	0
T46	0	631	0	0
T47	0	3133	0	0
T48	0	6357	0	0
T49	0	1885	0	0
T50	194512	0	0	0
T51	23317	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290516455	6411	0	0
T46	21555	156	0	0
T47	0	708	0	0
T98	0	511	0	0
T99	0	196	0	0
T100	0	327	0	0
T101	0	258	0	0
T102	0	176	0	0
T103	0	329	0	0
T104	0	471	0	0
T105	0	232	0	0
T106	967759	0	0	0
T107	8940	0	0	0
T108	342322	0	0	0
T109	171316	0	0	0
T110	7067	0	0	0
T111	1404	0	0	0
T112	13145	0	0	0
T113	372827	0	0	0
T114	263234	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290516455	5588	0	0
T46	21555	198	0	0
T47	0	522	0	0
T98	0	459	0	0
T99	0	170	0	0
T100	0	282	0	0
T101	0	294	0	0
T102	0	199	0	0
T103	0	310	0	0
T104	0	333	0	0
T105	0	145	0	0
T106	967759	0	0	0
T107	8940	0	0	0
T108	342322	0	0	0
T109	171316	0	0	0
T110	7067	0	0	0
T111	1404	0	0	0
T112	13145	0	0	0
T113	372827	0	0	0
T114	263234	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290516455	6109	0	0
T46	21555	133	0	0
T47	0	637	0	0
T98	0	528	0	0
T99	0	157	0	0
T100	0	258	0	0
T101	0	258	0	0
T102	0	134	0	0
T103	0	296	0	0
T104	0	400	0	0
T105	0	240	0	0
T106	967759	0	0	0
T107	8940	0	0	0
T108	342322	0	0	0
T109	171316	0	0	0
T110	7067	0	0	0
T111	1404	0	0	0
T112	13145	0	0	0
T113	372827	0	0	0
T114	263234	0	0	0