Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13956919	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57927576

1

T2

113304

T3

7492

T4

788

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35837910	1			T2	62057		T3	3742		T4	442
values[0x0]	16624756	1			T2	30277		T3	1917		T4	200
values[0x1]	19421829	1			T2	32332		T3	1833		T4	238

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6952051	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64932444

1

T2

118888

T3

7492

T4

837

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	244550	1			T2	248		T4	2		T5	19
valid_sources[0x01]	247221	1			T2	482		T4	2		T9	516
valid_sources[0x02]	235123	1			T2	370		T4	1		T5	1
valid_sources[0x03]	303335	1			T2	387		T4	2		T5	2
valid_sources[0x04]	272823	1			T2	311		T4	5		T5	7
valid_sources[0x05]	299904	1			T2	357		T4	6		T9	558
valid_sources[0x06]	260783	1			T2	400		T4	6		T9	510
valid_sources[0x07]	302790	1			T2	387		T4	1		T5	13
valid_sources[0x08]	255127	1			T2	425		T4	7		T5	1
valid_sources[0x09]	247150	1			T2	292		T4	3		T5	2
valid_sources[0x0a]	275410	1			T2	292		T4	4		T9	538
valid_sources[0x0b]	287109	1			T2	462		T4	4		T5	6
valid_sources[0x0c]	250599	1			T2	318		T4	6		T5	12
valid_sources[0x0d]	269313	1			T2	422		T4	6		T9	553
valid_sources[0x0e]	306610	1			T2	555		T4	4		T9	539
valid_sources[0x0f]	356513	1			T2	481		T4	5		T5	8
valid_sources[0x10]	292957	1			T2	337		T4	3		T5	18
valid_sources[0x11]	245648	1			T2	531		T4	5		T9	551
valid_sources[0x12]	295647	1			T2	370		T4	1		T5	3
valid_sources[0x13]	252187	1			T2	368		T4	3		T9	484
valid_sources[0x14]	281114	1			T2	375		T4	5		T5	1
valid_sources[0x15]	267740	1			T2	291		T4	5		T9	502
valid_sources[0x16]	294468	1			T2	326		T4	3		T9	517
valid_sources[0x17]	238517	1			T2	304		T4	2		T5	1
valid_sources[0x18]	333437	1			T2	434		T4	3		T9	575
valid_sources[0x19]	298744	1			T2	521		T4	2		T9	508
valid_sources[0x1a]	277353	1			T2	465		T4	5		T9	524
valid_sources[0x1b]	249165	1			T2	349		T4	3		T5	1
valid_sources[0x1c]	267196	1			T2	450		T4	5		T9	534
valid_sources[0x1d]	355048	1			T2	353		T4	4		T9	542
valid_sources[0x1e]	380962	1			T2	301		T4	1		T9	542
valid_sources[0x1f]	267259	1			T2	455		T9	529		T10	620
valid_sources[0x20]	247228	1			T2	353		T4	12		T5	17
valid_sources[0x21]	242096	1			T2	358		T4	6		T9	535
valid_sources[0x22]	365607	1			T2	319		T4	2		T5	8
valid_sources[0x23]	251568	1			T2	332		T4	3		T5	1
valid_sources[0x24]	292887	1			T2	297		T4	1		T9	520
valid_sources[0x25]	262517	1			T2	510		T4	5		T5	14
valid_sources[0x26]	243593	1			T2	296		T5	5		T9	513
valid_sources[0x27]	246121	1			T2	301		T4	3		T5	1
valid_sources[0x28]	260180	1			T2	336		T4	5		T5	10
valid_sources[0x29]	239629	1			T2	312		T4	3		T5	4
valid_sources[0x2a]	254415	1			T2	356		T4	7		T9	546
valid_sources[0x2b]	294587	1			T2	254		T4	2		T9	542
valid_sources[0x2c]	280913	1			T2	450		T4	2		T9	538
valid_sources[0x2d]	244517	1			T2	414		T4	3		T5	2
valid_sources[0x2e]	269334	1			T2	405		T4	5		T9	535
valid_sources[0x2f]	254240	1			T2	488		T4	3		T5	9
valid_sources[0x30]	276206	1			T2	313		T4	2		T5	4
valid_sources[0x31]	244288	1			T2	427		T4	1		T9	617
valid_sources[0x32]	241168	1			T2	468		T4	4		T5	7
valid_sources[0x33]	250003	1			T2	323		T4	3		T9	566
valid_sources[0x34]	267980	1			T2	442		T4	2		T9	575
valid_sources[0x35]	360604	1			T2	415		T4	5		T9	546
valid_sources[0x36]	247491	1			T2	313		T4	5		T5	13
valid_sources[0x37]	325884	1			T2	360		T4	1		T5	4
valid_sources[0x38]	269188	1			T2	399		T5	1		T9	528
valid_sources[0x39]	270816	1			T2	296		T4	3		T9	526
valid_sources[0x3a]	296078	1			T2	317		T4	4		T5	16
valid_sources[0x3b]	256653	1			T2	407		T4	4		T9	555
valid_sources[0x3c]	289191	1			T2	478		T4	2		T9	500
valid_sources[0x3d]	288982	1			T2	377		T5	12		T9	562
valid_sources[0x3e]	243562	1			T2	479		T4	4		T9	564
valid_sources[0x3f]	264344	1			T2	398		T4	3		T9	520
valid_sources[0x40]	298099	1			T2	398		T4	5		T5	12
valid_sources[0x41]	274787	1			T2	413		T4	5		T9	542
valid_sources[0x42]	279239	1			T2	323		T4	3		T5	11
valid_sources[0x43]	329446	1			T2	432		T4	1		T9	459
valid_sources[0x44]	258321	1			T2	387		T4	6		T5	3
valid_sources[0x45]	320653	1			T2	369		T4	6		T5	2
valid_sources[0x46]	301005	1			T2	358		T4	5		T5	9
valid_sources[0x47]	280750	1			T2	322		T4	4		T9	572
valid_sources[0x48]	260761	1			T2	475		T4	4		T5	3
valid_sources[0x49]	301729	1			T2	440		T4	4		T5	9
valid_sources[0x4a]	238090	1			T2	464		T4	5		T9	491
valid_sources[0x4b]	283299	1			T2	321		T4	1		T9	510
valid_sources[0x4c]	294440	1			T2	380		T4	5		T5	6
valid_sources[0x4d]	251349	1			T2	412		T4	5		T5	3
valid_sources[0x4e]	301236	1			T2	398		T4	3		T5	3
valid_sources[0x4f]	314962	1			T2	315		T4	1		T9	555
valid_sources[0x50]	277122	1			T2	493		T4	1		T5	20
valid_sources[0x51]	291062	1			T2	391		T4	3		T5	17
valid_sources[0x52]	254387	1			T2	337		T4	6		T9	580
valid_sources[0x53]	255991	1			T2	384		T4	3		T9	554
valid_sources[0x54]	329574	1			T2	374		T4	7		T9	526
valid_sources[0x55]	323197	1			T2	8624		T4	3		T5	2
valid_sources[0x56]	263161	1			T2	371		T4	2		T5	13
valid_sources[0x57]	294177	1			T2	5012		T4	1		T5	2
valid_sources[0x58]	262156	1			T2	278		T4	3		T5	1
valid_sources[0x59]	266672	1			T2	435		T4	2		T9	532
valid_sources[0x5a]	315170	1			T2	448		T4	3		T9	533
valid_sources[0x5b]	376955	1			T2	307		T4	1		T9	464
valid_sources[0x5c]	249639	1			T2	371		T4	2		T9	560
valid_sources[0x5d]	267699	1			T2	360		T4	5		T9	519
valid_sources[0x5e]	290889	1			T2	388		T4	4		T5	3
valid_sources[0x5f]	298587	1			T2	305		T4	7		T9	541
valid_sources[0x60]	252780	1			T2	347		T9	585		T10	574
valid_sources[0x61]	264849	1			T2	393		T4	1		T9	510
valid_sources[0x62]	284238	1			T2	472		T4	4		T5	8
valid_sources[0x63]	266845	1			T2	304		T4	5		T5	13
valid_sources[0x64]	256636	1			T2	364		T4	2		T5	6
valid_sources[0x65]	253025	1			T2	370		T4	4		T5	3
valid_sources[0x66]	308957	1			T2	417		T4	3		T9	523
valid_sources[0x67]	267029	1			T2	413		T4	2		T5	1
valid_sources[0x68]	310634	1			T2	457		T4	1		T9	545
valid_sources[0x69]	309043	1			T2	390		T4	8		T9	552
valid_sources[0x6a]	240023	1			T2	315		T4	7		T5	7
valid_sources[0x6b]	248207	1			T2	302		T4	6		T5	11
valid_sources[0x6c]	246400	1			T2	383		T4	3		T5	1
valid_sources[0x6d]	331151	1			T2	420		T4	8		T5	1
valid_sources[0x6e]	274824	1			T2	300		T4	2		T9	471
valid_sources[0x6f]	248184	1			T2	409		T4	2		T5	8
valid_sources[0x70]	285292	1			T2	417		T4	4		T5	7
valid_sources[0x71]	255986	1			T2	429		T4	1		T5	7
valid_sources[0x72]	277191	1			T2	412		T4	4		T5	15
valid_sources[0x73]	307713	1			T2	361		T4	5		T5	2
valid_sources[0x74]	273554	1			T2	381		T5	7		T9	508
valid_sources[0x75]	245651	1			T2	425		T4	3		T5	9
valid_sources[0x76]	329412	1			T2	278		T4	1		T9	617
valid_sources[0x77]	293226	1			T2	478		T4	1		T9	564
valid_sources[0x78]	295129	1			T2	388		T4	4		T5	1
valid_sources[0x79]	260956	1			T2	277		T4	2		T9	568
valid_sources[0x7a]	244223	1			T2	451		T4	4		T9	560
valid_sources[0x7b]	266946	1			T2	360		T4	4		T5	15
valid_sources[0x7c]	324497	1			T2	418		T4	5		T5	3
valid_sources[0x7d]	262296	1			T2	414		T4	4		T9	525
valid_sources[0x7e]	319787	1			T2	353		T4	2		T5	6
valid_sources[0x7f]	341135	1			T2	368		T4	5		T9	558
valid_sources[0x80]	279701	1			T2	386		T4	3		T9	578

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28862097

1

T2

56260

T3

3742

T4

398

values[0x0]

all_enables

biggest_size

14530161

1

T2

28569

T3

1917

T4

187

values[0x1]

all_enables

biggest_size

14535318

1

T2

28475

T3

1833

T4

203

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34031	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

127981

1

T1

1

T2

4

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47777	1			T6	49		T7	41		T16	516
values[0x0]	55180	1			T1	1		T2	5		T5	1
values[0x1]	59055	1			T1	1		T2	8		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

135973

1

T1

1

T2

4

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	634	1			T2	1		T6	1		T7	3
valid_sources[0x01]	776	1			T25	3		T26	6		T59	1
valid_sources[0x02]	806	1			T7	2		T26	14		T58	3
valid_sources[0x03]	510	1			T64	4		T16	3		T26	3
valid_sources[0x04]	440	1			T6	3		T7	2		T43	1
valid_sources[0x05]	622	1			T6	3		T7	3		T26	10
valid_sources[0x06]	546	1			T7	2		T20	4		T26	5
valid_sources[0x07]	716	1			T26	6		T58	3		T27	6
valid_sources[0x08]	607	1			T6	1		T7	2		T20	3
valid_sources[0x09]	750	1			T41	2		T26	3		T58	2
valid_sources[0x0a]	641	1			T6	1		T7	1		T26	4
valid_sources[0x0b]	665	1			T26	4		T27	1		T24	2
valid_sources[0x0c]	627	1			T6	1		T26	10		T58	3
valid_sources[0x0d]	758	1			T5	1		T41	2		T26	8
valid_sources[0x0e]	757	1			T9	1		T6	2		T7	1
valid_sources[0x0f]	722	1			T25	1		T26	6		T27	4
valid_sources[0x10]	703	1			T7	1		T16	3		T26	4
valid_sources[0x11]	532	1			T7	1		T26	3		T27	3
valid_sources[0x12]	464	1			T4	1		T6	2		T16	10
valid_sources[0x13]	668	1			T6	2		T41	2		T26	7
valid_sources[0x14]	548	1			T9	2		T6	2		T7	1
valid_sources[0x15]	479	1			T9	2		T6	1		T7	2
valid_sources[0x16]	450	1			T6	1		T7	2		T134	1
valid_sources[0x17]	468	1			T6	2		T7	1		T26	3
valid_sources[0x18]	646	1			T6	3		T27	6		T23	1
valid_sources[0x19]	666	1			T2	1		T6	2		T16	2
valid_sources[0x1a]	551	1			T6	2		T25	1		T43	1
valid_sources[0x1b]	542	1			T6	2		T7	1		T42	1
valid_sources[0x1c]	454	1			T26	8		T27	2		T59	1
valid_sources[0x1d]	462	1			T26	15		T58	1		T27	3
valid_sources[0x1e]	740	1			T2	1		T6	1		T8	11
valid_sources[0x1f]	551	1			T7	3		T55	4		T26	2
valid_sources[0x20]	652	1			T26	6		T27	2		T23	2
valid_sources[0x21]	536	1			T6	1		T15	1		T26	8
valid_sources[0x22]	400	1			T6	1		T58	2		T27	1
valid_sources[0x23]	622	1			T6	1		T135	9		T26	6
valid_sources[0x24]	513	1			T6	1		T42	1		T134	2
valid_sources[0x25]	532	1			T6	2		T15	1		T25	1
valid_sources[0x26]	509	1			T6	1		T7	2		T42	1
valid_sources[0x27]	754	1			T6	1		T7	1		T26	5
valid_sources[0x28]	463	1			T6	2		T7	1		T42	1
valid_sources[0x29]	550	1			T26	1		T58	4		T27	7
valid_sources[0x2a]	484	1			T7	6		T26	6		T58	3
valid_sources[0x2b]	573	1			T26	11		T58	3		T27	2
valid_sources[0x2c]	513	1			T7	3		T26	15		T27	1
valid_sources[0x2d]	465	1			T10	2		T26	10		T27	3
valid_sources[0x2e]	837	1			T6	4		T7	1		T26	9
valid_sources[0x2f]	561	1			T6	1		T7	2		T26	14
valid_sources[0x30]	581	1			T42	1		T26	4		T27	5
valid_sources[0x31]	507	1			T9	2		T52	1		T53	1
valid_sources[0x32]	604	1			T6	1		T7	1		T26	10
valid_sources[0x33]	540	1			T6	2		T26	8		T58	1
valid_sources[0x34]	407	1			T6	2		T26	6		T58	1
valid_sources[0x35]	701	1			T15	2		T26	5		T27	5
valid_sources[0x36]	540	1			T6	1		T7	1		T27	2
valid_sources[0x37]	565	1			T6	1		T7	4		T26	5
valid_sources[0x38]	697	1			T3	2		T10	3		T26	9
valid_sources[0x39]	516	1			T9	1		T6	1		T7	1
valid_sources[0x3a]	780	1			T14	1		T7	2		T26	2
valid_sources[0x3b]	630	1			T7	1		T43	1		T26	7
valid_sources[0x3c]	483	1			T2	1		T6	1		T42	3
valid_sources[0x3d]	1094	1			T7	1		T42	2		T26	6
valid_sources[0x3e]	650	1			T7	1		T52	1		T26	9
valid_sources[0x3f]	576	1			T7	3		T26	7		T27	3
valid_sources[0x40]	620	1			T26	7		T27	3		T23	2
valid_sources[0x41]	588	1			T26	2		T136	2		T27	1
valid_sources[0x42]	485	1			T6	2		T7	2		T26	6
valid_sources[0x43]	504	1			T7	2		T26	9		T27	3
valid_sources[0x44]	770	1			T42	2		T16	47		T26	6
valid_sources[0x45]	658	1			T6	2		T7	2		T52	1
valid_sources[0x46]	507	1			T6	1		T26	12		T58	1
valid_sources[0x47]	573	1			T6	1		T7	2		T26	2
valid_sources[0x48]	598	1			T26	2		T27	6		T24	1
valid_sources[0x49]	445	1			T6	1		T16	2		T26	4
valid_sources[0x4a]	756	1			T9	1		T7	2		T8	1
valid_sources[0x4b]	743	1			T6	2		T26	4		T27	1
valid_sources[0x4c]	658	1			T26	11		T27	4		T24	2
valid_sources[0x4d]	681	1			T6	1		T7	3		T41	8
valid_sources[0x4e]	453	1			T26	10		T27	3		T45	4
valid_sources[0x4f]	805	1			T6	1		T7	2		T26	7
valid_sources[0x50]	937	1			T42	1		T16	92		T43	1
valid_sources[0x51]	726	1			T6	2		T43	1		T26	5
valid_sources[0x52]	450	1			T6	1		T7	1		T26	8
valid_sources[0x53]	504	1			T2	1		T16	2		T26	12
valid_sources[0x54]	395	1			T7	4		T26	3		T58	2
valid_sources[0x55]	967	1			T6	1		T7	1		T26	21
valid_sources[0x56]	695	1			T6	2		T55	1		T26	9
valid_sources[0x57]	490	1			T6	1		T7	1		T26	17
valid_sources[0x58]	851	1			T26	11		T58	1		T27	4
valid_sources[0x59]	736	1			T6	2		T7	1		T26	14
valid_sources[0x5a]	482	1			T6	1		T7	1		T42	1
valid_sources[0x5b]	633	1			T7	1		T26	2		T59	1
valid_sources[0x5c]	769	1			T10	1		T6	1		T26	5
valid_sources[0x5d]	650	1			T6	1		T7	4		T26	5
valid_sources[0x5e]	783	1			T26	2		T58	1		T27	2
valid_sources[0x5f]	752	1			T16	74		T26	3		T24	2
valid_sources[0x60]	464	1			T26	7		T27	4		T137	3
valid_sources[0x61]	677	1			T9	2		T6	2		T55	1
valid_sources[0x62]	790	1			T16	300		T26	10		T27	3
valid_sources[0x63]	708	1			T7	1		T26	5		T27	10
valid_sources[0x64]	811	1			T57	1		T26	5		T27	5
valid_sources[0x65]	682	1			T42	1		T16	145		T26	1
valid_sources[0x66]	564	1			T6	1		T26	10		T27	5
valid_sources[0x67]	539	1			T7	1		T26	4		T58	1
valid_sources[0x68]	955	1			T9	2		T6	2		T42	2
valid_sources[0x69]	480	1			T9	1		T7	3		T16	3
valid_sources[0x6a]	894	1			T26	6		T27	1		T23	1
valid_sources[0x6b]	724	1			T6	2		T26	12		T27	4
valid_sources[0x6c]	504	1			T7	1		T16	97		T26	4
valid_sources[0x6d]	554	1			T26	15		T27	2		T24	3
valid_sources[0x6e]	676	1			T6	2		T53	1		T26	6
valid_sources[0x6f]	447	1			T6	2		T26	1		T27	1
valid_sources[0x70]	659	1			T6	1		T52	1		T26	8
valid_sources[0x71]	542	1			T6	1		T7	1		T26	11
valid_sources[0x72]	969	1			T6	2		T16	6		T26	3
valid_sources[0x73]	469	1			T16	40		T43	1		T26	9
valid_sources[0x74]	528	1			T6	1		T16	86		T43	1
valid_sources[0x75]	563	1			T6	1		T81	1		T26	16
valid_sources[0x76]	600	1			T1	1		T15	1		T26	15
valid_sources[0x77]	491	1			T2	1		T41	4		T26	6
valid_sources[0x78]	651	1			T7	1		T26	5		T58	1
valid_sources[0x79]	647	1			T7	3		T26	1		T58	1
valid_sources[0x7a]	529	1			T6	1		T26	1		T27	3
valid_sources[0x7b]	584	1			T6	1		T26	12		T27	2
valid_sources[0x7c]	1036	1			T9	4		T7	1		T41	1
valid_sources[0x7d]	580	1			T52	1		T25	1		T26	5
valid_sources[0x7e]	619	1			T20	3		T135	4		T26	9
valid_sources[0x7f]	524	1			T26	4		T58	1		T137	1
valid_sources[0x80]	574	1			T7	1		T26	4		T58	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35518

1

T6

24

T7

14

T16

450

values[0x0]

all_enables

biggest_size

47091

1

T1

1

T2

2

T5

1

values[0x1]

all_enables

biggest_size

45372

1

T2

2

T9

3

T12

1