Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13652730

1

T2

11362

T4

92

T5

913

full_word

53170033

1

T2

113304

T3

7492

T4

788

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66822453	1			T2	124666		T3	7492		T4	880
auto[TlIntgErrCmd]	112	1			T101	9		T102	5		T103	9
auto[TlIntgErrData]	100	1			T101	5		T102	3		T103	5
auto[TlIntgErrBoth]	98	1			T101	6		T102	2		T103	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30729964

1

T2

62057

T3

3742

T4

442

auto[1]

36092799

1

T2

62609

T3

3750

T4

438

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6541718	1			T2	5797		T4	44		T5	363
auto[TlIntgErrNone]	partial	auto[1]	7110729	1			T2	5565		T4	48		T5	550
auto[TlIntgErrNone]	full_word	auto[0]	24188111	1			T2	56260		T3	3742		T4	398
auto[TlIntgErrNone]	full_word	auto[1]	28981895	1			T2	57044		T3	3750		T4	390
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T101	2		T102	1		T103	5
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T101	7		T102	4		T103	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T119	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T103	1		T119	1		T125	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T101	1		T102	1		T103	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T101	3		T102	2		T103	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T101	1		T103	1		T116	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T119	2		T116	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T101	4		T102	1		T103	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T101	2		T103	5		T119	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T102	1		T119	1		T126	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T118	1		T127	1		T126	1