Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	858938	1			T2	12552		T6	4663		T13	19804
auto[1]	10162569	1			T2	3022		T3	3741		T4	2
auto[2]	720067	1			T2	11370		T6	4177		T13	14136
auto[3]	10041961	1			T2	1805		T3	3749		T4	1

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14356845	1			T2	22659		T3	7490		T4	1
auto[1]	2059823	1			T2	3132		T5	52		T9	4632
auto[2]	2045956	1			T2	2600		T4	1		T5	72
auto[3]	3320911	1			T2	358		T4	1		T5	807

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8552585

1

T2

28720

T3

7483

T4

3

auto[1]

13230950

1

T2

29

T3

7

T5

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	291787	1			T2	10422		T6	3814		T13	1
auto[0]	auto[0]	auto[1]	29340	1			T2	993		T6	421		T13	1
auto[0]	auto[0]	auto[2]	29722	1			T2	1018		T6	397		T55	1612
auto[0]	auto[0]	auto[3]	7220	1			T2	105		T6	27		T13	6
auto[0]	auto[1]	auto[0]	3235601	1			T2	1731		T3	3738		T9	23461
auto[0]	auto[1]	auto[1]	337625	1			T2	1019		T5	3		T9	2325
auto[0]	auto[1]	auto[2]	325284	1			T2	167		T4	1		T5	25
auto[0]	auto[1]	auto[3]	65204	1			T2	104		T4	1		T5	331
auto[0]	auto[2]	auto[0]	251933	1			T2	9579		T6	3543		T8	7
auto[0]	auto[2]	auto[1]	25886	1			T2	1017		T6	336		T13	1
auto[0]	auto[2]	auto[2]	23648	1			T2	685		T6	277		T13	1
auto[0]	auto[2]	auto[3]	5547	1			T2	76		T6	19		T55	138
auto[0]	auto[3]	auto[0]	3200236	1			T2	904		T3	3745		T4	1
auto[0]	auto[3]	auto[1]	322323	1			T2	100		T5	49		T9	2304
auto[0]	auto[3]	auto[2]	333086	1			T2	727		T5	47		T9	2302
auto[0]	auto[3]	auto[3]	68143	1			T2	73		T5	473		T9	258
auto[1]	auto[0]	auto[0]	16906	1			T2	11		T6	4		T13	645
auto[1]	auto[0]	auto[1]	74535	1			T2	1		T13	3007		T55	1
auto[1]	auto[0]	auto[2]	74128	1			T2	2		T13	2976		T43	1
auto[1]	auto[0]	auto[3]	335300	1			T13	13168		T94	20839		T96	8683
auto[1]	auto[1]	auto[0]	3672521	1			T2	1		T3	3		T9	20
auto[1]	auto[1]	auto[1]	626114	1			T9	1		T10	6342		T12	5786
auto[1]	auto[1]	auto[2]	587397	1			T9	2		T10	5956		T12	5658
auto[1]	auto[1]	auto[3]	1312823	1			T10	665		T12	613		T7	1
auto[1]	auto[2]	auto[0]	14557	1			T2	10		T6	2		T13	585
auto[1]	auto[2]	auto[1]	65202	1			T2	2		T13	2705		T55	1
auto[1]	auto[2]	auto[2]	60711	1			T2	1		T13	2008		T55	1
auto[1]	auto[2]	auto[3]	272583	1			T13	8836		T94	17272		T96	9592
auto[1]	auto[3]	auto[0]	3673304	1			T2	1		T3	4		T9	17
auto[1]	auto[3]	auto[1]	578798	1			T9	2		T10	6251		T12	5612
auto[1]	auto[3]	auto[2]	611980	1			T9	1		T10	6211		T12	5608
auto[1]	auto[3]	auto[3]	1254091	1			T5	3		T10	638		T12	576