Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	303721906	120704	0	0
ctrl_regwen_rd_A	303721906	6448	0	0
exec_rd_A	303721906	5681	0	0
exec_regwen_rd_A	303721906	6421	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303721906	120704	0	0
T8	15672	0	0	0
T16	172757	1956	0	0
T20	986	0	0	0
T25	687227	0	0	0
T26	0	1932	0	0
T27	0	826	0	0
T45	0	319	0	0
T46	0	754	0	0
T47	0	981	0	0
T48	0	2254	0	0
T49	0	5079	0	0
T50	0	2790	0	0
T51	0	4676	0	0
T52	277293	0	0	0
T53	139745	0	0	0
T54	14416	0	0	0
T55	187278	0	0	0
T56	16530	0	0	0
T57	283029	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303721906	6448	0	0
T27	63065	210	0	0
T44	158496	0	0	0
T45	0	52	0	0
T46	0	256	0	0
T47	0	268	0	0
T59	853137	0	0	0
T92	291520	0	0	0
T93	264671	0	0	0
T104	0	553	0	0
T105	0	464	0	0
T106	0	536	0	0
T107	0	593	0	0
T108	0	248	0	0
T109	0	162	0	0
T110	13552	0	0	0
T111	96432	0	0	0
T112	20573	0	0	0
T113	65693	0	0	0
T114	12500	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303721906	5681	0	0
T27	63065	182	0	0
T44	158496	0	0	0
T45	0	28	0	0
T46	0	212	0	0
T47	0	195	0	0
T59	853137	0	0	0
T92	291520	0	0	0
T93	264671	0	0	0
T104	0	369	0	0
T105	0	368	0	0
T106	0	430	0	0
T107	0	423	0	0
T108	0	182	0	0
T109	0	101	0	0
T110	13552	0	0	0
T111	96432	0	0	0
T112	20573	0	0	0
T113	65693	0	0	0
T114	12500	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303721906	6421	0	0
T27	63065	222	0	0
T44	158496	0	0	0
T45	0	54	0	0
T46	0	381	0	0
T47	0	173	0	0
T59	853137	0	0	0
T92	291520	0	0	0
T93	264671	0	0	0
T104	0	466	0	0
T105	0	330	0	0
T106	0	553	0	0
T107	0	478	0	0
T108	0	249	0	0
T109	0	167	0	0
T110	13552	0	0	0
T111	96432	0	0	0
T112	20573	0	0	0
T113	65693	0	0	0
T114	12500	0	0	0