Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15008510	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

62022427

1

T1

2836

T2

35861

T3

43383

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38405888	1			T1	1571		T2	19802		T3	118807
values[0x0]	17811231	1			T1	754		T2	9557		T3	39844
values[0x1]	20813818	1			T1	808		T2	10118		T3	79060

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7480192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

69550745

1

T1

2975

T2

37661

T3

141035

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	310437	1			T2	119		T3	994		T4	14
valid_sources[0x01]	285583	1			T2	183		T3	930		T4	28
valid_sources[0x02]	338460	1			T1	76		T2	165		T3	900
valid_sources[0x03]	293456	1			T2	54		T3	875		T4	22
valid_sources[0x04]	322320	1			T2	149		T3	910		T4	30
valid_sources[0x05]	318774	1			T2	109		T3	902		T4	30
valid_sources[0x06]	307179	1			T2	146		T3	996		T4	26
valid_sources[0x07]	321615	1			T1	43		T2	93		T3	979
valid_sources[0x08]	303802	1			T1	13		T2	165		T3	954
valid_sources[0x09]	265325	1			T1	96		T2	134		T3	879
valid_sources[0x0a]	278484	1			T1	29		T2	155		T3	914
valid_sources[0x0b]	300068	1			T1	80		T2	117		T3	911
valid_sources[0x0c]	291183	1			T2	98		T3	889		T4	15
valid_sources[0x0d]	379284	1			T2	176		T3	948		T4	22
valid_sources[0x0e]	291478	1			T1	1		T2	211		T3	889
valid_sources[0x0f]	274304	1			T2	97		T3	937		T4	18
valid_sources[0x10]	273661	1			T2	159		T3	954		T4	28
valid_sources[0x11]	263523	1			T2	111		T3	894		T4	28
valid_sources[0x12]	264777	1			T1	82		T2	185		T3	925
valid_sources[0x13]	309998	1			T2	69		T3	940		T4	21
valid_sources[0x14]	267039	1			T1	72		T2	196		T3	964
valid_sources[0x15]	327544	1			T2	188		T3	969		T4	25
valid_sources[0x16]	277959	1			T2	168		T3	963		T4	29
valid_sources[0x17]	273333	1			T2	113		T3	898		T4	19
valid_sources[0x18]	318184	1			T2	134		T3	932		T4	23
valid_sources[0x19]	353485	1			T2	118		T3	960		T4	26
valid_sources[0x1a]	275850	1			T1	12		T2	210		T3	920
valid_sources[0x1b]	322991	1			T1	73		T2	116		T3	923
valid_sources[0x1c]	296911	1			T2	138		T3	910		T4	26
valid_sources[0x1d]	302488	1			T2	123		T3	965		T4	16
valid_sources[0x1e]	281044	1			T2	227		T3	951		T4	17
valid_sources[0x1f]	303709	1			T1	32		T2	147		T3	959
valid_sources[0x20]	300872	1			T2	120		T3	946		T4	23
valid_sources[0x21]	307651	1			T1	97		T2	94		T3	909
valid_sources[0x22]	272195	1			T2	153		T3	953		T4	20
valid_sources[0x23]	287443	1			T1	1		T2	288		T3	920
valid_sources[0x24]	290138	1			T2	89		T3	939		T4	22
valid_sources[0x25]	287024	1			T2	131		T3	1011		T4	24
valid_sources[0x26]	298630	1			T2	91		T3	919		T4	24
valid_sources[0x27]	317004	1			T2	141		T3	950		T4	34
valid_sources[0x28]	311218	1			T2	132		T3	939		T4	23
valid_sources[0x29]	285465	1			T1	153		T2	187		T3	903
valid_sources[0x2a]	286114	1			T2	156		T3	873		T4	20
valid_sources[0x2b]	294982	1			T1	1		T2	223		T3	1042
valid_sources[0x2c]	308836	1			T2	134		T3	894		T4	22
valid_sources[0x2d]	281571	1			T2	131		T3	913		T4	23
valid_sources[0x2e]	410683	1			T2	102		T3	880		T4	18
valid_sources[0x2f]	318268	1			T1	14		T2	170		T3	952
valid_sources[0x30]	389658	1			T1	1		T2	181		T3	896
valid_sources[0x31]	302612	1			T2	109		T3	940		T4	25
valid_sources[0x32]	278688	1			T2	158		T3	910		T4	18
valid_sources[0x33]	295211	1			T2	116		T3	924		T4	12
valid_sources[0x34]	310729	1			T2	141		T3	929		T4	27
valid_sources[0x35]	303937	1			T2	141		T3	915		T4	19
valid_sources[0x36]	273289	1			T2	125		T3	928		T4	21
valid_sources[0x37]	268586	1			T2	141		T3	919		T4	32
valid_sources[0x38]	275495	1			T2	191		T3	958		T4	22
valid_sources[0x39]	317558	1			T2	154		T3	899		T4	25
valid_sources[0x3a]	268595	1			T2	137		T3	949		T4	21
valid_sources[0x3b]	332739	1			T1	4		T2	146		T3	930
valid_sources[0x3c]	267259	1			T1	46		T2	157		T3	909
valid_sources[0x3d]	349124	1			T2	162		T3	949		T4	25
valid_sources[0x3e]	293295	1			T1	2		T2	204		T3	913
valid_sources[0x3f]	422259	1			T2	168		T3	846		T4	21
valid_sources[0x40]	338721	1			T1	45		T2	99		T3	894
valid_sources[0x41]	284058	1			T1	38		T2	160		T3	918
valid_sources[0x42]	277505	1			T1	27		T2	193		T3	872
valid_sources[0x43]	319163	1			T1	1		T2	204		T3	946
valid_sources[0x44]	267980	1			T2	167		T3	962		T4	25
valid_sources[0x45]	350886	1			T2	139		T3	889		T4	27
valid_sources[0x46]	367680	1			T2	141		T3	884		T4	20
valid_sources[0x47]	281580	1			T1	17		T2	138		T3	976
valid_sources[0x48]	289463	1			T1	4		T2	253		T3	855
valid_sources[0x49]	304119	1			T1	2		T2	210		T3	961
valid_sources[0x4a]	297787	1			T2	113		T3	946		T4	28
valid_sources[0x4b]	269672	1			T2	113		T3	929		T4	19
valid_sources[0x4c]	279611	1			T1	44		T2	154		T3	940
valid_sources[0x4d]	289535	1			T1	17		T2	201		T3	939
valid_sources[0x4e]	362648	1			T2	182		T3	938		T4	19
valid_sources[0x4f]	310531	1			T2	190		T3	904		T4	28
valid_sources[0x50]	332532	1			T2	190		T3	969		T4	23
valid_sources[0x51]	291406	1			T2	153		T3	954		T4	16
valid_sources[0x52]	273818	1			T1	75		T2	244		T3	880
valid_sources[0x53]	362735	1			T1	46		T2	219		T3	871
valid_sources[0x54]	314533	1			T2	167		T3	946		T4	24
valid_sources[0x55]	305801	1			T2	167		T3	911		T4	29
valid_sources[0x56]	302774	1			T2	134		T3	933		T4	27
valid_sources[0x57]	329403	1			T1	2		T2	150		T3	917
valid_sources[0x58]	268652	1			T2	291		T3	884		T4	27
valid_sources[0x59]	350345	1			T1	3		T2	159		T3	952
valid_sources[0x5a]	295463	1			T2	153		T3	926		T4	23
valid_sources[0x5b]	283417	1			T2	200		T3	886		T4	20
valid_sources[0x5c]	284756	1			T2	110		T3	916		T4	20
valid_sources[0x5d]	283821	1			T2	189		T3	935		T4	17
valid_sources[0x5e]	319010	1			T2	166		T3	931		T4	19
valid_sources[0x5f]	295840	1			T1	46		T2	184		T3	982
valid_sources[0x60]	293801	1			T2	121		T3	889		T4	18
valid_sources[0x61]	298984	1			T2	260		T3	934		T4	26
valid_sources[0x62]	321012	1			T2	172		T3	916		T4	25
valid_sources[0x63]	299886	1			T1	29		T2	115		T3	932
valid_sources[0x64]	323634	1			T2	125		T3	865		T4	24
valid_sources[0x65]	298333	1			T2	117		T3	931		T4	27
valid_sources[0x66]	281810	1			T2	96		T3	889		T4	30
valid_sources[0x67]	277863	1			T1	28		T2	110		T3	941
valid_sources[0x68]	355250	1			T2	133		T3	948		T4	26
valid_sources[0x69]	313988	1			T2	208		T3	905		T4	24
valid_sources[0x6a]	276608	1			T2	76		T3	885		T4	25
valid_sources[0x6b]	275362	1			T1	87		T2	120		T3	975
valid_sources[0x6c]	292550	1			T2	163		T3	999		T4	21
valid_sources[0x6d]	324292	1			T2	107		T3	924		T4	20
valid_sources[0x6e]	272171	1			T2	129		T3	922		T4	25
valid_sources[0x6f]	269789	1			T2	161		T3	944		T4	25
valid_sources[0x70]	313996	1			T1	46		T2	121		T3	939
valid_sources[0x71]	401088	1			T2	108		T3	947		T4	20
valid_sources[0x72]	294070	1			T2	133		T3	870		T4	24
valid_sources[0x73]	388995	1			T2	136		T3	901		T4	31
valid_sources[0x74]	324284	1			T2	190		T3	906		T4	20
valid_sources[0x75]	300015	1			T1	19		T2	110		T3	967
valid_sources[0x76]	380794	1			T2	173		T3	873		T4	22
valid_sources[0x77]	337845	1			T1	2		T2	120		T3	957
valid_sources[0x78]	286757	1			T1	55		T2	98		T3	941
valid_sources[0x79]	283193	1			T2	219		T3	933		T4	15
valid_sources[0x7a]	299242	1			T1	16		T2	73		T3	926
valid_sources[0x7b]	315525	1			T2	74		T3	939		T4	27
valid_sources[0x7c]	289130	1			T1	15		T2	155		T3	950
valid_sources[0x7d]	331501	1			T2	172		T3	901		T4	26
valid_sources[0x7e]	277185	1			T2	217		T3	905		T4	16
valid_sources[0x7f]	276952	1			T1	30		T2	198		T3	923
valid_sources[0x80]	289865	1			T1	57		T2	213		T3	905

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30908740

1

T1

1436

T2

18011

T3

21807

values[0x0]

all_enables

biggest_size

15557364

1

T1

700

T2

9030

T3

10797

values[0x1]

all_enables

biggest_size

15556323

1

T1

700

T2

8820

T3

10779

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

138114

1

T1

24

T3

1

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49866	1			T1	30		T5	25		T6	25
values[0x0]	59068	1			T1	21		T2	4		T3	2
values[0x1]	63374	1			T1	15		T2	5		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26045	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

146263

1

T1

30

T2

3

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	492	1			T12	2		T65	1		T45	2
valid_sources[0x01]	550	1			T12	2		T64	1		T65	1
valid_sources[0x02]	573	1			T12	1		T27	1		T109	1
valid_sources[0x03]	606	1			T12	1		T65	2		T46	5
valid_sources[0x04]	577	1			T11	3		T6	1		T12	2
valid_sources[0x05]	509	1			T89	1		T151	2		T152	1
valid_sources[0x06]	722	1			T6	1		T12	3		T65	3
valid_sources[0x07]	979	1			T12	1		T64	5		T28	2
valid_sources[0x08]	975	1			T12	2		T27	1		T45	3
valid_sources[0x09]	601	1			T65	1		T108	1		T27	2
valid_sources[0x0a]	719	1			T12	1		T64	1		T45	2
valid_sources[0x0b]	1019	1			T11	13		T12	2		T65	1
valid_sources[0x0c]	621	1			T63	1		T65	1		T27	2
valid_sources[0x0d]	660	1			T12	1		T64	1		T90	6
valid_sources[0x0e]	562	1			T153	2		T27	2		T154	17
valid_sources[0x0f]	617	1			T6	1		T64	2		T65	1
valid_sources[0x10]	720	1			T12	2		T64	3		T27	1
valid_sources[0x11]	659	1			T14	1		T12	1		T65	2
valid_sources[0x12]	936	1			T12	2		T65	2		T27	1
valid_sources[0x13]	976	1			T12	1		T64	2		T65	1
valid_sources[0x14]	589	1			T12	2		T65	6		T27	2
valid_sources[0x15]	486	1			T64	1		T155	1		T30	2
valid_sources[0x16]	882	1			T14	3		T6	1		T64	2
valid_sources[0x17]	941	1			T6	1		T12	3		T65	1
valid_sources[0x18]	536	1			T12	1		T27	2		T156	3
valid_sources[0x19]	660	1			T12	3		T20	1		T46	2
valid_sources[0x1a]	664	1			T12	5		T65	1		T28	2
valid_sources[0x1b]	780	1			T12	1		T65	2		T27	2
valid_sources[0x1c]	553	1			T12	1		T30	1		T65	5
valid_sources[0x1d]	833	1			T12	3		T64	1		T30	1
valid_sources[0x1e]	491	1			T11	1		T12	4		T45	1
valid_sources[0x1f]	503	1			T6	1		T12	1		T65	3
valid_sources[0x20]	622	1			T12	3		T27	1		T151	1
valid_sources[0x21]	1127	1			T6	1		T12	1		T65	2
valid_sources[0x22]	604	1			T106	1		T30	8		T65	1
valid_sources[0x23]	578	1			T6	1		T65	3		T20	1
valid_sources[0x24]	708	1			T12	1		T27	2		T45	3
valid_sources[0x25]	847	1			T12	2		T27	2		T46	5
valid_sources[0x26]	667	1			T6	1		T12	1		T65	1
valid_sources[0x27]	536	1			T12	2		T27	3		T157	1
valid_sources[0x28]	654	1			T12	2		T30	1		T67	1
valid_sources[0x29]	542	1			T64	1		T30	3		T65	3
valid_sources[0x2a]	553	1			T12	3		T64	1		T27	2
valid_sources[0x2b]	567	1			T6	1		T79	2		T64	1
valid_sources[0x2c]	513	1			T64	1		T65	2		T45	1
valid_sources[0x2d]	587	1			T12	2		T112	5		T20	2
valid_sources[0x2e]	876	1			T12	2		T64	1		T65	1
valid_sources[0x2f]	514	1			T12	1		T27	1		T90	1
valid_sources[0x30]	611	1			T12	2		T158	7		T64	2
valid_sources[0x31]	650	1			T40	7		T159	1		T146	1
valid_sources[0x32]	916	1			T2	2		T12	1		T65	4
valid_sources[0x33]	653	1			T65	1		T27	1		T45	1
valid_sources[0x34]	877	1			T6	1		T12	1		T64	1
valid_sources[0x35]	624	1			T160	1		T161	2		T162	5
valid_sources[0x36]	663	1			T12	1		T105	6		T27	1
valid_sources[0x37]	668	1			T12	1		T30	1		T163	1
valid_sources[0x38]	811	1			T164	12		T65	3		T20	2
valid_sources[0x39]	555	1			T6	1		T165	1		T65	1
valid_sources[0x3a]	802	1			T18	1		T12	1		T65	2
valid_sources[0x3b]	503	1			T12	1		T30	3		T27	1
valid_sources[0x3c]	498	1			T15	2		T64	1		T30	3
valid_sources[0x3d]	605	1			T10	47		T12	4		T64	1
valid_sources[0x3e]	537	1			T6	2		T12	1		T166	1
valid_sources[0x3f]	569	1			T2	3		T12	1		T67	1
valid_sources[0x40]	862	1			T12	3		T46	2		T151	1
valid_sources[0x41]	703	1			T12	1		T155	1		T65	1
valid_sources[0x42]	544	1			T12	1		T64	1		T27	1
valid_sources[0x43]	573	1			T12	1		T79	1		T167	2
valid_sources[0x44]	676	1			T27	2		T109	1		T168	1
valid_sources[0x45]	679	1			T12	3		T30	2		T65	1
valid_sources[0x46]	534	1			T45	1		T46	3		T152	1
valid_sources[0x47]	979	1			T65	1		T27	3		T46	2
valid_sources[0x48]	619	1			T12	1		T64	1		T65	1
valid_sources[0x49]	877	1			T12	2		T64	1		T65	1
valid_sources[0x4a]	850	1			T12	3		T65	2		T27	2
valid_sources[0x4b]	529	1			T12	2		T27	2		T45	2
valid_sources[0x4c]	614	1			T65	5		T40	2		T29	55
valid_sources[0x4d]	602	1			T12	1		T65	1		T27	3
valid_sources[0x4e]	1001	1			T86	1		T27	2		T151	1
valid_sources[0x4f]	681	1			T107	1		T30	1		T27	1
valid_sources[0x50]	592	1			T3	1		T12	1		T64	1
valid_sources[0x51]	552	1			T12	2		T64	2		T27	1
valid_sources[0x52]	757	1			T28	1		T45	1		T169	1
valid_sources[0x53]	480	1			T12	1		T45	1		T151	1
valid_sources[0x54]	708	1			T12	1		T108	1		T46	7
valid_sources[0x55]	594	1			T12	4		T64	1		T27	2
valid_sources[0x56]	537	1			T12	1		T65	1		T28	1
valid_sources[0x57]	672	1			T12	4		T65	2		T45	2
valid_sources[0x58]	515	1			T12	3		T27	1		T40	4
valid_sources[0x59]	641	1			T6	1		T12	4		T27	1
valid_sources[0x5a]	514	1			T30	1		T27	1		T46	4
valid_sources[0x5b]	541	1			T11	3		T20	1		T40	8
valid_sources[0x5c]	538	1			T12	1		T79	1		T46	1
valid_sources[0x5d]	526	1			T65	2		T170	2		T27	1
valid_sources[0x5e]	712	1			T12	1		T30	2		T65	1
valid_sources[0x5f]	691	1			T6	1		T12	1		T65	1
valid_sources[0x60]	693	1			T6	1		T30	1		T27	2
valid_sources[0x61]	687	1			T5	110		T64	2		T65	1
valid_sources[0x62]	1004	1			T6	1		T12	1		T65	2
valid_sources[0x63]	552	1			T6	2		T12	1		T171	1
valid_sources[0x64]	859	1			T6	1		T12	1		T30	1
valid_sources[0x65]	760	1			T12	2		T45	3		T46	5
valid_sources[0x66]	624	1			T1	66		T65	2		T40	4
valid_sources[0x67]	451	1			T12	3		T27	3		T151	1
valid_sources[0x68]	628	1			T64	1		T65	1		T27	1
valid_sources[0x69]	1346	1			T106	3		T64	1		T27	3
valid_sources[0x6a]	817	1			T6	1		T12	4		T64	2
valid_sources[0x6b]	740	1			T6	1		T30	1		T169	2
valid_sources[0x6c]	503	1			T12	1		T64	1		T65	1
valid_sources[0x6d]	682	1			T7	1		T65	1		T28	3
valid_sources[0x6e]	787	1			T12	1		T79	2		T64	1
valid_sources[0x6f]	581	1			T12	1		T65	1		T27	2
valid_sources[0x70]	600	1			T12	1		T65	2		T27	1
valid_sources[0x71]	608	1			T12	1		T65	1		T27	1
valid_sources[0x72]	653	1			T46	2		T151	1		T145	1
valid_sources[0x73]	835	1			T12	1		T106	1		T27	1
valid_sources[0x74]	664	1			T12	2		T64	1		T65	2
valid_sources[0x75]	433	1			T12	1		T150	11		T64	1
valid_sources[0x76]	568	1			T65	1		T27	2		T46	4
valid_sources[0x77]	508	1			T12	1		T20	2		T40	1
valid_sources[0x78]	838	1			T65	1		T45	4		T151	1
valid_sources[0x79]	499	1			T12	4		T39	2		T46	4
valid_sources[0x7a]	594	1			T12	1		T64	1		T65	1
valid_sources[0x7b]	597	1			T6	1		T30	2		T27	1
valid_sources[0x7c]	736	1			T11	2		T12	2		T64	1
valid_sources[0x7d]	551	1			T12	2		T107	1		T65	2
valid_sources[0x7e]	753	1			T12	1		T30	3		T65	1
valid_sources[0x7f]	779	1			T65	1		T27	1		T46	5
valid_sources[0x80]	642	1			T6	1		T12	2		T64	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37664

1

T1

15

T5

8

T6

10

values[0x0]

all_enables

biggest_size

50882

1

T1

8

T3

1

T10

7

values[0x1]

all_enables

biggest_size

49568

1

T1

1

T7

1

T10

7