Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 14681307 1 T1 18 T2 3616 T3 194328
full_word 56902489 1 T1 193 T2 35861 T3 43383



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 71583466 1 T1 211 T2 39477 T3 237711
auto[TlIntgErrCmd] 105 1 T116 2 T117 5 T118 6
auto[TlIntgErrData] 116 1 T116 6 T117 4 T118 6
auto[TlIntgErrBoth] 109 1 T116 2 T117 1 T118 8



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32902028 1 T1 116 T2 19802 T3 118807
auto[1] 38681768 1 T1 95 T2 19675 T3 118904



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 7030187 1 T1 12 T2 1791 T3 97000
auto[TlIntgErrNone] partial auto[1] 7650812 1 T1 6 T2 1825 T3 97328
auto[TlIntgErrNone] full_word auto[0] 25871694 1 T1 104 T2 18011 T3 21807
auto[TlIntgErrNone] full_word auto[1] 31030773 1 T1 89 T2 17850 T3 21576
auto[TlIntgErrCmd] partial auto[0] 40 1 T116 1 T117 2 T118 3
auto[TlIntgErrCmd] partial auto[1] 61 1 T116 1 T117 3 T118 3
auto[TlIntgErrCmd] full_word auto[0] 2 1 T135 1 T139 1 - -
auto[TlIntgErrCmd] full_word auto[1] 2 1 T140 1 T141 1 - -
auto[TlIntgErrData] partial auto[0] 54 1 T116 6 T117 1 T118 2
auto[TlIntgErrData] partial auto[1] 53 1 T117 2 T118 3 T133 1
auto[TlIntgErrData] full_word auto[0] 5 1 T117 1 T118 1 T142 1
auto[TlIntgErrData] full_word auto[1] 4 1 T136 1 T143 1 T141 2
auto[TlIntgErrBoth] partial auto[0] 45 1 T116 1 T118 5 T134 2
auto[TlIntgErrBoth] partial auto[1] 55 1 T116 1 T118 2 T133 1
auto[TlIntgErrBoth] full_word auto[0] 1 1 T135 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 8 1 T117 1 T118 1 T133 1

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