Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	615263	1			T1	21		T6	16		T12	7726
auto[1]	11375084	1			T1	6		T2	9836		T3	13627
auto[2]	533024	1			T1	13		T6	20		T12	6844
auto[3]	11308573	1			T2	9634		T3	13634		T10	76010

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15232739	1			T1	31		T2	16181		T3	373
auto[1]	2313151	1			T1	6		T2	1570		T3	3182
auto[2]	2317218	1			T1	3		T2	1566		T3	3136
auto[3]	3968836	1			T2	153		T3	20570		T10	1137

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9350054

1

T1

40

T2

19452

T3

5

auto[1]

14481890

1

T2

18

T3

27256

T10

139

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	322126	1			T1	17		T6	15		T12	6413
auto[0]	auto[0]	auto[1]	32952	1			T1	2		T12	596		T17	1510
auto[0]	auto[0]	auto[2]	32723	1			T1	2		T6	1		T12	646
auto[0]	auto[0]	auto[3]	7854	1			T12	63		T17	150		T150	153
auto[0]	auto[1]	auto[0]	3511684	1			T1	3		T2	8173		T10	63127
auto[0]	auto[1]	auto[1]	372238	1			T1	3		T2	746		T3	1
auto[0]	auto[1]	auto[2]	357098	1			T2	826		T10	6360		T11	6075
auto[0]	auto[1]	auto[3]	87478	1			T2	81		T3	1		T10	577
auto[0]	auto[2]	auto[0]	280570	1			T1	11		T6	20		T12	5787
auto[0]	auto[2]	auto[1]	28727	1			T1	1		T12	601		T17	1286
auto[0]	auto[2]	auto[2]	26229	1			T1	1		T12	400		T17	1183
auto[0]	auto[2]	auto[3]	6316	1			T12	52		T17	130		T150	117
auto[0]	auto[3]	auto[0]	3471740	1			T2	7994		T10	63244		T11	60282
auto[0]	auto[3]	auto[1]	352663	1			T2	821		T10	6378		T11	5975
auto[0]	auto[3]	auto[2]	368801	1			T2	739		T10	5760		T11	5380
auto[0]	auto[3]	auto[3]	90855	1			T2	72		T3	3		T10	559
auto[1]	auto[0]	auto[0]	7446	1			T12	7		T17	11		T150	21
auto[1]	auto[0]	auto[1]	32664	1			T17	2		T150	1		T46	1
auto[1]	auto[0]	auto[2]	32513	1			T12	1		T17	1		T150	2
auto[1]	auto[0]	auto[3]	146985	1			T89	1		T45	1		T145	1
auto[1]	auto[1]	auto[0]	3816156	1			T2	7		T3	195		T10	52
auto[1]	auto[1]	auto[1]	739720	1			T2	2		T3	2419		T10	10
auto[1]	auto[1]	auto[2]	733986	1			T2	1		T3	768		T10	8
auto[1]	auto[1]	auto[3]	1756724	1			T3	10243		T78	955		T105	790
auto[1]	auto[2]	auto[0]	5978	1			T12	3		T17	8		T150	11
auto[1]	auto[2]	auto[1]	26122	1			T12	1		T17	1		T150	3
auto[1]	auto[2]	auto[2]	29002	1			T17	2		T45	1		T46	1
auto[1]	auto[2]	auto[3]	130080	1			T89	1		T148	10241		T149	14901
auto[1]	auto[3]	auto[0]	3817039	1			T2	7		T3	178		T10	56
auto[1]	auto[3]	auto[1]	728065	1			T2	1		T3	762		T10	11
auto[1]	auto[3]	auto[2]	736866	1			T3	2368		T10	1		T11	8
auto[1]	auto[3]	auto[3]	1742544	1			T3	10323		T10	1		T78	1010