Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	343219890	128064	0	0
ctrl_regwen_rd_A	343219890	6193	0	0
exec_rd_A	343219890	5477	0	0
exec_regwen_rd_A	343219890	6398	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343219890	128064	0	0
T32	139692	4318	0	0
T33	0	5009	0	0
T34	0	1040	0	0
T47	0	2269	0	0
T48	0	2173	0	0
T49	0	624	0	0
T50	0	5117	0	0
T51	0	868	0	0
T52	0	1968	0	0
T53	0	1597	0	0
T54	776753	0	0	0
T55	7159	0	0	0
T56	33310	0	0	0
T57	396960	0	0	0
T58	240818	0	0	0
T59	468993	0	0	0
T60	344995	0	0	0
T61	2397	0	0	0
T62	104135	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343219890	6193	0	0
T34	55640	421	0	0
T47	131331	0	0	0
T48	0	377	0	0
T49	0	231	0	0
T51	0	178	0	0
T53	0	212	0	0
T119	0	183	0	0
T120	0	497	0	0
T121	0	252	0	0
T122	0	876	0	0
T123	0	528	0	0
T124	10809	0	0	0
T125	223866	0	0	0
T126	13503	0	0	0
T127	31276	0	0	0
T128	371149	0	0	0
T129	43525	0	0	0
T130	158609	0	0	0
T131	16104	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343219890	5477	0	0
T34	55640	370	0	0
T47	131331	0	0	0
T48	0	363	0	0
T49	0	138	0	0
T51	0	209	0	0
T53	0	193	0	0
T119	0	228	0	0
T120	0	370	0	0
T121	0	155	0	0
T122	0	784	0	0
T123	0	411	0	0
T124	10809	0	0	0
T125	223866	0	0	0
T126	13503	0	0	0
T127	31276	0	0	0
T128	371149	0	0	0
T129	43525	0	0	0
T130	158609	0	0	0
T131	16104	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343219890	6398	0	0
T34	55640	451	0	0
T47	131331	0	0	0
T48	0	398	0	0
T49	0	240	0	0
T51	0	250	0	0
T53	0	190	0	0
T119	0	214	0	0
T120	0	443	0	0
T121	0	302	0	0
T122	0	892	0	0
T123	0	503	0	0
T124	10809	0	0	0
T125	223866	0	0	0
T126	13503	0	0	0
T127	31276	0	0	0
T128	371149	0	0	0
T129	43525	0	0	0
T130	158609	0	0	0
T131	16104	0	0	0