Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.78	100.00	81.82	100.00		100.00	47.06	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	316000054	8575	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	316000054	8575	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	316000054	8575	0	0
T1	310244	11	0	0
T2	328308	62	0	0
T3	33924	0	0	0
T4	590091	4	0	0
T5	383904	35	0	0
T6	0	15	0	0
T8	801	0	0	0
T9	115305	2	0	0
T10	540070	11	0	0
T11	389233	39	0	0
T12	143682	13	0	0
T22	0	16	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	316000054	8575	0	0
T1	310244	11	0	0
T2	328308	62	0	0
T3	33924	0	0	0
T4	590091	4	0	0
T5	383904	35	0	0
T6	0	15	0	0
T8	801	0	0	0
T9	115305	2	0	0
T10	540070	11	0	0
T11	389233	39	0	0
T12	143682	13	0	0
T22	0	16	0	0