Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.78	100.00	81.82	100.00		100.00	47.06	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	317267025	168598	0	0
ctrl_regwen_rd_A	317267025	3975	0	0
exec_rd_A	317267025	3827	0	0
exec_regwen_rd_A	317267025	4090	0	0
readback_rd_A	317267025	2397	0	0
readback_regwen_rd_A	317267025	1827	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317267025	168598	0	0
T6	20493	0	0	0
T12	143682	3741	0	0
T15	107161	0	0	0
T16	161572	7415	0	0
T20	13218	0	0	0
T21	0	3822	0	0
T22	271125	0	0	0
T29	0	8321	0	0
T32	0	2495	0	0
T38	0	1695	0	0
T42	7021	0	0	0
T55	0	1969	0	0
T56	0	1159	0	0
T57	0	1872	0	0
T58	0	1303	0	0
T59	14189	0	0	0
T60	15209	0	0	0
T61	266774	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317267025	3975	0	0
T30	0	133	0	0
T38	41828	0	0	0
T56	23256	96	0	0
T103	0	226	0	0
T104	0	114	0	0
T105	0	296	0	0
T106	0	49	0	0
T107	0	183	0	0
T108	0	238	0	0
T109	0	284	0	0
T110	0	493	0	0
T111	20348	0	0	0
T112	287857	0	0	0
T113	113085	0	0	0
T114	275067	0	0	0
T115	10988	0	0	0
T116	66356	0	0	0
T117	58453	0	0	0
T118	8705	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317267025	3827	0	0
T30	0	182	0	0
T38	41828	0	0	0
T56	23256	70	0	0
T103	0	160	0	0
T104	0	120	0	0
T105	0	284	0	0
T106	0	35	0	0
T107	0	208	0	0
T108	0	300	0	0
T109	0	188	0	0
T110	0	359	0	0
T111	20348	0	0	0
T112	287857	0	0	0
T113	113085	0	0	0
T114	275067	0	0	0
T115	10988	0	0	0
T116	66356	0	0	0
T117	58453	0	0	0
T118	8705	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317267025	4090	0	0
T30	0	153	0	0
T38	41828	0	0	0
T56	23256	148	0	0
T103	0	224	0	0
T104	0	142	0	0
T105	0	428	0	0
T106	0	59	0	0
T107	0	271	0	0
T108	0	280	0	0
T109	0	190	0	0
T110	0	374	0	0
T111	20348	0	0	0
T112	287857	0	0	0
T113	113085	0	0	0
T114	275067	0	0	0
T115	10988	0	0	0
T116	66356	0	0	0
T117	58453	0	0	0
T118	8705	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317267025	2397	0	0
T30	0	149	0	0
T38	41828	0	0	0
T56	23256	61	0	0
T103	0	281	0	0
T104	0	97	0	0
T105	0	395	0	0
T106	0	36	0	0
T107	0	200	0	0
T108	0	352	0	0
T109	0	132	0	0
T110	0	476	0	0
T111	20348	0	0	0
T112	287857	0	0	0
T113	113085	0	0	0
T114	275067	0	0	0
T115	10988	0	0	0
T116	66356	0	0	0
T117	58453	0	0	0
T118	8705	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317267025	1827	0	0
T30	0	85	0	0
T38	41828	0	0	0
T56	23256	95	0	0
T103	0	239	0	0
T104	0	120	0	0
T105	0	217	0	0
T106	0	20	0	0
T107	0	168	0	0
T108	0	195	0	0
T109	0	172	0	0
T110	0	343	0	0
T111	20348	0	0	0
T112	287857	0	0	0
T113	113085	0	0	0
T114	275067	0	0	0
T115	10988	0	0	0
T116	66356	0	0	0
T117	58453	0	0	0
T118	8705	0	0	0