Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14639137	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59139738

1

T1

51134

T2

124279

T3

237

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36778512	1			T1	139910		T2	68430		T3	648
values[0x0]	17040798	1			T1	47282		T2	32776		T3	206
values[0x1]	19959565	1			T1	92898		T2	35458		T3	406

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7297341	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66481534

1

T1

165929

T2

130547

T3

771

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	375595	1			T1	1113		T3	6		T4	966
valid_sources[0x01]	261806	1			T1	1069		T3	2		T7	10
valid_sources[0x02]	278860	1			T1	1132		T3	3		T7	1
valid_sources[0x03]	260029	1			T1	1204		T3	2		T7	1
valid_sources[0x04]	286148	1			T1	1065		T3	7		T7	6
valid_sources[0x05]	291795	1			T1	1076		T3	3		T7	1
valid_sources[0x06]	255963	1			T1	1133		T3	3		T4	954
valid_sources[0x07]	282941	1			T1	1107		T3	2		T7	1
valid_sources[0x08]	264578	1			T1	1081		T3	5		T7	10
valid_sources[0x09]	278662	1			T1	1107		T3	7		T4	932
valid_sources[0x0a]	361517	1			T1	1079		T3	3		T7	3
valid_sources[0x0b]	286276	1			T1	1121		T3	2		T4	1007
valid_sources[0x0c]	262446	1			T1	1117		T3	8		T7	5
valid_sources[0x0d]	294282	1			T1	1048		T3	6		T7	9
valid_sources[0x0e]	296689	1			T1	1117		T3	1		T7	1
valid_sources[0x0f]	265937	1			T1	1098		T3	5		T7	4
valid_sources[0x10]	259718	1			T1	1124		T3	7		T7	6
valid_sources[0x11]	300799	1			T1	1103		T3	3		T7	3
valid_sources[0x12]	274306	1			T1	1066		T7	3		T4	1005
valid_sources[0x13]	273661	1			T1	1094		T3	5		T7	6
valid_sources[0x14]	297794	1			T1	1125		T3	2		T7	3
valid_sources[0x15]	261301	1			T1	1065		T3	12		T7	1
valid_sources[0x16]	347247	1			T1	1058		T3	3		T7	2
valid_sources[0x17]	276225	1			T1	1089		T3	2		T7	4
valid_sources[0x18]	312456	1			T1	1042		T3	3		T7	3
valid_sources[0x19]	301656	1			T1	1066		T3	15		T7	2
valid_sources[0x1a]	261203	1			T1	1139		T3	8		T7	6
valid_sources[0x1b]	292336	1			T1	1116		T3	8		T4	980
valid_sources[0x1c]	281387	1			T1	1113		T3	1		T7	2
valid_sources[0x1d]	269925	1			T1	1056		T7	4		T4	1018
valid_sources[0x1e]	275770	1			T1	1049		T3	4		T7	14
valid_sources[0x1f]	279026	1			T1	1055		T3	3		T7	2
valid_sources[0x20]	279971	1			T1	1081		T3	6		T4	1019
valid_sources[0x21]	325781	1			T1	1045		T3	7		T7	3
valid_sources[0x22]	265407	1			T1	1061		T3	6		T7	11
valid_sources[0x23]	277194	1			T1	1113		T7	2		T4	1009
valid_sources[0x24]	268150	1			T1	1126		T3	3		T7	1
valid_sources[0x25]	309281	1			T1	1156		T3	6		T4	984
valid_sources[0x26]	283220	1			T1	1194		T3	1		T4	1019
valid_sources[0x27]	360704	1			T1	1126		T3	7		T7	11
valid_sources[0x28]	255816	1			T1	1086		T3	2		T7	6
valid_sources[0x29]	262754	1			T1	1086		T3	8		T7	9
valid_sources[0x2a]	286487	1			T1	1149		T7	8		T4	995
valid_sources[0x2b]	335292	1			T1	1095		T3	6		T7	5
valid_sources[0x2c]	267402	1			T1	1086		T3	12		T7	6
valid_sources[0x2d]	285729	1			T1	1111		T2	3634		T7	7
valid_sources[0x2e]	290344	1			T1	1113		T3	4		T7	7
valid_sources[0x2f]	263865	1			T1	1139		T3	4		T7	3
valid_sources[0x30]	262305	1			T1	1124		T3	6		T7	5
valid_sources[0x31]	304523	1			T1	1089		T3	3		T7	1
valid_sources[0x32]	262055	1			T1	1123		T3	6		T7	3
valid_sources[0x33]	285269	1			T1	1059		T3	4		T7	7
valid_sources[0x34]	282537	1			T1	1079		T3	7		T7	3
valid_sources[0x35]	268655	1			T1	1121		T3	2		T7	6
valid_sources[0x36]	280158	1			T1	1086		T3	9		T7	7
valid_sources[0x37]	255974	1			T1	1107		T3	8		T7	3
valid_sources[0x38]	270968	1			T1	1049		T3	5		T7	13
valid_sources[0x39]	290690	1			T1	1046		T3	16		T7	2
valid_sources[0x3a]	301005	1			T1	1082		T3	3		T7	7
valid_sources[0x3b]	395601	1			T1	1125		T3	2		T7	2
valid_sources[0x3c]	333730	1			T1	1071		T3	4		T7	2
valid_sources[0x3d]	263302	1			T1	1065		T7	3		T4	1006
valid_sources[0x3e]	254046	1			T1	1077		T3	1		T7	3
valid_sources[0x3f]	281319	1			T1	1051		T3	4		T7	14
valid_sources[0x40]	343106	1			T1	1034		T3	3		T7	23
valid_sources[0x41]	258654	1			T1	1124		T3	13		T7	18
valid_sources[0x42]	272281	1			T1	1086		T3	7		T7	2
valid_sources[0x43]	267525	1			T1	1082		T3	10		T7	4
valid_sources[0x44]	302492	1			T1	1100		T3	1		T7	4
valid_sources[0x45]	270723	1			T1	1103		T3	11		T7	9
valid_sources[0x46]	268564	1			T1	1139		T3	3		T7	2
valid_sources[0x47]	286900	1			T1	1088		T3	3		T4	1072
valid_sources[0x48]	283683	1			T1	1169		T3	4		T7	7
valid_sources[0x49]	296655	1			T1	1142		T3	5		T7	3
valid_sources[0x4a]	270448	1			T1	1152		T3	3		T7	9
valid_sources[0x4b]	301542	1			T1	1117		T7	17		T4	1035
valid_sources[0x4c]	323693	1			T1	1042		T3	4		T7	3
valid_sources[0x4d]	281328	1			T1	1086		T2	2828		T3	8
valid_sources[0x4e]	261762	1			T1	1081		T3	5		T7	6
valid_sources[0x4f]	277345	1			T1	1083		T3	1		T7	3
valid_sources[0x50]	257367	1			T1	1105		T3	4		T7	6
valid_sources[0x51]	271322	1			T1	1117		T3	4		T7	7
valid_sources[0x52]	267217	1			T1	1146		T3	4		T7	3
valid_sources[0x53]	278033	1			T1	1083		T3	4		T7	3
valid_sources[0x54]	257138	1			T1	1123		T3	3		T7	8
valid_sources[0x55]	257829	1			T1	1054		T3	2		T7	4
valid_sources[0x56]	264802	1			T1	1090		T3	5		T7	3
valid_sources[0x57]	296581	1			T1	1048		T2	23334		T3	2
valid_sources[0x58]	271666	1			T1	1083		T3	19		T7	17
valid_sources[0x59]	289631	1			T1	1188		T3	3		T4	984
valid_sources[0x5a]	280348	1			T1	1086		T3	4		T7	3
valid_sources[0x5b]	270937	1			T1	1049		T3	9		T4	950
valid_sources[0x5c]	310806	1			T1	1143		T3	8		T7	3
valid_sources[0x5d]	303799	1			T1	1100		T7	7		T4	987
valid_sources[0x5e]	299441	1			T1	1119		T3	9		T7	1
valid_sources[0x5f]	288142	1			T1	1069		T3	10		T7	4
valid_sources[0x60]	263051	1			T1	1088		T3	3		T7	1
valid_sources[0x61]	298453	1			T1	1038		T3	4		T7	1
valid_sources[0x62]	262981	1			T1	1099		T3	6		T7	14
valid_sources[0x63]	255522	1			T1	1051		T3	1		T4	955
valid_sources[0x64]	344722	1			T1	1040		T3	13		T7	2
valid_sources[0x65]	261278	1			T1	1081		T3	9		T7	4
valid_sources[0x66]	272650	1			T1	1079		T3	2		T7	2
valid_sources[0x67]	258270	1			T1	1103		T3	5		T7	6
valid_sources[0x68]	306685	1			T1	1129		T2	4708		T3	5
valid_sources[0x69]	308083	1			T1	1091		T3	8		T7	2
valid_sources[0x6a]	280996	1			T1	1123		T3	2		T4	942
valid_sources[0x6b]	290855	1			T1	1086		T3	5		T7	15
valid_sources[0x6c]	380375	1			T1	1095		T3	8		T7	1
valid_sources[0x6d]	309947	1			T1	1131		T3	5		T4	964
valid_sources[0x6e]	265948	1			T1	1051		T3	2		T7	8
valid_sources[0x6f]	274248	1			T1	1087		T3	7		T7	9
valid_sources[0x70]	315045	1			T1	1030		T3	3		T7	14
valid_sources[0x71]	265743	1			T1	1178		T3	5		T7	3
valid_sources[0x72]	262258	1			T1	1074		T3	6		T7	4
valid_sources[0x73]	265509	1			T1	1106		T2	12		T3	4
valid_sources[0x74]	255864	1			T1	1059		T3	8		T7	16
valid_sources[0x75]	260438	1			T1	1070		T3	9		T7	4
valid_sources[0x76]	294390	1			T1	1128		T3	1		T4	998
valid_sources[0x77]	314548	1			T1	1129		T3	7		T7	1
valid_sources[0x78]	280096	1			T1	1089		T3	6		T7	16
valid_sources[0x79]	270599	1			T1	1127		T3	5		T7	27
valid_sources[0x7a]	330807	1			T1	1124		T3	2		T7	5
valid_sources[0x7b]	291998	1			T1	1082		T2	25879		T3	4
valid_sources[0x7c]	266605	1			T1	1073		T2	3094		T3	3
valid_sources[0x7d]	282545	1			T1	1088		T3	6		T7	7
valid_sources[0x7e]	280372	1			T1	1101		T3	4		T7	4
valid_sources[0x7f]	277039	1			T1	1110		T2	3858		T7	3
valid_sources[0x80]	295059	1			T1	1024		T3	1		T7	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29461808

1

T1

25441

T2

62170

T3

125

values[0x0]

all_enables

biggest_size

14842916

1

T1

12884

T2

30960

T3

58

values[0x1]

all_enables

biggest_size

14835014

1

T1

12809

T2

31149

T3

54

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33979	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140996

1

T2

6

T3

1

T4

64

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49761	1			T4	90		T9	591		T11	5
values[0x0]	60355	1			T1	1		T2	5		T3	1
values[0x1]	64859	1			T1	2		T2	11		T7	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25565	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149410

1

T1

1

T2

7

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	609	1			T9	5		T67	2		T24	7
valid_sources[0x01]	665	1			T9	15		T42	2		T23	2
valid_sources[0x02]	560	1			T9	6		T24	4		T53	10
valid_sources[0x03]	631	1			T9	2		T42	2		T138	1
valid_sources[0x04]	916	1			T9	5		T42	3		T23	273
valid_sources[0x05]	580	1			T9	4		T39	1		T24	10
valid_sources[0x06]	801	1			T9	2		T44	2		T23	29
valid_sources[0x07]	565	1			T9	10		T24	8		T53	31
valid_sources[0x08]	701	1			T9	4		T43	3		T141	2
valid_sources[0x09]	815	1			T9	7		T67	11		T24	9
valid_sources[0x0a]	784	1			T9	8		T43	3		T23	63
valid_sources[0x0b]	718	1			T9	16		T41	1		T24	7
valid_sources[0x0c]	900	1			T9	14		T67	3		T24	9
valid_sources[0x0d]	692	1			T9	4		T98	1		T43	1
valid_sources[0x0e]	624	1			T9	4		T40	3		T71	1
valid_sources[0x0f]	586	1			T9	10		T39	1		T24	12
valid_sources[0x10]	734	1			T9	7		T39	1		T43	2
valid_sources[0x11]	667	1			T9	8		T41	2		T24	8
valid_sources[0x12]	713	1			T9	8		T138	1		T24	11
valid_sources[0x13]	597	1			T9	6		T42	3		T43	1
valid_sources[0x14]	700	1			T9	16		T138	2		T67	3
valid_sources[0x15]	1111	1			T9	3		T67	1		T24	2
valid_sources[0x16]	586	1			T9	14		T44	2		T23	3
valid_sources[0x17]	622	1			T9	12		T42	4		T41	1
valid_sources[0x18]	622	1			T9	5		T24	9		T53	28
valid_sources[0x19]	690	1			T9	4		T43	1		T24	10
valid_sources[0x1a]	598	1			T9	18		T67	2		T140	1
valid_sources[0x1b]	601	1			T9	9		T24	11		T53	10
valid_sources[0x1c]	675	1			T9	8		T20	73		T24	11
valid_sources[0x1d]	910	1			T9	3		T67	1		T41	1
valid_sources[0x1e]	660	1			T9	6		T56	1		T39	1
valid_sources[0x1f]	609	1			T9	16		T42	2		T43	2
valid_sources[0x20]	781	1			T9	8		T67	3		T41	1
valid_sources[0x21]	722	1			T9	2		T42	1		T24	5
valid_sources[0x22]	735	1			T9	8		T5	32		T138	1
valid_sources[0x23]	656	1			T9	3		T24	6		T53	35
valid_sources[0x24]	544	1			T9	8		T43	1		T23	3
valid_sources[0x25]	742	1			T2	1		T9	8		T24	9
valid_sources[0x26]	606	1			T9	3		T40	2		T24	2
valid_sources[0x27]	535	1			T9	11		T25	1		T42	2
valid_sources[0x28]	547	1			T9	5		T21	1		T24	4
valid_sources[0x29]	617	1			T9	5		T24	9		T53	18
valid_sources[0x2a]	659	1			T9	14		T39	1		T67	2
valid_sources[0x2b]	757	1			T9	10		T24	11		T53	5
valid_sources[0x2c]	556	1			T9	2		T67	1		T142	2
valid_sources[0x2d]	689	1			T3	1		T7	2		T9	9
valid_sources[0x2e]	602	1			T9	6		T67	1		T41	1
valid_sources[0x2f]	590	1			T9	15		T39	1		T71	2
valid_sources[0x30]	577	1			T8	1		T9	7		T22	2
valid_sources[0x31]	643	1			T9	8		T24	11		T53	27
valid_sources[0x32]	731	1			T9	8		T5	65		T24	7
valid_sources[0x33]	624	1			T9	21		T24	8		T53	26
valid_sources[0x34]	805	1			T9	7		T21	1		T24	6
valid_sources[0x35]	629	1			T9	8		T39	1		T24	14
valid_sources[0x36]	660	1			T9	6		T67	1		T24	8
valid_sources[0x37]	763	1			T9	12		T68	1		T41	1
valid_sources[0x38]	657	1			T9	6		T143	3		T41	1
valid_sources[0x39]	628	1			T9	7		T71	1		T24	8
valid_sources[0x3a]	537	1			T9	7		T23	3		T67	2
valid_sources[0x3b]	648	1			T9	5		T24	13		T53	30
valid_sources[0x3c]	691	1			T9	7		T39	1		T42	1
valid_sources[0x3d]	690	1			T9	6		T67	2		T24	15
valid_sources[0x3e]	869	1			T9	5		T40	6		T144	1
valid_sources[0x3f]	579	1			T9	8		T67	1		T24	13
valid_sources[0x40]	795	1			T2	2		T9	16		T40	1
valid_sources[0x41]	846	1			T9	5		T41	1		T139	1
valid_sources[0x42]	541	1			T9	7		T43	1		T24	7
valid_sources[0x43]	521	1			T9	5		T43	1		T24	10
valid_sources[0x44]	724	1			T9	4		T24	4		T53	17
valid_sources[0x45]	708	1			T9	9		T41	1		T71	1
valid_sources[0x46]	823	1			T9	13		T24	4		T53	29
valid_sources[0x47]	594	1			T9	11		T71	1		T24	6
valid_sources[0x48]	612	1			T9	5		T24	10		T53	26
valid_sources[0x49]	659	1			T9	3		T23	63		T71	1
valid_sources[0x4a]	805	1			T9	5		T24	15		T53	25
valid_sources[0x4b]	748	1			T9	2		T145	2		T41	1
valid_sources[0x4c]	592	1			T9	13		T11	12		T146	1
valid_sources[0x4d]	680	1			T9	8		T43	3		T147	1
valid_sources[0x4e]	812	1			T9	4		T56	1		T148	2
valid_sources[0x4f]	607	1			T9	9		T138	1		T43	1
valid_sources[0x50]	597	1			T9	2		T48	3		T67	2
valid_sources[0x51]	533	1			T9	24		T43	1		T67	2
valid_sources[0x52]	701	1			T9	9		T43	1		T41	1
valid_sources[0x53]	830	1			T4	191		T9	12		T138	2
valid_sources[0x54]	663	1			T9	5		T44	1		T40	3
valid_sources[0x55]	685	1			T23	147		T24	10		T53	2
valid_sources[0x56]	747	1			T9	7		T24	4		T53	21
valid_sources[0x57]	710	1			T9	6		T42	2		T147	1
valid_sources[0x58]	742	1			T9	10		T39	1		T138	1
valid_sources[0x59]	586	1			T9	2		T138	1		T67	1
valid_sources[0x5a]	609	1			T9	10		T23	4		T24	9
valid_sources[0x5b]	869	1			T9	6		T149	2		T24	13
valid_sources[0x5c]	636	1			T9	5		T57	1		T42	1
valid_sources[0x5d]	839	1			T9	9		T42	2		T41	1
valid_sources[0x5e]	940	1			T9	12		T24	8		T53	8
valid_sources[0x5f]	735	1			T9	7		T138	1		T67	1
valid_sources[0x60]	522	1			T9	7		T150	17		T41	1
valid_sources[0x61]	626	1			T9	4		T151	1		T24	5
valid_sources[0x62]	575	1			T9	5		T24	8		T53	17
valid_sources[0x63]	595	1			T9	13		T24	6		T53	11
valid_sources[0x64]	567	1			T9	6		T140	1		T24	6
valid_sources[0x65]	724	1			T1	3		T9	8		T43	3
valid_sources[0x66]	608	1			T9	5		T24	16		T53	24
valid_sources[0x67]	640	1			T9	1		T71	1		T24	10
valid_sources[0x68]	767	1			T9	5		T43	1		T23	139
valid_sources[0x69]	544	1			T9	7		T42	2		T40	1
valid_sources[0x6a]	669	1			T9	18		T42	1		T24	7
valid_sources[0x6b]	680	1			T40	2		T43	1		T24	6
valid_sources[0x6c]	893	1			T9	9		T14	2		T67	2
valid_sources[0x6d]	606	1			T9	14		T138	1		T24	11
valid_sources[0x6e]	772	1			T9	16		T24	8		T53	25
valid_sources[0x6f]	617	1			T9	12		T43	1		T24	10
valid_sources[0x70]	608	1			T9	16		T43	1		T21	1
valid_sources[0x71]	1075	1			T9	15		T43	4		T67	1
valid_sources[0x72]	560	1			T9	5		T39	1		T67	1
valid_sources[0x73]	616	1			T9	4		T56	1		T67	1
valid_sources[0x74]	534	1			T9	12		T42	1		T99	2
valid_sources[0x75]	606	1			T9	4		T23	3		T67	1
valid_sources[0x76]	565	1			T9	9		T152	1		T43	2
valid_sources[0x77]	556	1			T9	8		T21	1		T24	9
valid_sources[0x78]	602	1			T9	5		T39	1		T43	1
valid_sources[0x79]	843	1			T9	7		T23	152		T41	2
valid_sources[0x7a]	615	1			T9	8		T10	2		T56	1
valid_sources[0x7b]	663	1			T2	3		T9	14		T39	1
valid_sources[0x7c]	701	1			T40	1		T153	2		T24	6
valid_sources[0x7d]	654	1			T9	6		T42	8		T24	10
valid_sources[0x7e]	772	1			T9	7		T24	7		T53	20
valid_sources[0x7f]	786	1			T9	13		T40	5		T67	2
valid_sources[0x80]	1083	1			T9	8		T24	6		T53	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38130

1

T4

45

T9

542

T11

1

values[0x0]

all_enables

biggest_size

52468

1

T2

2

T3

1

T4

13

values[0x1]

all_enables

biggest_size

50398

1

T2

4

T4

6

T9

724