Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14343950

1

T1

228956

T2

12385

T3

1023

full_word

54216387

1

T1

51134

T2

124279

T3

237

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68560087	1			T1	280090		T2	136664		T3	1260
auto[TlIntgErrCmd]	74	1			T61	1		T62	1		T63	8
auto[TlIntgErrData]	85	1			T61	5		T62	3		T63	5
auto[TlIntgErrBoth]	91	1			T61	4		T62	6		T63	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31486422

1

T1

139910

T2

68430

T3

648

auto[1]

37073915

1

T1

140180

T2

68234

T3

612

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6871087	1			T1	114469		T2	6260		T3	523
auto[TlIntgErrNone]	partial	auto[1]	7472642	1			T1	114487		T2	6125		T3	500
auto[TlIntgErrNone]	full_word	auto[0]	24615218	1			T1	25441		T2	62170		T3	125
auto[TlIntgErrNone]	full_word	auto[1]	29601140	1			T1	25693		T2	62109		T3	112
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T62	1		T126	1		T122	1
auto[TlIntgErrCmd]	partial	auto[1]	34	1			T61	1		T63	8		T126	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T129	1		T120	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T122	1		T124	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T61	2		T62	1		T63	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T61	2		T62	2		T63	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T63	1		T120	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T61	1		T122	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T61	1		T62	1		T63	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T61	2		T62	5		T63	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T61	1		T127	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T127	1		T120	2		T124	1