Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	713713	1			T4	9462		T10	589		T22	671
auto[1]	10931328	1			T1	117597		T2	30528		T3	634
auto[2]	595945	1			T4	8585		T10	346		T22	690
auto[3]	10826518	1			T1	117704		T2	30464		T3	590

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14557018	1			T1	7845		T2	50821		T3	37
auto[1]	2230020	1			T1	35216		T2	4866		T3	194
auto[2]	2251236	1			T1	35302		T2	4849		T3	184
auto[3]	4029230	1			T1	156938		T2	456		T3	809

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8259829

1

T2

60930

T3

1223

T4

21598

auto[1]

14807675

1

T1

235301

T2

62

T3

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	255049	1			T4	7740		T10	479		T22	23
auto[0]	auto[0]	auto[1]	26824	1			T4	840		T10	57		T22	112
auto[0]	auto[0]	auto[2]	26917	1			T4	810		T10	46		T22	100
auto[0]	auto[0]	auto[3]	9007	1			T4	64		T10	7		T22	433
auto[0]	auto[1]	auto[0]	3150340	1			T2	25425		T3	19		T4	1297
auto[0]	auto[1]	auto[1]	323542	1			T2	2306		T3	102		T4	774
auto[0]	auto[1]	auto[2]	317937	1			T2	2541		T3	91		T4	125
auto[0]	auto[1]	auto[3]	65375	1			T2	225		T3	421		T4	74
auto[0]	auto[2]	auto[0]	214481	1			T4	7257		T10	272		T22	17
auto[0]	auto[2]	auto[1]	22505	1			T4	751		T10	29		T22	58
auto[0]	auto[2]	auto[2]	25069	1			T4	526		T10	41		T22	115
auto[0]	auto[2]	auto[3]	7740	1			T4	46		T10	3		T22	499
auto[0]	auto[3]	auto[0]	3112406	1			T2	25350		T3	18		T4	635
auto[0]	auto[3]	auto[1]	312639	1			T2	2551		T3	92		T4	67
auto[0]	auto[3]	auto[2]	323353	1			T2	2303		T3	92		T4	524
auto[0]	auto[3]	auto[3]	66645	1			T2	229		T3	388		T4	68
auto[1]	auto[0]	auto[0]	13138	1			T4	5		T42	19		T138	11
auto[1]	auto[0]	auto[1]	58817	1			T4	1		T42	2		T138	2
auto[1]	auto[0]	auto[2]	59089	1			T4	2		T42	1		T138	1
auto[1]	auto[0]	auto[3]	264872	1			T22	3		T99	13197		T139	2
auto[1]	auto[1]	auto[0]	3902504	1			T1	3861		T2	23		T9	1
auto[1]	auto[1]	auto[1]	735851	1			T1	17539		T2	4		T4	1
auto[1]	auto[1]	auto[2]	722789	1			T1	17744		T2	3		T3	1
auto[1]	auto[1]	auto[3]	1712990	1			T1	78453		T2	1		T12	5
auto[1]	auto[2]	auto[0]	9806	1			T4	3		T10	1		T42	16
auto[1]	auto[2]	auto[1]	42644	1			T4	2		T138	1		T99	1728
auto[1]	auto[2]	auto[2]	49712	1			T42	4		T99	3183		T140	1
auto[1]	auto[2]	auto[3]	223988	1			T22	1		T99	14238		T136	8120
auto[1]	auto[3]	auto[0]	3899294	1			T1	3984		T2	23		T11	1
auto[1]	auto[3]	auto[1]	707198	1			T1	17677		T2	5		T11	1
auto[1]	auto[3]	auto[2]	726370	1			T1	17558		T2	2		T4	1
auto[1]	auto[3]	auto[3]	1678613	1			T1	78485		T2	1		T12	1