Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	306260095	215391	0	0
ctrl_regwen_rd_A	306260095	1658	0	0
exec_rd_A	306260095	1542	0	0
exec_regwen_rd_A	306260095	1548	0	0
readback_rd_A	306260095	685	0	0
readback_regwen_rd_A	306260095	399	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306260095	215391	0	0
T9	79223	4180	0	0
T10	58950	0	0	0
T11	108304	0	0	0
T12	13160	0	0	0
T19	364874	0	0	0
T22	65016	0	0	0
T23	0	3141	0	0
T24	0	2609	0	0
T25	1901	0	0	0
T44	44373	0	0	0
T45	0	7698	0	0
T46	0	1254	0	0
T53	0	8447	0	0
T55	0	6401	0	0
T56	7269	0	0	0
T57	22435	0	0	0
T58	0	1962	0	0
T69	0	2215	0	0
T70	0	1743	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306260095	1658	0	0
T24	76988	126	0	0
T51	9869	0	0	0
T52	17256	0	0	0
T53	166757	0	0	0
T54	22836	0	0	0
T61	0	37	0	0
T62	0	26	0	0
T65	0	8	0	0
T66	0	6	0	0
T74	0	2	0	0
T77	0	51	0	0
T86	107151	0	0	0
T95	0	31	0	0
T107	0	159	0	0
T108	0	229	0	0
T109	25956	0	0	0
T110	21181	0	0	0
T111	14349	0	0	0
T112	803025	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306260095	1542	0	0
T24	76988	109	0	0
T51	9869	0	0	0
T52	17256	0	0	0
T53	166757	0	0	0
T54	22836	0	0	0
T61	0	28	0	0
T62	0	62	0	0
T65	0	1	0	0
T66	0	5	0	0
T74	0	1	0	0
T77	0	36	0	0
T86	107151	0	0	0
T95	0	16	0	0
T107	0	182	0	0
T108	0	179	0	0
T109	25956	0	0	0
T110	21181	0	0	0
T111	14349	0	0	0
T112	803025	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306260095	1548	0	0
T24	76988	93	0	0
T51	9869	0	0	0
T52	17256	0	0	0
T53	166757	0	0	0
T54	22836	0	0	0
T61	0	26	0	0
T62	0	35	0	0
T65	0	11	0	0
T66	0	8	0	0
T74	0	8	0	0
T77	0	42	0	0
T86	107151	0	0	0
T95	0	17	0	0
T107	0	138	0	0
T108	0	173	0	0
T109	25956	0	0	0
T110	21181	0	0	0
T111	14349	0	0	0
T112	803025	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306260095	685	0	0
T24	76988	112	0	0
T51	9869	0	0	0
T52	17256	0	0	0
T53	166757	0	0	0
T54	22836	0	0	0
T86	107151	0	0	0
T107	0	147	0	0
T108	0	278	0	0
T109	25956	0	0	0
T110	21181	0	0	0
T111	14349	0	0	0
T112	803025	0	0	0
T113	0	23	0	0
T114	0	5	0	0
T115	0	25	0	0
T116	0	14	0	0
T117	0	9	0	0
T118	0	31	0	0
T119	0	41	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306260095	399	0	0
T24	76988	102	0	0
T51	9869	0	0	0
T52	17256	0	0	0
T53	166757	0	0	0
T54	22836	0	0	0
T86	107151	0	0	0
T107	0	154	0	0
T108	0	106	0	0
T109	25956	0	0	0
T110	21181	0	0	0
T111	14349	0	0	0
T112	803025	0	0	0
T114	0	3	0	0
T116	0	17	0	0
T118	0	7	0	0
T119	0	7	0	0
T120	0	3	0	0