| T798 |
/workspace/coverage/default/32.sram_ctrl_partial_access.2075953160 |
|
|
Jun 23 06:27:10 PM PDT 24 |
Jun 23 06:27:26 PM PDT 24 |
1660435754 ps |
| T799 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3009192929 |
|
|
Jun 23 06:26:50 PM PDT 24 |
Jun 23 06:26:51 PM PDT 24 |
27222626 ps |
| T800 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.442819580 |
|
|
Jun 23 06:27:31 PM PDT 24 |
Jun 23 06:56:42 PM PDT 24 |
43185171649 ps |
| T801 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.671644756 |
|
|
Jun 23 06:24:46 PM PDT 24 |
Jun 23 06:24:47 PM PDT 24 |
28355412 ps |
| T802 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3744764227 |
|
|
Jun 23 06:27:01 PM PDT 24 |
Jun 23 06:27:02 PM PDT 24 |
144528821 ps |
| T803 |
/workspace/coverage/default/10.sram_ctrl_regwen.2450252444 |
|
|
Jun 23 06:25:12 PM PDT 24 |
Jun 23 06:36:38 PM PDT 24 |
28792806668 ps |
| T804 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2206339901 |
|
|
Jun 23 06:25:09 PM PDT 24 |
Jun 23 06:25:10 PM PDT 24 |
49213785 ps |
| T805 |
/workspace/coverage/default/4.sram_ctrl_bijection.3321212722 |
|
|
Jun 23 06:24:45 PM PDT 24 |
Jun 23 06:25:12 PM PDT 24 |
8971502935 ps |
| T806 |
/workspace/coverage/default/33.sram_ctrl_bijection.622188734 |
|
|
Jun 23 06:27:15 PM PDT 24 |
Jun 23 06:28:03 PM PDT 24 |
2098304656 ps |
| T807 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3253417406 |
|
|
Jun 23 06:28:50 PM PDT 24 |
Jun 23 06:28:52 PM PDT 24 |
20133410 ps |
| T808 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.1953710498 |
|
|
Jun 23 06:26:10 PM PDT 24 |
Jun 23 06:26:20 PM PDT 24 |
1576250472 ps |
| T809 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3650416780 |
|
|
Jun 23 06:28:45 PM PDT 24 |
Jun 23 06:34:09 PM PDT 24 |
3580139085 ps |
| T28 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1112676132 |
|
|
Jun 23 06:24:45 PM PDT 24 |
Jun 23 06:24:47 PM PDT 24 |
389327065 ps |
| T810 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3635406748 |
|
|
Jun 23 06:25:03 PM PDT 24 |
Jun 23 06:25:10 PM PDT 24 |
1279423910 ps |
| T811 |
/workspace/coverage/default/2.sram_ctrl_stress_all.2454411814 |
|
|
Jun 23 06:24:37 PM PDT 24 |
Jun 23 06:59:40 PM PDT 24 |
247617078244 ps |
| T812 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3676332473 |
|
|
Jun 23 06:28:57 PM PDT 24 |
Jun 23 06:29:38 PM PDT 24 |
1036436062 ps |
| T813 |
/workspace/coverage/default/31.sram_ctrl_stress_all.4121081181 |
|
|
Jun 23 06:27:09 PM PDT 24 |
Jun 23 07:40:59 PM PDT 24 |
15724448687 ps |
| T814 |
/workspace/coverage/default/30.sram_ctrl_partial_access.1562023276 |
|
|
Jun 23 06:27:00 PM PDT 24 |
Jun 23 06:27:15 PM PDT 24 |
2844169147 ps |
| T815 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.4198493499 |
|
|
Jun 23 06:25:57 PM PDT 24 |
Jun 23 06:28:14 PM PDT 24 |
141734065 ps |
| T816 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2430580957 |
|
|
Jun 23 06:27:20 PM PDT 24 |
Jun 23 06:27:21 PM PDT 24 |
27487670 ps |
| T817 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.595720938 |
|
|
Jun 23 06:27:37 PM PDT 24 |
Jun 23 06:27:38 PM PDT 24 |
42585714 ps |
| T29 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2532895947 |
|
|
Jun 23 06:24:35 PM PDT 24 |
Jun 23 06:24:37 PM PDT 24 |
361269286 ps |
| T818 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.390387050 |
|
|
Jun 23 06:24:27 PM PDT 24 |
Jun 23 06:24:37 PM PDT 24 |
506323659 ps |
| T819 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1589219255 |
|
|
Jun 23 06:24:41 PM PDT 24 |
Jun 23 06:27:46 PM PDT 24 |
2168664209 ps |
| T820 |
/workspace/coverage/default/22.sram_ctrl_stress_all.4130061263 |
|
|
Jun 23 06:26:22 PM PDT 24 |
Jun 23 06:34:41 PM PDT 24 |
13802745573 ps |
| T821 |
/workspace/coverage/default/29.sram_ctrl_smoke.3027651291 |
|
|
Jun 23 06:26:50 PM PDT 24 |
Jun 23 06:27:02 PM PDT 24 |
3138124453 ps |
| T822 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2361905314 |
|
|
Jun 23 06:25:34 PM PDT 24 |
Jun 23 06:25:35 PM PDT 24 |
80823247 ps |
| T823 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3448059781 |
|
|
Jun 23 06:28:44 PM PDT 24 |
Jun 23 06:28:50 PM PDT 24 |
1455076600 ps |
| T824 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.4061309590 |
|
|
Jun 23 06:26:32 PM PDT 24 |
Jun 23 06:26:38 PM PDT 24 |
233952941 ps |
| T825 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2264480957 |
|
|
Jun 23 06:24:43 PM PDT 24 |
Jun 23 06:26:13 PM PDT 24 |
542222948 ps |
| T826 |
/workspace/coverage/default/21.sram_ctrl_regwen.3678549202 |
|
|
Jun 23 06:26:15 PM PDT 24 |
Jun 23 06:46:07 PM PDT 24 |
76515761086 ps |
| T827 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1837458152 |
|
|
Jun 23 06:26:41 PM PDT 24 |
Jun 23 06:32:03 PM PDT 24 |
443297225 ps |
| T828 |
/workspace/coverage/default/26.sram_ctrl_bijection.1835101312 |
|
|
Jun 23 06:26:35 PM PDT 24 |
Jun 23 06:27:45 PM PDT 24 |
2851247617 ps |
| T829 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2225560461 |
|
|
Jun 23 06:25:21 PM PDT 24 |
Jun 23 06:31:43 PM PDT 24 |
14271850738 ps |
| T830 |
/workspace/coverage/default/11.sram_ctrl_smoke.2404881587 |
|
|
Jun 23 06:25:14 PM PDT 24 |
Jun 23 06:25:49 PM PDT 24 |
666544553 ps |
| T831 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.281145163 |
|
|
Jun 23 06:26:49 PM PDT 24 |
Jun 23 06:30:32 PM PDT 24 |
12011584155 ps |
| T832 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.693262081 |
|
|
Jun 23 06:26:24 PM PDT 24 |
Jun 23 06:26:29 PM PDT 24 |
64993926 ps |
| T833 |
/workspace/coverage/default/16.sram_ctrl_regwen.3404793685 |
|
|
Jun 23 06:25:41 PM PDT 24 |
Jun 23 06:27:10 PM PDT 24 |
809980145 ps |
| T834 |
/workspace/coverage/default/9.sram_ctrl_bijection.2548755389 |
|
|
Jun 23 06:25:04 PM PDT 24 |
Jun 23 06:26:14 PM PDT 24 |
12130192220 ps |
| T835 |
/workspace/coverage/default/26.sram_ctrl_alert_test.759757739 |
|
|
Jun 23 06:26:42 PM PDT 24 |
Jun 23 06:26:43 PM PDT 24 |
38677867 ps |
| T836 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1566300427 |
|
|
Jun 23 06:25:23 PM PDT 24 |
Jun 23 06:25:37 PM PDT 24 |
514179981 ps |
| T837 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1576624027 |
|
|
Jun 23 06:25:00 PM PDT 24 |
Jun 23 06:25:54 PM PDT 24 |
440696121 ps |
| T838 |
/workspace/coverage/default/20.sram_ctrl_bijection.199556147 |
|
|
Jun 23 06:26:02 PM PDT 24 |
Jun 23 06:26:41 PM PDT 24 |
2392769815 ps |
| T839 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2902852828 |
|
|
Jun 23 06:24:49 PM PDT 24 |
Jun 23 06:27:41 PM PDT 24 |
1766140880 ps |
| T840 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3088524504 |
|
|
Jun 23 06:26:41 PM PDT 24 |
Jun 23 06:26:54 PM PDT 24 |
2728815910 ps |
| T841 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2558804029 |
|
|
Jun 23 06:27:22 PM PDT 24 |
Jun 23 06:27:23 PM PDT 24 |
15640181 ps |
| T842 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1266466500 |
|
|
Jun 23 06:24:48 PM PDT 24 |
Jun 23 06:24:54 PM PDT 24 |
1687948664 ps |
| T843 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2933460329 |
|
|
Jun 23 06:28:25 PM PDT 24 |
Jun 23 06:28:26 PM PDT 24 |
84379640 ps |
| T844 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.4223399209 |
|
|
Jun 23 06:26:56 PM PDT 24 |
Jun 23 06:28:35 PM PDT 24 |
136724385 ps |
| T845 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.3927958262 |
|
|
Jun 23 06:25:17 PM PDT 24 |
Jun 23 06:27:27 PM PDT 24 |
555617025 ps |
| T846 |
/workspace/coverage/default/10.sram_ctrl_alert_test.3928118321 |
|
|
Jun 23 06:25:16 PM PDT 24 |
Jun 23 06:25:17 PM PDT 24 |
42233556 ps |
| T847 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3692399605 |
|
|
Jun 23 06:28:30 PM PDT 24 |
Jun 23 06:38:01 PM PDT 24 |
1261906808 ps |
| T848 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3208779690 |
|
|
Jun 23 06:25:23 PM PDT 24 |
Jun 23 06:27:51 PM PDT 24 |
546206161 ps |
| T849 |
/workspace/coverage/default/19.sram_ctrl_bijection.2269098872 |
|
|
Jun 23 06:25:59 PM PDT 24 |
Jun 23 06:26:57 PM PDT 24 |
3698171787 ps |
| T850 |
/workspace/coverage/default/19.sram_ctrl_executable.202964262 |
|
|
Jun 23 06:25:58 PM PDT 24 |
Jun 23 06:43:56 PM PDT 24 |
21703031511 ps |
| T851 |
/workspace/coverage/default/21.sram_ctrl_executable.2116870882 |
|
|
Jun 23 06:26:15 PM PDT 24 |
Jun 23 06:40:35 PM PDT 24 |
85416196716 ps |
| T852 |
/workspace/coverage/default/42.sram_ctrl_bijection.1408110251 |
|
|
Jun 23 06:28:06 PM PDT 24 |
Jun 23 06:28:32 PM PDT 24 |
802680987 ps |
| T853 |
/workspace/coverage/default/47.sram_ctrl_smoke.2138432826 |
|
|
Jun 23 06:28:43 PM PDT 24 |
Jun 23 06:28:45 PM PDT 24 |
230151057 ps |
| T854 |
/workspace/coverage/default/33.sram_ctrl_executable.681914206 |
|
|
Jun 23 06:27:19 PM PDT 24 |
Jun 23 06:43:02 PM PDT 24 |
2572351139 ps |
| T855 |
/workspace/coverage/default/36.sram_ctrl_bijection.2883210900 |
|
|
Jun 23 06:27:33 PM PDT 24 |
Jun 23 06:28:14 PM PDT 24 |
2494868923 ps |
| T856 |
/workspace/coverage/default/17.sram_ctrl_partial_access.15348925 |
|
|
Jun 23 06:25:47 PM PDT 24 |
Jun 23 06:25:50 PM PDT 24 |
238552862 ps |
| T857 |
/workspace/coverage/default/22.sram_ctrl_smoke.3044891845 |
|
|
Jun 23 06:26:14 PM PDT 24 |
Jun 23 06:26:18 PM PDT 24 |
243110778 ps |
| T858 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.3885846301 |
|
|
Jun 23 06:28:01 PM PDT 24 |
Jun 23 06:29:01 PM PDT 24 |
133568731 ps |
| T859 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.3931950743 |
|
|
Jun 23 06:25:44 PM PDT 24 |
Jun 23 06:25:56 PM PDT 24 |
685489165 ps |
| T860 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3320692822 |
|
|
Jun 23 06:27:52 PM PDT 24 |
Jun 23 06:28:02 PM PDT 24 |
361986350 ps |
| T861 |
/workspace/coverage/default/48.sram_ctrl_regwen.307760069 |
|
|
Jun 23 06:28:52 PM PDT 24 |
Jun 23 06:37:15 PM PDT 24 |
50186203682 ps |
| T862 |
/workspace/coverage/default/17.sram_ctrl_smoke.3568858972 |
|
|
Jun 23 06:25:42 PM PDT 24 |
Jun 23 06:25:46 PM PDT 24 |
249458780 ps |
| T863 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1127179696 |
|
|
Jun 23 06:27:19 PM PDT 24 |
Jun 23 06:27:26 PM PDT 24 |
2289410563 ps |
| T864 |
/workspace/coverage/default/31.sram_ctrl_alert_test.350845137 |
|
|
Jun 23 06:27:08 PM PDT 24 |
Jun 23 06:27:10 PM PDT 24 |
41959287 ps |
| T865 |
/workspace/coverage/default/33.sram_ctrl_partial_access.3462660549 |
|
|
Jun 23 06:27:22 PM PDT 24 |
Jun 23 06:27:29 PM PDT 24 |
74073840 ps |
| T866 |
/workspace/coverage/default/30.sram_ctrl_smoke.3247550602 |
|
|
Jun 23 06:26:57 PM PDT 24 |
Jun 23 06:27:04 PM PDT 24 |
152303629 ps |
| T867 |
/workspace/coverage/default/36.sram_ctrl_alert_test.2276725018 |
|
|
Jun 23 06:27:43 PM PDT 24 |
Jun 23 06:27:45 PM PDT 24 |
13511030 ps |
| T868 |
/workspace/coverage/default/30.sram_ctrl_bijection.3218041399 |
|
|
Jun 23 06:26:59 PM PDT 24 |
Jun 23 06:28:13 PM PDT 24 |
4452631528 ps |
| T869 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2880994314 |
|
|
Jun 23 06:26:11 PM PDT 24 |
Jun 23 06:26:19 PM PDT 24 |
60413751 ps |
| T870 |
/workspace/coverage/default/29.sram_ctrl_bijection.444808469 |
|
|
Jun 23 06:26:50 PM PDT 24 |
Jun 23 06:27:18 PM PDT 24 |
1369415053 ps |
| T871 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.822293126 |
|
|
Jun 23 06:25:05 PM PDT 24 |
Jun 23 06:25:06 PM PDT 24 |
134162046 ps |
| T872 |
/workspace/coverage/default/30.sram_ctrl_executable.4169779902 |
|
|
Jun 23 06:27:03 PM PDT 24 |
Jun 23 06:36:18 PM PDT 24 |
12038592329 ps |
| T873 |
/workspace/coverage/default/38.sram_ctrl_smoke.871041405 |
|
|
Jun 23 06:27:48 PM PDT 24 |
Jun 23 06:27:53 PM PDT 24 |
55397037 ps |
| T874 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.1819204169 |
|
|
Jun 23 06:24:22 PM PDT 24 |
Jun 23 06:25:12 PM PDT 24 |
100226626 ps |
| T875 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2696107244 |
|
|
Jun 23 06:28:01 PM PDT 24 |
Jun 23 06:28:11 PM PDT 24 |
685105986 ps |
| T876 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2608411604 |
|
|
Jun 23 06:27:34 PM PDT 24 |
Jun 23 06:33:58 PM PDT 24 |
25221882312 ps |
| T49 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3124400609 |
|
|
Jun 23 06:26:53 PM PDT 24 |
Jun 23 06:31:45 PM PDT 24 |
12702385466 ps |
| T877 |
/workspace/coverage/default/18.sram_ctrl_stress_all.687429587 |
|
|
Jun 23 06:25:52 PM PDT 24 |
Jun 23 07:14:40 PM PDT 24 |
82036778599 ps |
| T878 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2189055921 |
|
|
Jun 23 06:25:24 PM PDT 24 |
Jun 23 06:25:35 PM PDT 24 |
2739462340 ps |
| T879 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3954062111 |
|
|
Jun 23 06:24:30 PM PDT 24 |
Jun 23 06:39:18 PM PDT 24 |
4337066124 ps |
| T880 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3364782834 |
|
|
Jun 23 06:26:43 PM PDT 24 |
Jun 23 06:28:49 PM PDT 24 |
507118926 ps |
| T881 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1920705383 |
|
|
Jun 23 06:28:47 PM PDT 24 |
Jun 23 06:32:54 PM PDT 24 |
9818524128 ps |
| T882 |
/workspace/coverage/default/46.sram_ctrl_executable.1533592838 |
|
|
Jun 23 06:28:38 PM PDT 24 |
Jun 23 06:40:32 PM PDT 24 |
14121699034 ps |
| T883 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4255225205 |
|
|
Jun 23 06:29:01 PM PDT 24 |
Jun 23 06:29:02 PM PDT 24 |
71618624 ps |
| T884 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.4072426546 |
|
|
Jun 23 06:25:54 PM PDT 24 |
Jun 23 06:25:57 PM PDT 24 |
82247355 ps |
| T885 |
/workspace/coverage/default/43.sram_ctrl_executable.3294211938 |
|
|
Jun 23 06:28:20 PM PDT 24 |
Jun 23 06:32:31 PM PDT 24 |
6105697476 ps |
| T886 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.628289749 |
|
|
Jun 23 06:26:01 PM PDT 24 |
Jun 23 06:26:02 PM PDT 24 |
81286114 ps |
| T887 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1044339278 |
|
|
Jun 23 06:28:29 PM PDT 24 |
Jun 23 06:32:06 PM PDT 24 |
5829297105 ps |
| T888 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.917435005 |
|
|
Jun 23 06:28:30 PM PDT 24 |
Jun 23 06:50:43 PM PDT 24 |
18634333394 ps |
| T889 |
/workspace/coverage/default/26.sram_ctrl_regwen.3197345608 |
|
|
Jun 23 06:26:37 PM PDT 24 |
Jun 23 06:27:06 PM PDT 24 |
1416804044 ps |
| T890 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.3564671482 |
|
|
Jun 23 06:28:53 PM PDT 24 |
Jun 23 06:28:58 PM PDT 24 |
151319480 ps |
| T891 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3816526709 |
|
|
Jun 23 06:25:33 PM PDT 24 |
Jun 23 06:36:21 PM PDT 24 |
47785120145 ps |
| T892 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1628065172 |
|
|
Jun 23 06:24:29 PM PDT 24 |
Jun 23 06:31:26 PM PDT 24 |
3659960879 ps |
| T893 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2827357229 |
|
|
Jun 23 06:24:38 PM PDT 24 |
Jun 23 06:30:03 PM PDT 24 |
4410892406 ps |
| T894 |
/workspace/coverage/default/29.sram_ctrl_alert_test.558053990 |
|
|
Jun 23 06:26:57 PM PDT 24 |
Jun 23 06:26:57 PM PDT 24 |
45704811 ps |
| T895 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1841444254 |
|
|
Jun 23 06:26:45 PM PDT 24 |
Jun 23 06:26:46 PM PDT 24 |
17184120 ps |
| T896 |
/workspace/coverage/default/6.sram_ctrl_smoke.330544856 |
|
|
Jun 23 06:24:49 PM PDT 24 |
Jun 23 06:26:54 PM PDT 24 |
697528470 ps |
| T897 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.2636898525 |
|
|
Jun 23 06:26:18 PM PDT 24 |
Jun 23 06:27:25 PM PDT 24 |
1581157843 ps |
| T898 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1781132032 |
|
|
Jun 23 06:24:32 PM PDT 24 |
Jun 23 07:41:37 PM PDT 24 |
179519713860 ps |
| T899 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1789408879 |
|
|
Jun 23 06:25:19 PM PDT 24 |
Jun 23 06:25:21 PM PDT 24 |
526376758 ps |
| T900 |
/workspace/coverage/default/37.sram_ctrl_executable.1259080733 |
|
|
Jun 23 06:27:46 PM PDT 24 |
Jun 23 06:43:28 PM PDT 24 |
79676974500 ps |
| T901 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.2669092199 |
|
|
Jun 23 06:27:36 PM PDT 24 |
Jun 23 06:27:41 PM PDT 24 |
1289116926 ps |
| T902 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.2221681887 |
|
|
Jun 23 06:26:16 PM PDT 24 |
Jun 23 06:26:18 PM PDT 24 |
78652006 ps |
| T903 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1309051962 |
|
|
Jun 23 06:27:46 PM PDT 24 |
Jun 23 06:28:59 PM PDT 24 |
316613225 ps |
| T904 |
/workspace/coverage/default/4.sram_ctrl_regwen.2738715917 |
|
|
Jun 23 06:24:39 PM PDT 24 |
Jun 23 06:42:32 PM PDT 24 |
28354133449 ps |
| T905 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2578214504 |
|
|
Jun 23 06:28:06 PM PDT 24 |
Jun 23 06:28:12 PM PDT 24 |
202673458 ps |
| T906 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2302761591 |
|
|
Jun 23 06:25:47 PM PDT 24 |
Jun 23 06:35:03 PM PDT 24 |
7387026871 ps |
| T907 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3986947165 |
|
|
Jun 23 06:25:06 PM PDT 24 |
Jun 23 06:28:39 PM PDT 24 |
10719896591 ps |
| T908 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2858784074 |
|
|
Jun 23 06:24:48 PM PDT 24 |
Jun 23 07:35:25 PM PDT 24 |
93015627560 ps |
| T909 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.540535801 |
|
|
Jun 23 06:24:56 PM PDT 24 |
Jun 23 06:24:57 PM PDT 24 |
93918591 ps |
| T910 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2574524447 |
|
|
Jun 23 06:27:06 PM PDT 24 |
Jun 23 06:31:33 PM PDT 24 |
14933800704 ps |
| T911 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.615080213 |
|
|
Jun 23 06:28:48 PM PDT 24 |
Jun 23 06:29:37 PM PDT 24 |
11292763840 ps |
| T912 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.788601877 |
|
|
Jun 23 06:25:48 PM PDT 24 |
Jun 23 06:47:53 PM PDT 24 |
15735069320 ps |
| T913 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.447079762 |
|
|
Jun 23 06:26:54 PM PDT 24 |
Jun 23 06:29:03 PM PDT 24 |
1825576038 ps |
| T914 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1013814203 |
|
|
Jun 23 06:28:00 PM PDT 24 |
Jun 23 06:29:03 PM PDT 24 |
12334405466 ps |
| T915 |
/workspace/coverage/default/1.sram_ctrl_bijection.2626440887 |
|
|
Jun 23 06:24:27 PM PDT 24 |
Jun 23 06:24:46 PM PDT 24 |
1107936951 ps |
| T916 |
/workspace/coverage/default/13.sram_ctrl_executable.1619985187 |
|
|
Jun 23 06:25:23 PM PDT 24 |
Jun 23 06:29:53 PM PDT 24 |
4404871093 ps |
| T917 |
/workspace/coverage/default/40.sram_ctrl_bijection.3752615892 |
|
|
Jun 23 06:27:56 PM PDT 24 |
Jun 23 06:28:38 PM PDT 24 |
1414526475 ps |
| T918 |
/workspace/coverage/default/1.sram_ctrl_smoke.2192133103 |
|
|
Jun 23 06:24:24 PM PDT 24 |
Jun 23 06:24:39 PM PDT 24 |
846507802 ps |
| T919 |
/workspace/coverage/default/14.sram_ctrl_alert_test.2345438376 |
|
|
Jun 23 06:25:33 PM PDT 24 |
Jun 23 06:25:34 PM PDT 24 |
33276472 ps |
| T920 |
/workspace/coverage/default/15.sram_ctrl_partial_access.873871792 |
|
|
Jun 23 06:25:39 PM PDT 24 |
Jun 23 06:27:40 PM PDT 24 |
1199774069 ps |
| T921 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2623388643 |
|
|
Jun 23 06:25:25 PM PDT 24 |
Jun 23 06:31:16 PM PDT 24 |
13308996096 ps |
| T922 |
/workspace/coverage/default/15.sram_ctrl_bijection.375597782 |
|
|
Jun 23 06:25:34 PM PDT 24 |
Jun 23 06:25:53 PM PDT 24 |
3786989125 ps |
| T923 |
/workspace/coverage/default/2.sram_ctrl_smoke.3523174753 |
|
|
Jun 23 06:24:30 PM PDT 24 |
Jun 23 06:24:36 PM PDT 24 |
168001064 ps |
| T924 |
/workspace/coverage/default/31.sram_ctrl_smoke.2395469243 |
|
|
Jun 23 06:27:05 PM PDT 24 |
Jun 23 06:27:08 PM PDT 24 |
610641168 ps |
| T925 |
/workspace/coverage/default/9.sram_ctrl_smoke.3554616438 |
|
|
Jun 23 06:25:03 PM PDT 24 |
Jun 23 06:25:17 PM PDT 24 |
862140597 ps |
| T926 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.2802563316 |
|
|
Jun 23 06:28:33 PM PDT 24 |
Jun 23 06:28:42 PM PDT 24 |
140457898 ps |
| T927 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1393179293 |
|
|
Jun 23 06:28:01 PM PDT 24 |
Jun 23 06:36:23 PM PDT 24 |
18859911331 ps |
| T928 |
/workspace/coverage/default/10.sram_ctrl_executable.643897417 |
|
|
Jun 23 06:25:16 PM PDT 24 |
Jun 23 06:52:23 PM PDT 24 |
21409868120 ps |
| T929 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.340782425 |
|
|
Jun 23 06:26:15 PM PDT 24 |
Jun 23 06:26:20 PM PDT 24 |
364197618 ps |
| T930 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.554144045 |
|
|
Jun 23 06:27:02 PM PDT 24 |
Jun 23 06:44:15 PM PDT 24 |
11594138689 ps |
| T931 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1823222940 |
|
|
Jun 23 06:24:31 PM PDT 24 |
Jun 23 06:24:39 PM PDT 24 |
131228953 ps |
| T932 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2561840527 |
|
|
Jun 23 06:28:52 PM PDT 24 |
Jun 23 07:06:13 PM PDT 24 |
217199000670 ps |
| T933 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3740252283 |
|
|
Jun 23 06:24:27 PM PDT 24 |
Jun 23 06:25:13 PM PDT 24 |
726853279 ps |
| T65 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2326824481 |
|
|
Jun 23 06:16:50 PM PDT 24 |
Jun 23 06:16:51 PM PDT 24 |
21616140 ps |
| T61 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1177021873 |
|
|
Jun 23 06:16:38 PM PDT 24 |
Jun 23 06:16:42 PM PDT 24 |
4937714209 ps |
| T66 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1344092862 |
|
|
Jun 23 06:16:36 PM PDT 24 |
Jun 23 06:16:38 PM PDT 24 |
138083535 ps |
| T95 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2215660402 |
|
|
Jun 23 06:16:45 PM PDT 24 |
Jun 23 06:16:47 PM PDT 24 |
23192871 ps |
| T72 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1436314435 |
|
|
Jun 23 06:16:38 PM PDT 24 |
Jun 23 06:16:40 PM PDT 24 |
136204287 ps |
| T105 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.39963203 |
|
|
Jun 23 06:16:38 PM PDT 24 |
Jun 23 06:16:39 PM PDT 24 |
40292242 ps |
| T62 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4009684105 |
|
|
Jun 23 06:16:47 PM PDT 24 |
Jun 23 06:16:50 PM PDT 24 |
146490962 ps |
| T934 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1072574639 |
|
|
Jun 23 06:16:27 PM PDT 24 |
Jun 23 06:16:29 PM PDT 24 |
26884700 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1589516429 |
|
|
Jun 23 06:16:35 PM PDT 24 |
Jun 23 06:16:37 PM PDT 24 |
27097740 ps |
| T74 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.282997256 |
|
|
Jun 23 06:16:47 PM PDT 24 |
Jun 23 06:16:49 PM PDT 24 |
41948014 ps |
| T75 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.101204226 |
|
|
Jun 23 06:17:03 PM PDT 24 |
Jun 23 06:17:05 PM PDT 24 |
25215742 ps |
| T63 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3898001033 |
|
|
Jun 23 06:16:33 PM PDT 24 |
Jun 23 06:16:36 PM PDT 24 |
3007169118 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1211519199 |
|
|
Jun 23 06:16:36 PM PDT 24 |
Jun 23 06:16:38 PM PDT 24 |
16488238 ps |
| T76 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3580719163 |
|
|
Jun 23 06:16:54 PM PDT 24 |
Jun 23 06:16:58 PM PDT 24 |
1820358865 ps |
| T935 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2631776658 |
|
|
Jun 23 06:16:45 PM PDT 24 |
Jun 23 06:16:49 PM PDT 24 |
134711382 ps |
| T77 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3916272274 |
|
|
Jun 23 06:16:52 PM PDT 24 |
Jun 23 06:16:54 PM PDT 24 |
417165789 ps |
| T78 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3235203096 |
|
|
Jun 23 06:16:35 PM PDT 24 |
Jun 23 06:16:38 PM PDT 24 |
242224555 ps |
| T936 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2945798989 |
|
|
Jun 23 06:16:32 PM PDT 24 |
Jun 23 06:16:33 PM PDT 24 |
22130898 ps |
| T937 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4112431105 |
|
|
Jun 23 06:16:34 PM PDT 24 |
Jun 23 06:16:36 PM PDT 24 |
28309817 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1824053404 |
|
|
Jun 23 06:16:32 PM PDT 24 |
Jun 23 06:16:34 PM PDT 24 |
225530346 ps |
| T79 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3135341658 |
|
|
Jun 23 06:16:41 PM PDT 24 |
Jun 23 06:16:45 PM PDT 24 |
1513965205 ps |
| T97 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3339433569 |
|
|
Jun 23 06:16:36 PM PDT 24 |
Jun 23 06:16:38 PM PDT 24 |
25816063 ps |
| T938 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.835612853 |
|
|
Jun 23 06:16:54 PM PDT 24 |
Jun 23 06:16:56 PM PDT 24 |
134517577 ps |
| T939 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2614778188 |
|
|
Jun 23 06:17:03 PM PDT 24 |
Jun 23 06:17:06 PM PDT 24 |
56162988 ps |
| T113 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2861604938 |
|
|
Jun 23 06:16:34 PM PDT 24 |
Jun 23 06:16:35 PM PDT 24 |
30772651 ps |
| T80 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1006013890 |
|
|
Jun 23 06:16:52 PM PDT 24 |
Jun 23 06:16:53 PM PDT 24 |
93969090 ps |
| T126 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2675542000 |
|
|
Jun 23 06:16:45 PM PDT 24 |
Jun 23 06:16:48 PM PDT 24 |
182017328 ps |
| T122 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1543152637 |
|
|
Jun 23 06:16:34 PM PDT 24 |
Jun 23 06:16:36 PM PDT 24 |
103815965 ps |
| T940 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3848446060 |
|
|
Jun 23 06:16:27 PM PDT 24 |
Jun 23 06:16:31 PM PDT 24 |
78134058 ps |
| T941 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3205994360 |
|
|
Jun 23 06:16:56 PM PDT 24 |
Jun 23 06:16:57 PM PDT 24 |
40203675 ps |
| T123 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1188314912 |
|
|
Jun 23 06:16:39 PM PDT 24 |
Jun 23 06:16:41 PM PDT 24 |
105255745 ps |
| T127 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3414321475 |
|
|
Jun 23 06:16:36 PM PDT 24 |
Jun 23 06:16:39 PM PDT 24 |
283828384 ps |
| T81 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.795321175 |
|
|
Jun 23 06:16:58 PM PDT 24 |
Jun 23 06:17:01 PM PDT 24 |
1720342685 ps |
| T942 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1105285632 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:16:58 PM PDT 24 |
138141944 ps |
| T943 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.155447871 |
|
|
Jun 23 06:16:45 PM PDT 24 |
Jun 23 06:16:47 PM PDT 24 |
38788257 ps |
| T944 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.238313576 |
|
|
Jun 23 06:16:30 PM PDT 24 |
Jun 23 06:16:31 PM PDT 24 |
13774296 ps |
| T82 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3115489515 |
|
|
Jun 23 06:16:38 PM PDT 24 |
Jun 23 06:16:41 PM PDT 24 |
221240566 ps |
| T114 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2952045175 |
|
|
Jun 23 06:17:03 PM PDT 24 |
Jun 23 06:17:06 PM PDT 24 |
330041384 ps |
| T115 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3204816638 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:16:57 PM PDT 24 |
40823913 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2884350012 |
|
|
Jun 23 06:16:34 PM PDT 24 |
Jun 23 06:16:39 PM PDT 24 |
548471249 ps |
| T946 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.301357522 |
|
|
Jun 23 06:16:57 PM PDT 24 |
Jun 23 06:16:59 PM PDT 24 |
34995418 ps |
| T83 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.102861728 |
|
|
Jun 23 06:16:34 PM PDT 24 |
Jun 23 06:16:35 PM PDT 24 |
31482245 ps |
| T129 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.99189210 |
|
|
Jun 23 06:16:43 PM PDT 24 |
Jun 23 06:16:45 PM PDT 24 |
91046295 ps |
| T947 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1222312893 |
|
|
Jun 23 06:16:50 PM PDT 24 |
Jun 23 06:16:52 PM PDT 24 |
72555732 ps |
| T948 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2014039019 |
|
|
Jun 23 06:16:44 PM PDT 24 |
Jun 23 06:16:45 PM PDT 24 |
23146920 ps |
| T949 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2835210782 |
|
|
Jun 23 06:16:47 PM PDT 24 |
Jun 23 06:16:49 PM PDT 24 |
12615391 ps |
| T950 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2169012017 |
|
|
Jun 23 06:16:50 PM PDT 24 |
Jun 23 06:16:51 PM PDT 24 |
29692798 ps |
| T951 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.315559105 |
|
|
Jun 23 06:17:02 PM PDT 24 |
Jun 23 06:17:03 PM PDT 24 |
43762875 ps |
| T120 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2442863854 |
|
|
Jun 23 06:16:53 PM PDT 24 |
Jun 23 06:16:56 PM PDT 24 |
369642474 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1089535463 |
|
|
Jun 23 06:16:52 PM PDT 24 |
Jun 23 06:16:55 PM PDT 24 |
3340742614 ps |
| T94 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2879452207 |
|
|
Jun 23 06:16:53 PM PDT 24 |
Jun 23 06:16:54 PM PDT 24 |
19718701 ps |
| T953 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3572401071 |
|
|
Jun 23 06:17:02 PM PDT 24 |
Jun 23 06:17:05 PM PDT 24 |
42174196 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1122077873 |
|
|
Jun 23 06:16:37 PM PDT 24 |
Jun 23 06:16:38 PM PDT 24 |
19864876 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1700290280 |
|
|
Jun 23 06:16:37 PM PDT 24 |
Jun 23 06:16:42 PM PDT 24 |
413350863 ps |
| T124 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3668338901 |
|
|
Jun 23 06:16:52 PM PDT 24 |
Jun 23 06:16:55 PM PDT 24 |
447614938 ps |
| T84 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.779070902 |
|
|
Jun 23 06:16:44 PM PDT 24 |
Jun 23 06:16:48 PM PDT 24 |
1655957082 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.195900277 |
|
|
Jun 23 06:16:44 PM PDT 24 |
Jun 23 06:16:46 PM PDT 24 |
124986416 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1557767924 |
|
|
Jun 23 06:16:34 PM PDT 24 |
Jun 23 06:16:36 PM PDT 24 |
93303938 ps |
| T85 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.310861979 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:16:57 PM PDT 24 |
737533768 ps |
| T91 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3330225558 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:16:58 PM PDT 24 |
4065919469 ps |
| T128 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2582935505 |
|
|
Jun 23 06:16:49 PM PDT 24 |
Jun 23 06:16:51 PM PDT 24 |
264023095 ps |
| T92 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1299095878 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:16:56 PM PDT 24 |
22823732 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1968839071 |
|
|
Jun 23 06:16:34 PM PDT 24 |
Jun 23 06:16:36 PM PDT 24 |
98300588 ps |
| T958 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.126627596 |
|
|
Jun 23 06:16:53 PM PDT 24 |
Jun 23 06:16:54 PM PDT 24 |
17396727 ps |
| T959 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.404879941 |
|
|
Jun 23 06:16:49 PM PDT 24 |
Jun 23 06:16:51 PM PDT 24 |
94040251 ps |
| T116 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1327201362 |
|
|
Jun 23 06:16:49 PM PDT 24 |
Jun 23 06:16:53 PM PDT 24 |
85854591 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2980421175 |
|
|
Jun 23 06:16:33 PM PDT 24 |
Jun 23 06:16:34 PM PDT 24 |
184779662 ps |
| T961 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3439789551 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:16:57 PM PDT 24 |
25143536 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1169446944 |
|
|
Jun 23 06:16:45 PM PDT 24 |
Jun 23 06:16:47 PM PDT 24 |
64993920 ps |
| T963 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3366023502 |
|
|
Jun 23 06:16:48 PM PDT 24 |
Jun 23 06:16:49 PM PDT 24 |
15563259 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.817366915 |
|
|
Jun 23 06:16:42 PM PDT 24 |
Jun 23 06:16:44 PM PDT 24 |
175127450 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3118261181 |
|
|
Jun 23 06:16:35 PM PDT 24 |
Jun 23 06:16:37 PM PDT 24 |
14971920 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1333665829 |
|
|
Jun 23 06:16:47 PM PDT 24 |
Jun 23 06:16:49 PM PDT 24 |
43790065 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1356517448 |
|
|
Jun 23 06:16:39 PM PDT 24 |
Jun 23 06:16:43 PM PDT 24 |
1404632142 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.409579896 |
|
|
Jun 23 06:16:37 PM PDT 24 |
Jun 23 06:16:38 PM PDT 24 |
21313380 ps |
| T969 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3344932548 |
|
|
Jun 23 06:17:00 PM PDT 24 |
Jun 23 06:17:01 PM PDT 24 |
58684079 ps |
| T970 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.181944860 |
|
|
Jun 23 06:16:39 PM PDT 24 |
Jun 23 06:16:42 PM PDT 24 |
79631548 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2489474092 |
|
|
Jun 23 06:16:25 PM PDT 24 |
Jun 23 06:16:26 PM PDT 24 |
18347527 ps |
| T972 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.195320632 |
|
|
Jun 23 06:16:46 PM PDT 24 |
Jun 23 06:16:51 PM PDT 24 |
180274931 ps |
| T973 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.527631194 |
|
|
Jun 23 06:16:45 PM PDT 24 |
Jun 23 06:16:51 PM PDT 24 |
539553907 ps |
| T125 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3172671273 |
|
|
Jun 23 06:16:53 PM PDT 24 |
Jun 23 06:16:56 PM PDT 24 |
686830197 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2778634965 |
|
|
Jun 23 06:16:33 PM PDT 24 |
Jun 23 06:16:35 PM PDT 24 |
811655928 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2189185066 |
|
|
Jun 23 06:16:54 PM PDT 24 |
Jun 23 06:16:57 PM PDT 24 |
1262639784 ps |
| T976 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.178855946 |
|
|
Jun 23 06:16:43 PM PDT 24 |
Jun 23 06:16:45 PM PDT 24 |
201003014 ps |
| T977 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3161622216 |
|
|
Jun 23 06:16:56 PM PDT 24 |
Jun 23 06:16:58 PM PDT 24 |
99078587 ps |
| T978 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2626909995 |
|
|
Jun 23 06:16:45 PM PDT 24 |
Jun 23 06:16:48 PM PDT 24 |
206784310 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.589527488 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:16:57 PM PDT 24 |
176863731 ps |
| T980 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4177681882 |
|
|
Jun 23 06:16:51 PM PDT 24 |
Jun 23 06:16:55 PM PDT 24 |
438909870 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3395896022 |
|
|
Jun 23 06:17:03 PM PDT 24 |
Jun 23 06:17:04 PM PDT 24 |
15724879 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.246456697 |
|
|
Jun 23 06:16:40 PM PDT 24 |
Jun 23 06:16:42 PM PDT 24 |
299368471 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1734771191 |
|
|
Jun 23 06:16:45 PM PDT 24 |
Jun 23 06:16:47 PM PDT 24 |
15432093 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1793480893 |
|
|
Jun 23 06:16:30 PM PDT 24 |
Jun 23 06:16:32 PM PDT 24 |
286391700 ps |
| T985 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1466953159 |
|
|
Jun 23 06:16:51 PM PDT 24 |
Jun 23 06:16:52 PM PDT 24 |
47493263 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2160985963 |
|
|
Jun 23 06:17:02 PM PDT 24 |
Jun 23 06:17:03 PM PDT 24 |
14276902 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3526225119 |
|
|
Jun 23 06:16:57 PM PDT 24 |
Jun 23 06:16:59 PM PDT 24 |
117453653 ps |
| T988 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1775820363 |
|
|
Jun 23 06:16:46 PM PDT 24 |
Jun 23 06:16:47 PM PDT 24 |
25290220 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.223981586 |
|
|
Jun 23 06:16:28 PM PDT 24 |
Jun 23 06:16:30 PM PDT 24 |
50937655 ps |
| T990 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3795053777 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:16:59 PM PDT 24 |
462466036 ps |
| T991 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1388222604 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:17:00 PM PDT 24 |
99587147 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4204479346 |
|
|
Jun 23 06:16:39 PM PDT 24 |
Jun 23 06:16:40 PM PDT 24 |
47452658 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2580434617 |
|
|
Jun 23 06:16:26 PM PDT 24 |
Jun 23 06:16:27 PM PDT 24 |
33211941 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3482146360 |
|
|
Jun 23 06:17:02 PM PDT 24 |
Jun 23 06:17:06 PM PDT 24 |
137864301 ps |
| T995 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.687977810 |
|
|
Jun 23 06:16:55 PM PDT 24 |
Jun 23 06:16:56 PM PDT 24 |
81009071 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.731735040 |
|
|
Jun 23 06:16:32 PM PDT 24 |
Jun 23 06:16:33 PM PDT 24 |
32332863 ps |
| T117 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2359650410 |
|
|
Jun 23 06:16:53 PM PDT 24 |
Jun 23 06:16:55 PM PDT 24 |
45367478 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.134172536 |
|
|
Jun 23 06:16:50 PM PDT 24 |
Jun 23 06:16:51 PM PDT 24 |
19621039 ps |
| T998 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2465432831 |
|
|
Jun 23 06:16:45 PM PDT 24 |
Jun 23 06:16:47 PM PDT 24 |
27697792 ps |
| T999 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3598285495 |
|
|
Jun 23 06:16:51 PM PDT 24 |
Jun 23 06:16:54 PM PDT 24 |
1688393789 ps |
| T1000 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2249723769 |
|
|
Jun 23 06:16:49 PM PDT 24 |
Jun 23 06:16:51 PM PDT 24 |
55137005 ps |
| T1001 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2628637048 |
|
|
Jun 23 06:16:38 PM PDT 24 |
Jun 23 06:16:40 PM PDT 24 |
296706698 ps |
| T1002 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4043410755 |
|
|
Jun 23 06:16:56 PM PDT 24 |
Jun 23 06:16:58 PM PDT 24 |
187444751 ps |