Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Total test records in report: 1018

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1003	/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2035342625			Jun 23 06:16:34 PM PDT 24	Jun 23 06:16:35 PM PDT 24	35555099 ps
T1004	/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1921887930			Jun 23 06:16:39 PM PDT 24	Jun 23 06:16:40 PM PDT 24	32763962 ps
T1005	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2303450971			Jun 23 06:16:41 PM PDT 24	Jun 23 06:16:45 PM PDT 24	169842353 ps
T118	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3679376931			Jun 23 06:16:52 PM PDT 24	Jun 23 06:16:55 PM PDT 24	81608389 ps
T1006	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3754483900			Jun 23 06:16:46 PM PDT 24	Jun 23 06:16:52 PM PDT 24	148081903 ps
T1007	/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1965226491			Jun 23 06:16:46 PM PDT 24	Jun 23 06:16:47 PM PDT 24	24882239 ps
T1008	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3570880079			Jun 23 06:16:50 PM PDT 24	Jun 23 06:16:51 PM PDT 24	17148510 ps
T1009	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4045454284			Jun 23 06:16:34 PM PDT 24	Jun 23 06:16:35 PM PDT 24	41947068 ps
T1010	/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.617328407			Jun 23 06:16:50 PM PDT 24	Jun 23 06:16:52 PM PDT 24	469198183 ps
T1011	/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1731637607			Jun 23 06:16:58 PM PDT 24	Jun 23 06:16:59 PM PDT 24	39861269 ps
T1012	/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.332421268			Jun 23 06:17:02 PM PDT 24	Jun 23 06:17:03 PM PDT 24	68807430 ps
T1013	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.392642107			Jun 23 06:16:55 PM PDT 24	Jun 23 06:16:57 PM PDT 24	25971147 ps
T1014	/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.833018027			Jun 23 06:16:44 PM PDT 24	Jun 23 06:16:48 PM PDT 24	460948097 ps
T1015	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2701231573			Jun 23 06:16:39 PM PDT 24	Jun 23 06:16:44 PM PDT 24	503890854 ps
T1016	/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1163561190			Jun 23 06:16:35 PM PDT 24	Jun 23 06:16:36 PM PDT 24	141538904 ps
T1017	/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1479642261			Jun 23 06:16:38 PM PDT 24	Jun 23 06:16:42 PM PDT 24	548897101 ps
T1018	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3713975573			Jun 23 06:16:49 PM PDT 24	Jun 23 06:16:53 PM PDT 24	177757065 ps
T119	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3779067386			Jun 23 06:16:51 PM PDT 24	Jun 23 06:16:55 PM PDT 24	138502392 ps

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1930095542
Short name	T9
Test name
Test status
Simulation time	11317740438 ps
CPU time	192.1 seconds
Started	Jun 23 06:29:05 PM PDT 24
Finished	Jun 23 06:32:18 PM PDT 24
Peak memory	352096 kb
Host	smart-ef59e3c5-f3ef-4def-83dc-0aa6c4bb99a4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1930095542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1930095542
Directory	/workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3163460542
Short name	T46
Test name
Test status
Simulation time	515406844 ps
CPU time	8.34 seconds
Started	Jun 23 06:25:47 PM PDT 24
Finished	Jun 23 06:25:56 PM PDT 24
Peak memory	211440 kb
Host	smart-4a23125d-e756-43e8-87f0-eeb9b99e4b82
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3163460542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.3163460542
Directory	/workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all.199108570
Short name	T4
Test name
Test status
Simulation time	53644128376 ps
CPU time	2078.08 seconds
Started	Jun 23 06:29:03 PM PDT 24
Finished	Jun 23 07:03:41 PM PDT 24
Peak memory	374664 kb
Host	smart-81b2d490-81c6-4fe8-9803-932e1e3f1ffb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199108570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_stress_all.199108570
Directory	/workspace/49.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1177021873
Short name	T61
Test name
Test status
Simulation time	4937714209 ps
CPU time	3.44 seconds
Started	Jun 23 06:16:38 PM PDT 24
Finished	Jun 23 06:16:42 PM PDT 24
Peak memory	211248 kb
Host	smart-156b4b1d-3ae3-4433-8f62-611e5eeca42e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177021873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1177021873
Directory	/workspace/1.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/43.sram_ctrl_regwen.1071773677
Short name	T43
Test name
Test status
Simulation time	21759677544 ps
CPU time	889.43 seconds
Started	Jun 23 06:28:21 PM PDT 24
Finished	Jun 23 06:43:11 PM PDT 24
Peak memory	373956 kb
Host	smart-e5899d5a-ffe1-42f9-8106-96a019bce63c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071773677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1071773677
Directory	/workspace/43.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/0.sram_ctrl_sec_cm.2161781309
Short name	T18
Test name
Test status
Simulation time	233781573 ps
CPU time	2.37 seconds
Started	Jun 23 06:24:35 PM PDT 24
Finished	Jun 23 06:24:38 PM PDT 24
Peak memory	221920 kb
Host	smart-5b1a5aa5-4a62-4388-aee9-b83ec4dfe0b2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161781309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2161781309
Directory	/workspace/0.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all.3585921962
Short name	T112
Test name
Test status
Simulation time	8030280920 ps
CPU time	2402.11 seconds
Started	Jun 23 06:25:07 PM PDT 24
Finished	Jun 23 07:05:10 PM PDT 24
Peak memory	374928 kb
Host	smart-aef444f0-8375-4365-b919-f49de6abef0b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585921962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.3585921962
Directory	/workspace/9.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.sram_ctrl_alert_test.1399452222
Short name	T164
Test name
Test status
Simulation time	12484469 ps
CPU time	0.63 seconds
Started	Jun 23 06:25:01 PM PDT 24
Finished	Jun 23 06:25:02 PM PDT 24
Peak memory	202944 kb
Host	smart-f7c9ed41-2f2c-4d7b-9b92-0f7ed9624a3d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399452222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.1399452222
Directory	/workspace/8.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3668338901
Short name	T124
Test name
Test status
Simulation time	447614938 ps
CPU time	2.33 seconds
Started	Jun 23 06:16:52 PM PDT 24
Finished	Jun 23 06:16:55 PM PDT 24
Peak memory	202872 kb
Host	smart-583b8ff7-7012-407d-a73b-0efb490ae7f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668338901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.3668338901
Directory	/workspace/13.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2346413687
Short name	T39
Test name
Test status
Simulation time	4181749922 ps
CPU time	459.58 seconds
Started	Jun 23 06:27:34 PM PDT 24
Finished	Jun 23 06:35:14 PM PDT 24
Peak memory	372028 kb
Host	smart-c25ab315-2380-4533-bb60-271184c0f272
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346413687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.2346413687
Directory	/workspace/36.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3271963932
Short name	T99
Test name
Test status
Simulation time	88614244191 ps
CPU time	545.64 seconds
Started	Jun 23 06:27:30 PM PDT 24
Finished	Jun 23 06:36:36 PM PDT 24
Peak memory	203164 kb
Host	smart-6016e9ca-9c7f-430f-8292-f7e47cbed019
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271963932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.3271963932
Directory	/workspace/35.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3580719163
Short name	T76
Test name
Test status
Simulation time	1820358865 ps
CPU time	3.35 seconds
Started	Jun 23 06:16:54 PM PDT 24
Finished	Jun 23 06:16:58 PM PDT 24
Peak memory	203048 kb
Host	smart-2f4e9bfb-a72c-4d87-9ed8-cb28863bfa85
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580719163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.3580719163
Directory	/workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/default/1.sram_ctrl_ram_cfg.3042883668
Short name	T259
Test name
Test status
Simulation time	59962476 ps
CPU time	0.77 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:24:32 PM PDT 24
Peak memory	202676 kb
Host	smart-b4112c76-f675-49bb-bad3-6540bedbc682
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042883668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3042883668
Directory	/workspace/1.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/18.sram_ctrl_executable.1566410159
Short name	T64
Test name
Test status
Simulation time	2275862458 ps
CPU time	957.48 seconds
Started	Jun 23 06:25:54 PM PDT 24
Finished	Jun 23 06:41:51 PM PDT 24
Peak memory	373952 kb
Host	smart-282dfc52-93d1-45bc-bff2-bd5552eb2973
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566410159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.1566410159
Directory	/workspace/18.sram_ctrl_executable/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2442863854
Short name	T120
Test name
Test status
Simulation time	369642474 ps
CPU time	2.54 seconds
Started	Jun 23 06:16:53 PM PDT 24
Finished	Jun 23 06:16:56 PM PDT 24
Peak memory	211068 kb
Host	smart-378a7384-ea2e-4759-8b1b-8a13ddb3e9ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442863854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.2442863854
Directory	/workspace/14.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3124400609
Short name	T49
Test name
Test status
Simulation time	12702385466 ps
CPU time	291.03 seconds
Started	Jun 23 06:26:53 PM PDT 24
Finished	Jun 23 06:31:45 PM PDT 24
Peak memory	361004 kb
Host	smart-175b8737-082b-44ea-baf6-20361280f0d2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3124400609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.3124400609
Directory	/workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.sram_ctrl_regwen.347318394
Short name	T539
Test name
Test status
Simulation time	18765308060 ps
CPU time	1171.38 seconds
Started	Jun 23 06:24:20 PM PDT 24
Finished	Jun 23 06:43:51 PM PDT 24
Peak memory	375948 kb
Host	smart-7a6667d8-a2bd-44d9-a3d3-7668fe13e945
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347318394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.347318394
Directory	/workspace/0.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/1.sram_ctrl_lc_escalation.85752757
Short name	T185
Test name
Test status
Simulation time	1022986104 ps
CPU time	8.25 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:24:40 PM PDT 24
Peak memory	202592 kb
Host	smart-bd2e153a-db27-42b2-a4f0-859575559779
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85752757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escal ation.85752757
Directory	/workspace/1.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2861604938
Short name	T113
Test name
Test status
Simulation time	30772651 ps
CPU time	1.04 seconds
Started	Jun 23 06:16:34 PM PDT 24
Finished	Jun 23 06:16:35 PM PDT 24
Peak memory	210900 kb
Host	smart-54c2e8b1-a7a9-4b18-acb5-1bd2ffb47816
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861604938 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2861604938
Directory	/workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.238313576
Short name	T944
Test name
Test status
Simulation time	13774296 ps
CPU time	0.68 seconds
Started	Jun 23 06:16:30 PM PDT 24
Finished	Jun 23 06:16:31 PM PDT 24
Peak memory	202620 kb
Host	smart-1ff3e0ec-10fd-4204-92e7-53d7a24e6e8d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238313576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_aliasing.238313576
Directory	/workspace/0.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1793480893
Short name	T984
Test name
Test status
Simulation time	286391700 ps
CPU time	1.4 seconds
Started	Jun 23 06:16:30 PM PDT 24
Finished	Jun 23 06:16:32 PM PDT 24
Peak memory	202816 kb
Host	smart-76211107-77d3-4451-b4b7-1752ce573313
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793480893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.1793480893
Directory	/workspace/0.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2489474092
Short name	T971
Test name
Test status
Simulation time	18347527 ps
CPU time	0.69 seconds
Started	Jun 23 06:16:25 PM PDT 24
Finished	Jun 23 06:16:26 PM PDT 24
Peak memory	202624 kb
Host	smart-1a092a87-5d15-4731-b178-071a23d3d44e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489474092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.2489474092
Directory	/workspace/0.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1072574639
Short name	T934
Test name
Test status
Simulation time	26884700 ps
CPU time	1.19 seconds
Started	Jun 23 06:16:27 PM PDT 24
Finished	Jun 23 06:16:29 PM PDT 24
Peak memory	210928 kb
Host	smart-6b8c964d-bb63-44be-8537-05859c2700b3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072574639 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1072574639
Directory	/workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2580434617
Short name	T993
Test name
Test status
Simulation time	33211941 ps
CPU time	0.66 seconds
Started	Jun 23 06:16:26 PM PDT 24
Finished	Jun 23 06:16:27 PM PDT 24
Peak memory	202636 kb
Host	smart-daae17a6-e83e-45a7-a169-e4105368a1bd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580434617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.2580434617
Directory	/workspace/0.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2778634965
Short name	T974
Test name
Test status
Simulation time	811655928 ps
CPU time	2.19 seconds
Started	Jun 23 06:16:33 PM PDT 24
Finished	Jun 23 06:16:35 PM PDT 24
Peak memory	202760 kb
Host	smart-2afe86cf-e9df-49de-a186-60c9f808ade8
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778634965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2778634965
Directory	/workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2980421175
Short name	T960
Test name
Test status
Simulation time	184779662 ps
CPU time	0.86 seconds
Started	Jun 23 06:16:33 PM PDT 24
Finished	Jun 23 06:16:34 PM PDT 24
Peak memory	202536 kb
Host	smart-b996e9cd-652d-474a-8589-5637cb8c54c0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980421175 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2980421175
Directory	/workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3848446060
Short name	T940
Test name
Test status
Simulation time	78134058 ps
CPU time	2.76 seconds
Started	Jun 23 06:16:27 PM PDT 24
Finished	Jun 23 06:16:31 PM PDT 24
Peak memory	211124 kb
Host	smart-ac33b45b-1b23-4b8b-8ccb-295e115a7ac6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848446060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.3848446060
Directory	/workspace/0.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3898001033
Short name	T63
Test name
Test status
Simulation time	3007169118 ps
CPU time	2.56 seconds
Started	Jun 23 06:16:33 PM PDT 24
Finished	Jun 23 06:16:36 PM PDT 24
Peak memory	211076 kb
Host	smart-ed2255fc-f372-4677-a1d2-40df6771bfd0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898001033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.3898001033
Directory	/workspace/0.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3118261181
Short name	T965
Test name
Test status
Simulation time	14971920 ps
CPU time	0.71 seconds
Started	Jun 23 06:16:35 PM PDT 24
Finished	Jun 23 06:16:37 PM PDT 24
Peak memory	202632 kb
Host	smart-df818ef2-a1ee-4aaf-8bdb-ba9303bbb7d0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118261181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.3118261181
Directory	/workspace/1.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1436314435
Short name	T72
Test name
Test status
Simulation time	136204287 ps
CPU time	1.38 seconds
Started	Jun 23 06:16:38 PM PDT 24
Finished	Jun 23 06:16:40 PM PDT 24
Peak memory	202836 kb
Host	smart-39820e21-3465-49ec-88fb-ab8f8c1abf92
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436314435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.1436314435
Directory	/workspace/1.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2945798989
Short name	T936
Test name
Test status
Simulation time	22130898 ps
CPU time	0.71 seconds
Started	Jun 23 06:16:32 PM PDT 24
Finished	Jun 23 06:16:33 PM PDT 24
Peak memory	202180 kb
Host	smart-a77ac677-1b78-4386-8f3a-cb030adabafe
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945798989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2945798989
Directory	/workspace/1.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.102861728
Short name	T83
Test name
Test status
Simulation time	31482245 ps
CPU time	0.65 seconds
Started	Jun 23 06:16:34 PM PDT 24
Finished	Jun 23 06:16:35 PM PDT 24
Peak memory	202576 kb
Host	smart-83191990-a39e-4947-9491-9ff1bed517e7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102861728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.sram_ctrl_csr_rw.102861728
Directory	/workspace/1.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1824053404
Short name	T96
Test name
Test status
Simulation time	225530346 ps
CPU time	1.99 seconds
Started	Jun 23 06:16:32 PM PDT 24
Finished	Jun 23 06:16:34 PM PDT 24
Peak memory	202804 kb
Host	smart-d42d909d-686f-4a9b-aee0-41ee60ba45b5
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824053404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1824053404
Directory	/workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1163561190
Short name	T1016
Test name
Test status
Simulation time	141538904 ps
CPU time	0.73 seconds
Started	Jun 23 06:16:35 PM PDT 24
Finished	Jun 23 06:16:36 PM PDT 24
Peak memory	202628 kb
Host	smart-801d1527-f12c-4e35-9ca1-47b5523bfb2c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163561190 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1163561190
Directory	/workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.223981586
Short name	T989
Test name
Test status
Simulation time	50937655 ps
CPU time	2.05 seconds
Started	Jun 23 06:16:28 PM PDT 24
Finished	Jun 23 06:16:30 PM PDT 24
Peak memory	202964 kb
Host	smart-f0e61ec8-66b6-4011-b0c8-2ad4511ddd14
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223981586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.223981586
Directory	/workspace/1.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3204816638
Short name	T115
Test name
Test status
Simulation time	40823913 ps
CPU time	1.35 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:57 PM PDT 24
Peak memory	211940 kb
Host	smart-c7821d8c-c399-45d0-92a9-9d2501c120d5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204816638 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3204816638
Directory	/workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1299095878
Short name	T92
Test name
Test status
Simulation time	22823732 ps
CPU time	0.68 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:56 PM PDT 24
Peak memory	202532 kb
Host	smart-4360ad9c-cfcd-4c98-8f9b-444c05a38ba8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299095878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.1299095878
Directory	/workspace/10.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.779070902
Short name	T84
Test name
Test status
Simulation time	1655957082 ps
CPU time	3.28 seconds
Started	Jun 23 06:16:44 PM PDT 24
Finished	Jun 23 06:16:48 PM PDT 24
Peak memory	203004 kb
Host	smart-486bd6f4-90ac-4d5b-beb3-f554611f50a8
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779070902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.779070902
Directory	/workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1333665829
Short name	T966
Test name
Test status
Simulation time	43790065 ps
CPU time	0.75 seconds
Started	Jun 23 06:16:47 PM PDT 24
Finished	Jun 23 06:16:49 PM PDT 24
Peak memory	202668 kb
Host	smart-3d1ec3ed-6f44-4c0b-9e56-b52aed5be826
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333665829 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.1333665829
Directory	/workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1388222604
Short name	T991
Test name
Test status
Simulation time	99587147 ps
CPU time	3.52 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:17:00 PM PDT 24
Peak memory	211044 kb
Host	smart-2641fbb5-4b6b-49de-93ad-2bdd06452b00
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388222604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.1388222604
Directory	/workspace/10.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4043410755
Short name	T1002
Test name
Test status
Simulation time	187444751 ps
CPU time	1.56 seconds
Started	Jun 23 06:16:56 PM PDT 24
Finished	Jun 23 06:16:58 PM PDT 24
Peak memory	210972 kb
Host	smart-ddfff890-24cd-47a3-917a-9c28c1e38642
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043410755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.4043410755
Directory	/workspace/10.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1222312893
Short name	T947
Test name
Test status
Simulation time	72555732 ps
CPU time	1.61 seconds
Started	Jun 23 06:16:50 PM PDT 24
Finished	Jun 23 06:16:52 PM PDT 24
Peak memory	211084 kb
Host	smart-3063c5de-385a-47d2-8cdd-e1fc187b4acd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222312893 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1222312893
Directory	/workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3366023502
Short name	T963
Test name
Test status
Simulation time	15563259 ps
CPU time	0.65 seconds
Started	Jun 23 06:16:48 PM PDT 24
Finished	Jun 23 06:16:49 PM PDT 24
Peak memory	202096 kb
Host	smart-968f81a8-651d-4b92-90e2-81660b316ee9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366023502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.3366023502
Directory	/workspace/11.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.178855946
Short name	T976
Test name
Test status
Simulation time	201003014 ps
CPU time	1.92 seconds
Started	Jun 23 06:16:43 PM PDT 24
Finished	Jun 23 06:16:45 PM PDT 24
Peak memory	202824 kb
Host	smart-c33b1675-4c40-426a-b1d3-4dfdfe81c78b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178855946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.178855946
Directory	/workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1006013890
Short name	T80
Test name
Test status
Simulation time	93969090 ps
CPU time	0.69 seconds
Started	Jun 23 06:16:52 PM PDT 24
Finished	Jun 23 06:16:53 PM PDT 24
Peak memory	202828 kb
Host	smart-3ce12c75-0ef9-44b8-9469-a5259fe4304a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006013890 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1006013890
Directory	/workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1327201362
Short name	T116
Test name
Test status
Simulation time	85854591 ps
CPU time	2.79 seconds
Started	Jun 23 06:16:49 PM PDT 24
Finished	Jun 23 06:16:53 PM PDT 24
Peak memory	202956 kb
Host	smart-b4ff3888-07cf-4b68-b374-a57e68f051c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327201362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1327201362
Directory	/workspace/11.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.99189210
Short name	T129
Test name
Test status
Simulation time	91046295 ps
CPU time	1.48 seconds
Started	Jun 23 06:16:43 PM PDT 24
Finished	Jun 23 06:16:45 PM PDT 24
Peak memory	211100 kb
Host	smart-1b23cec1-1dec-4315-9084-ddad215e92ca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99189210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 11.sram_ctrl_tl_intg_err.99189210
Directory	/workspace/11.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.404879941
Short name	T959
Test name
Test status
Simulation time	94040251 ps
CPU time	1 seconds
Started	Jun 23 06:16:49 PM PDT 24
Finished	Jun 23 06:16:51 PM PDT 24
Peak memory	210932 kb
Host	smart-d4d05464-e9f5-4f46-a7c9-965f513cd0ee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404879941 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.404879941
Directory	/workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.126627596
Short name	T958
Test name
Test status
Simulation time	17396727 ps
CPU time	0.72 seconds
Started	Jun 23 06:16:53 PM PDT 24
Finished	Jun 23 06:16:54 PM PDT 24
Peak memory	202800 kb
Host	smart-3743cad6-ea4a-46ea-9ed3-742f520b5068
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126627596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_csr_rw.126627596
Directory	/workspace/12.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1089535463
Short name	T952
Test name
Test status
Simulation time	3340742614 ps
CPU time	2.47 seconds
Started	Jun 23 06:16:52 PM PDT 24
Finished	Jun 23 06:16:55 PM PDT 24
Peak memory	203116 kb
Host	smart-03271a07-43fb-4338-843a-c3ba746b534d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089535463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1089535463
Directory	/workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1466953159
Short name	T985
Test name
Test status
Simulation time	47493263 ps
CPU time	0.7 seconds
Started	Jun 23 06:16:51 PM PDT 24
Finished	Jun 23 06:16:52 PM PDT 24
Peak memory	202640 kb
Host	smart-22529688-e8c8-4268-8dae-4f87eae9e462
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466953159 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1466953159
Directory	/workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3779067386
Short name	T119
Test name
Test status
Simulation time	138502392 ps
CPU time	4.24 seconds
Started	Jun 23 06:16:51 PM PDT 24
Finished	Jun 23 06:16:55 PM PDT 24
Peak memory	212200 kb
Host	smart-1476acbf-b033-4ab9-90dc-7023c6bedea6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779067386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.3779067386
Directory	/workspace/12.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2582935505
Short name	T128
Test name
Test status
Simulation time	264023095 ps
CPU time	1.42 seconds
Started	Jun 23 06:16:49 PM PDT 24
Finished	Jun 23 06:16:51 PM PDT 24
Peak memory	211136 kb
Host	smart-4a4fa1b5-f9ec-44fe-a515-a644097c68ce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582935505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.2582935505
Directory	/workspace/12.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2359650410
Short name	T117
Test name
Test status
Simulation time	45367478 ps
CPU time	1.16 seconds
Started	Jun 23 06:16:53 PM PDT 24
Finished	Jun 23 06:16:55 PM PDT 24
Peak memory	213732 kb
Host	smart-ef50c2b8-ae94-48d4-ad9c-2f9ed95abfc6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359650410 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2359650410
Directory	/workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2326824481
Short name	T65
Test name
Test status
Simulation time	21616140 ps
CPU time	0.69 seconds
Started	Jun 23 06:16:50 PM PDT 24
Finished	Jun 23 06:16:51 PM PDT 24
Peak memory	202652 kb
Host	smart-4617291e-ddf3-4216-828d-df4a3efac885
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326824481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.2326824481
Directory	/workspace/13.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.617328407
Short name	T1010
Test name
Test status
Simulation time	469198183 ps
CPU time	2.09 seconds
Started	Jun 23 06:16:50 PM PDT 24
Finished	Jun 23 06:16:52 PM PDT 24
Peak memory	202784 kb
Host	smart-1858251a-1197-4e61-82eb-114940b3c80e
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617328407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.617328407
Directory	/workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3570880079
Short name	T1008
Test name
Test status
Simulation time	17148510 ps
CPU time	0.73 seconds
Started	Jun 23 06:16:50 PM PDT 24
Finished	Jun 23 06:16:51 PM PDT 24
Peak memory	202664 kb
Host	smart-f4daa9ac-e512-4909-8401-ea6c5bbab9c1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570880079 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3570880079
Directory	/workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3713975573
Short name	T1018
Test name
Test status
Simulation time	177757065 ps
CPU time	3.96 seconds
Started	Jun 23 06:16:49 PM PDT 24
Finished	Jun 23 06:16:53 PM PDT 24
Peak memory	202928 kb
Host	smart-b8715696-bf65-4a90-8400-98a01c9b0740
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713975573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3713975573
Directory	/workspace/13.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2249723769
Short name	T1000
Test name
Test status
Simulation time	55137005 ps
CPU time	1.37 seconds
Started	Jun 23 06:16:49 PM PDT 24
Finished	Jun 23 06:16:51 PM PDT 24
Peak memory	211192 kb
Host	smart-64eb3ebd-a981-4086-bb0d-cfb80f0d4bae
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249723769 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2249723769
Directory	/workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2169012017
Short name	T950
Test name
Test status
Simulation time	29692798 ps
CPU time	0.64 seconds
Started	Jun 23 06:16:50 PM PDT 24
Finished	Jun 23 06:16:51 PM PDT 24
Peak memory	202640 kb
Host	smart-b97ff562-6e81-4ae0-87c8-7dd6a620d294
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169012017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.2169012017
Directory	/workspace/14.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3916272274
Short name	T77
Test name
Test status
Simulation time	417165789 ps
CPU time	2.41 seconds
Started	Jun 23 06:16:52 PM PDT 24
Finished	Jun 23 06:16:54 PM PDT 24
Peak memory	202848 kb
Host	smart-e61f1a8f-567b-4f5f-828c-a31c5ed34d8c
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916272274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3916272274
Directory	/workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.134172536
Short name	T997
Test name
Test status
Simulation time	19621039 ps
CPU time	0.73 seconds
Started	Jun 23 06:16:50 PM PDT 24
Finished	Jun 23 06:16:51 PM PDT 24
Peak memory	202660 kb
Host	smart-5f035a41-dbc8-48e4-8eee-b380b752b9bd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134172536 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.134172536
Directory	/workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3679376931
Short name	T118
Test name
Test status
Simulation time	81608389 ps
CPU time	2.68 seconds
Started	Jun 23 06:16:52 PM PDT 24
Finished	Jun 23 06:16:55 PM PDT 24
Peak memory	202992 kb
Host	smart-021e5e3e-26c0-4081-921b-cb966f6e8747
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679376931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3679376931
Directory	/workspace/14.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2160985963
Short name	T986
Test name
Test status
Simulation time	14276902 ps
CPU time	0.68 seconds
Started	Jun 23 06:17:02 PM PDT 24
Finished	Jun 23 06:17:03 PM PDT 24
Peak memory	202108 kb
Host	smart-c174ed57-4887-45e9-af1d-28c226a5461b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160985963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.2160985963
Directory	/workspace/15.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3598285495
Short name	T999
Test name
Test status
Simulation time	1688393789 ps
CPU time	3.09 seconds
Started	Jun 23 06:16:51 PM PDT 24
Finished	Jun 23 06:16:54 PM PDT 24
Peak memory	203052 kb
Host	smart-19036a3c-a114-4bbd-b76c-03d969cc9698
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598285495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3598285495
Directory	/workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.315559105
Short name	T951
Test name
Test status
Simulation time	43762875 ps
CPU time	0.88 seconds
Started	Jun 23 06:17:02 PM PDT 24
Finished	Jun 23 06:17:03 PM PDT 24
Peak memory	202596 kb
Host	smart-1f797dcd-a6c3-44c5-ac9e-498018fcaa56
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315559105 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.315559105
Directory	/workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4177681882
Short name	T980
Test name
Test status
Simulation time	438909870 ps
CPU time	3.8 seconds
Started	Jun 23 06:16:51 PM PDT 24
Finished	Jun 23 06:16:55 PM PDT 24
Peak memory	202892 kb
Host	smart-6dddd4c3-5f66-48c8-aafc-72840ee5d1b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177681882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.4177681882
Directory	/workspace/15.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3161622216
Short name	T977
Test name
Test status
Simulation time	99078587 ps
CPU time	1.46 seconds
Started	Jun 23 06:16:56 PM PDT 24
Finished	Jun 23 06:16:58 PM PDT 24
Peak memory	211024 kb
Host	smart-144bef63-f632-49f7-8843-341b7c370219
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161622216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.3161622216
Directory	/workspace/15.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.835612853
Short name	T938
Test name
Test status
Simulation time	134517577 ps
CPU time	1.75 seconds
Started	Jun 23 06:16:54 PM PDT 24
Finished	Jun 23 06:16:56 PM PDT 24
Peak memory	212364 kb
Host	smart-8a3d12be-1ad4-46ce-8e26-3b66149786e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835612853 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.835612853
Directory	/workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2879452207
Short name	T94
Test name
Test status
Simulation time	19718701 ps
CPU time	0.69 seconds
Started	Jun 23 06:16:53 PM PDT 24
Finished	Jun 23 06:16:54 PM PDT 24
Peak memory	202572 kb
Host	smart-6f0d8440-8f60-4da4-9f3b-89010c3bb56b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879452207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.2879452207
Directory	/workspace/16.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1731637607
Short name	T1011
Test name
Test status
Simulation time	39861269 ps
CPU time	0.79 seconds
Started	Jun 23 06:16:58 PM PDT 24
Finished	Jun 23 06:16:59 PM PDT 24
Peak memory	202664 kb
Host	smart-0c59ff37-6877-4b07-9eaa-56ff6c1aa74e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731637607 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.1731637607
Directory	/workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3482146360
Short name	T994
Test name
Test status
Simulation time	137864301 ps
CPU time	2.86 seconds
Started	Jun 23 06:17:02 PM PDT 24
Finished	Jun 23 06:17:06 PM PDT 24
Peak memory	212216 kb
Host	smart-d1173293-bb70-4827-911e-988f3b89d566
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482146360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.3482146360
Directory	/workspace/16.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3526225119
Short name	T987
Test name
Test status
Simulation time	117453653 ps
CPU time	1.45 seconds
Started	Jun 23 06:16:57 PM PDT 24
Finished	Jun 23 06:16:59 PM PDT 24
Peak memory	202892 kb
Host	smart-1f375ad7-4922-4c83-9821-0e4514dbfd68
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526225119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.3526225119
Directory	/workspace/16.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3572401071
Short name	T953
Test name
Test status
Simulation time	42174196 ps
CPU time	1.42 seconds
Started	Jun 23 06:17:02 PM PDT 24
Finished	Jun 23 06:17:05 PM PDT 24
Peak memory	211144 kb
Host	smart-f4df3644-a9c7-49b3-8d17-efffea133d5e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572401071 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3572401071
Directory	/workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.101204226
Short name	T75
Test name
Test status
Simulation time	25215742 ps
CPU time	0.7 seconds
Started	Jun 23 06:17:03 PM PDT 24
Finished	Jun 23 06:17:05 PM PDT 24
Peak memory	202492 kb
Host	smart-c9be2489-5e03-4c9d-8f98-54e26e6e6d3f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101204226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.101204226
Directory	/workspace/17.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3330225558
Short name	T91
Test name
Test status
Simulation time	4065919469 ps
CPU time	3.24 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:58 PM PDT 24
Peak memory	203104 kb
Host	smart-8d21f1c3-14c2-4a2d-88b6-fe5f1c025515
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330225558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3330225558
Directory	/workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3344932548
Short name	T969
Test name
Test status
Simulation time	58684079 ps
CPU time	0.8 seconds
Started	Jun 23 06:17:00 PM PDT 24
Finished	Jun 23 06:17:01 PM PDT 24
Peak memory	202652 kb
Host	smart-3c99303f-527e-499a-b201-1695eb21d32e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344932548 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3344932548
Directory	/workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1105285632
Short name	T942
Test name
Test status
Simulation time	138141944 ps
CPU time	2.57 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:58 PM PDT 24
Peak memory	211372 kb
Host	smart-f02c59d7-65f3-45f0-abd5-61f187f5278e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105285632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.1105285632
Directory	/workspace/17.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2952045175
Short name	T114
Test name
Test status
Simulation time	330041384 ps
CPU time	1.53 seconds
Started	Jun 23 06:17:03 PM PDT 24
Finished	Jun 23 06:17:06 PM PDT 24
Peak memory	202840 kb
Host	smart-094555e9-fbb8-4219-9a07-5f4d548566ef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952045175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.2952045175
Directory	/workspace/17.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3205994360
Short name	T941
Test name
Test status
Simulation time	40203675 ps
CPU time	0.7 seconds
Started	Jun 23 06:16:56 PM PDT 24
Finished	Jun 23 06:16:57 PM PDT 24
Peak memory	202664 kb
Host	smart-d1ea8b59-98e0-4ea8-bb3a-1c9f519a17fd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205994360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.3205994360
Directory	/workspace/18.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.795321175
Short name	T81
Test name
Test status
Simulation time	1720342685 ps
CPU time	3.27 seconds
Started	Jun 23 06:16:58 PM PDT 24
Finished	Jun 23 06:17:01 PM PDT 24
Peak memory	203068 kb
Host	smart-8f47f4fe-2954-4e17-9142-9f4a29cf4dd1
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795321175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.795321175
Directory	/workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.332421268
Short name	T1012
Test name
Test status
Simulation time	68807430 ps
CPU time	0.83 seconds
Started	Jun 23 06:17:02 PM PDT 24
Finished	Jun 23 06:17:03 PM PDT 24
Peak memory	202668 kb
Host	smart-4650bd69-2d02-4c93-8c35-291994e4a973
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332421268 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.332421268
Directory	/workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2189185066
Short name	T975
Test name
Test status
Simulation time	1262639784 ps
CPU time	2.54 seconds
Started	Jun 23 06:16:54 PM PDT 24
Finished	Jun 23 06:16:57 PM PDT 24
Peak memory	202976 kb
Host	smart-70eb24d7-90eb-452e-95b6-a4a41846c7a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189185066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.2189185066
Directory	/workspace/18.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3172671273
Short name	T125
Test name
Test status
Simulation time	686830197 ps
CPU time	2.32 seconds
Started	Jun 23 06:16:53 PM PDT 24
Finished	Jun 23 06:16:56 PM PDT 24
Peak memory	202848 kb
Host	smart-e2d31496-5d8b-44f6-94aa-5cd1b5c9822f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172671273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.3172671273
Directory	/workspace/18.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.301357522
Short name	T946
Test name
Test status
Simulation time	34995418 ps
CPU time	1.56 seconds
Started	Jun 23 06:16:57 PM PDT 24
Finished	Jun 23 06:16:59 PM PDT 24
Peak memory	212132 kb
Host	smart-b4bff261-8497-484f-8928-4c8a94a953d3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301357522 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.301357522
Directory	/workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3395896022
Short name	T981
Test name
Test status
Simulation time	15724879 ps
CPU time	0.67 seconds
Started	Jun 23 06:17:03 PM PDT 24
Finished	Jun 23 06:17:04 PM PDT 24
Peak memory	202648 kb
Host	smart-6ae25178-08d4-4a6c-ac45-f47f6ae71422
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395896022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.3395896022
Directory	/workspace/19.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.310861979
Short name	T85
Test name
Test status
Simulation time	737533768 ps
CPU time	2.14 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:57 PM PDT 24
Peak memory	202796 kb
Host	smart-f0db5de3-4e08-44fa-8aca-49783f338eab
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310861979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.310861979
Directory	/workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3439789551
Short name	T961
Test name
Test status
Simulation time	25143536 ps
CPU time	0.85 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:57 PM PDT 24
Peak memory	202680 kb
Host	smart-6bbebc74-1844-448f-99cf-55e5edd53cc4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439789551 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3439789551
Directory	/workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2614778188
Short name	T939
Test name
Test status
Simulation time	56162988 ps
CPU time	2.18 seconds
Started	Jun 23 06:17:03 PM PDT 24
Finished	Jun 23 06:17:06 PM PDT 24
Peak memory	211088 kb
Host	smart-d378168b-0212-46b1-88d3-85a61f9e768f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614778188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.2614778188
Directory	/workspace/19.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.687977810
Short name	T995
Test name
Test status
Simulation time	81009071 ps
CPU time	1.43 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:56 PM PDT 24
Peak memory	211020 kb
Host	smart-25f4ef30-7d4a-4dff-81f8-93acf8cd127d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687977810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.sram_ctrl_tl_intg_err.687977810
Directory	/workspace/19.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1211519199
Short name	T106
Test name
Test status
Simulation time	16488238 ps
CPU time	0.7 seconds
Started	Jun 23 06:16:36 PM PDT 24
Finished	Jun 23 06:16:38 PM PDT 24
Peak memory	202624 kb
Host	smart-dbb8a618-46d9-40ea-aa32-34cf612938ff
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211519199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.1211519199
Directory	/workspace/2.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1968839071
Short name	T93
Test name
Test status
Simulation time	98300588 ps
CPU time	1.47 seconds
Started	Jun 23 06:16:34 PM PDT 24
Finished	Jun 23 06:16:36 PM PDT 24
Peak memory	202896 kb
Host	smart-1b252c32-68d7-41ae-907b-73c3975aa726
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968839071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.1968839071
Directory	/workspace/2.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4112431105
Short name	T937
Test name
Test status
Simulation time	28309817 ps
CPU time	0.74 seconds
Started	Jun 23 06:16:34 PM PDT 24
Finished	Jun 23 06:16:36 PM PDT 24
Peak memory	202068 kb
Host	smart-f1805672-dbfb-41a3-a496-26062cede80a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112431105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.4112431105
Directory	/workspace/2.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1557767924
Short name	T957
Test name
Test status
Simulation time	93303938 ps
CPU time	1.36 seconds
Started	Jun 23 06:16:34 PM PDT 24
Finished	Jun 23 06:16:36 PM PDT 24
Peak memory	212184 kb
Host	smart-b62a6231-edb6-4361-8a13-837e6a426d01
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557767924 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1557767924
Directory	/workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4045454284
Short name	T1009
Test name
Test status
Simulation time	41947068 ps
CPU time	0.67 seconds
Started	Jun 23 06:16:34 PM PDT 24
Finished	Jun 23 06:16:35 PM PDT 24
Peak memory	202360 kb
Host	smart-306bfccb-0735-4373-84a2-991de9ff6df7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045454284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.4045454284
Directory	/workspace/2.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3235203096
Short name	T78
Test name
Test status
Simulation time	242224555 ps
CPU time	1.94 seconds
Started	Jun 23 06:16:35 PM PDT 24
Finished	Jun 23 06:16:38 PM PDT 24
Peak memory	202752 kb
Host	smart-5515ee14-d0db-4f58-b2ba-0d3bf4aa54da
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235203096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3235203096
Directory	/workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3339433569
Short name	T97
Test name
Test status
Simulation time	25816063 ps
CPU time	0.74 seconds
Started	Jun 23 06:16:36 PM PDT 24
Finished	Jun 23 06:16:38 PM PDT 24
Peak memory	202660 kb
Host	smart-377a41af-a522-4c69-81c0-ba65b969d538
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339433569 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3339433569
Directory	/workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2884350012
Short name	T945
Test name
Test status
Simulation time	548471249 ps
CPU time	4.73 seconds
Started	Jun 23 06:16:34 PM PDT 24
Finished	Jun 23 06:16:39 PM PDT 24
Peak memory	211112 kb
Host	smart-6159128b-8197-4b37-9e6a-8ec6feabc4e9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884350012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.2884350012
Directory	/workspace/2.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3414321475
Short name	T127
Test name
Test status
Simulation time	283828384 ps
CPU time	2.2 seconds
Started	Jun 23 06:16:36 PM PDT 24
Finished	Jun 23 06:16:39 PM PDT 24
Peak memory	211056 kb
Host	smart-1c38714b-f52f-423f-9a89-68ae3f4282e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414321475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.3414321475
Directory	/workspace/2.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.409579896
Short name	T968
Test name
Test status
Simulation time	21313380 ps
CPU time	0.7 seconds
Started	Jun 23 06:16:37 PM PDT 24
Finished	Jun 23 06:16:38 PM PDT 24
Peak memory	202624 kb
Host	smart-a56f8104-c751-46e6-be0c-bb10c58072fb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409579896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.409579896
Directory	/workspace/3.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1589516429
Short name	T73
Test name
Test status
Simulation time	27097740 ps
CPU time	1.28 seconds
Started	Jun 23 06:16:35 PM PDT 24
Finished	Jun 23 06:16:37 PM PDT 24
Peak memory	202860 kb
Host	smart-501b6027-920f-4900-ad27-581240d58151
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589516429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.1589516429
Directory	/workspace/3.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1344092862
Short name	T66
Test name
Test status
Simulation time	138083535 ps
CPU time	0.72 seconds
Started	Jun 23 06:16:36 PM PDT 24
Finished	Jun 23 06:16:38 PM PDT 24
Peak memory	202152 kb
Host	smart-525872e0-8fcf-4512-9a10-d498281036b2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344092862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1344092862
Directory	/workspace/3.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.731735040
Short name	T996
Test name
Test status
Simulation time	32332863 ps
CPU time	0.64 seconds
Started	Jun 23 06:16:32 PM PDT 24
Finished	Jun 23 06:16:33 PM PDT 24
Peak memory	202636 kb
Host	smart-cdedcdb6-f07f-4b19-9494-f157cec014d6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731735040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.sram_ctrl_csr_rw.731735040
Directory	/workspace/3.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3115489515
Short name	T82
Test name
Test status
Simulation time	221240566 ps
CPU time	2.05 seconds
Started	Jun 23 06:16:38 PM PDT 24
Finished	Jun 23 06:16:41 PM PDT 24
Peak memory	202804 kb
Host	smart-b5021cb5-8053-441f-82ed-d25899b216fe
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115489515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3115489515
Directory	/workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2035342625
Short name	T1003
Test name
Test status
Simulation time	35555099 ps
CPU time	0.79 seconds
Started	Jun 23 06:16:34 PM PDT 24
Finished	Jun 23 06:16:35 PM PDT 24
Peak memory	202640 kb
Host	smart-7efae86b-6196-4b92-8cae-73e875fd3301
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035342625 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2035342625
Directory	/workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1700290280
Short name	T955
Test name
Test status
Simulation time	413350863 ps
CPU time	3.79 seconds
Started	Jun 23 06:16:37 PM PDT 24
Finished	Jun 23 06:16:42 PM PDT 24
Peak memory	211096 kb
Host	smart-dd2df1e2-0b84-4837-887d-62c8a81f9d3a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700290280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.1700290280
Directory	/workspace/3.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1543152637
Short name	T122
Test name
Test status
Simulation time	103815965 ps
CPU time	1.62 seconds
Started	Jun 23 06:16:34 PM PDT 24
Finished	Jun 23 06:16:36 PM PDT 24
Peak memory	202932 kb
Host	smart-917895be-b79b-4697-acf0-17f2ec0136c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543152637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.1543152637
Directory	/workspace/3.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4204479346
Short name	T992
Test name
Test status
Simulation time	47452658 ps
CPU time	0.7 seconds
Started	Jun 23 06:16:39 PM PDT 24
Finished	Jun 23 06:16:40 PM PDT 24
Peak memory	202592 kb
Host	smart-3bbd0f39-4b63-4557-8264-672174346c6d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204479346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.4204479346
Directory	/workspace/4.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.817366915
Short name	T964
Test name
Test status
Simulation time	175127450 ps
CPU time	1.97 seconds
Started	Jun 23 06:16:42 PM PDT 24
Finished	Jun 23 06:16:44 PM PDT 24
Peak memory	202892 kb
Host	smart-46f16ae9-1bae-482d-9af7-17091fbddc96
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817366915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_bash.817366915
Directory	/workspace/4.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1122077873
Short name	T954
Test name
Test status
Simulation time	19864876 ps
CPU time	0.68 seconds
Started	Jun 23 06:16:37 PM PDT 24
Finished	Jun 23 06:16:38 PM PDT 24
Peak memory	202632 kb
Host	smart-99379167-3b2f-4b74-8a86-db3b0bd98829
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122077873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.1122077873
Directory	/workspace/4.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2303450971
Short name	T1005
Test name
Test status
Simulation time	169842353 ps
CPU time	2.98 seconds
Started	Jun 23 06:16:41 PM PDT 24
Finished	Jun 23 06:16:45 PM PDT 24
Peak memory	212632 kb
Host	smart-0d089295-a252-41cd-afc4-4f3dce70cc8e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303450971 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2303450971
Directory	/workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1734771191
Short name	T983
Test name
Test status
Simulation time	15432093 ps
CPU time	0.71 seconds
Started	Jun 23 06:16:45 PM PDT 24
Finished	Jun 23 06:16:47 PM PDT 24
Peak memory	202616 kb
Host	smart-58ea782a-e76b-4071-b4c7-f88276500fe3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734771191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.1734771191
Directory	/workspace/4.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1479642261
Short name	T1017
Test name
Test status
Simulation time	548897101 ps
CPU time	3.39 seconds
Started	Jun 23 06:16:38 PM PDT 24
Finished	Jun 23 06:16:42 PM PDT 24
Peak memory	203060 kb
Host	smart-ee1cf598-d0b3-432b-82cd-d408b940de4c
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479642261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1479642261
Directory	/workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1965226491
Short name	T1007
Test name
Test status
Simulation time	24882239 ps
CPU time	0.7 seconds
Started	Jun 23 06:16:46 PM PDT 24
Finished	Jun 23 06:16:47 PM PDT 24
Peak memory	202640 kb
Host	smart-cfe0f06b-45ca-4f09-b12e-36519d61faf3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965226491 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1965226491
Directory	/workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2701231573
Short name	T1015
Test name
Test status
Simulation time	503890854 ps
CPU time	4.34 seconds
Started	Jun 23 06:16:39 PM PDT 24
Finished	Jun 23 06:16:44 PM PDT 24
Peak memory	211132 kb
Host	smart-9548efce-73fe-40a1-8622-cebeba10144b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701231573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.2701231573
Directory	/workspace/4.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.246456697
Short name	T982
Test name
Test status
Simulation time	299368471 ps
CPU time	1.39 seconds
Started	Jun 23 06:16:40 PM PDT 24
Finished	Jun 23 06:16:42 PM PDT 24
Peak memory	202916 kb
Host	smart-13f414c0-e49f-469c-aa0f-1ecb9ceca716
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246456697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.sram_ctrl_tl_intg_err.246456697
Directory	/workspace/4.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2014039019
Short name	T948
Test name
Test status
Simulation time	23146920 ps
CPU time	0.65 seconds
Started	Jun 23 06:16:44 PM PDT 24
Finished	Jun 23 06:16:45 PM PDT 24
Peak memory	202636 kb
Host	smart-1718d8ea-2494-465d-bc24-7720d8cd07de
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014039019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.2014039019
Directory	/workspace/5.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1356517448
Short name	T967
Test name
Test status
Simulation time	1404632142 ps
CPU time	3.38 seconds
Started	Jun 23 06:16:39 PM PDT 24
Finished	Jun 23 06:16:43 PM PDT 24
Peak memory	203044 kb
Host	smart-f3d9ced4-93cf-4e19-a149-6988cab483ef
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356517448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.1356517448
Directory	/workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1921887930
Short name	T1004
Test name
Test status
Simulation time	32763962 ps
CPU time	0.74 seconds
Started	Jun 23 06:16:39 PM PDT 24
Finished	Jun 23 06:16:40 PM PDT 24
Peak memory	202604 kb
Host	smart-a950c425-33b5-404e-8f33-abc0d3889bb1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921887930 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1921887930
Directory	/workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.195320632
Short name	T972
Test name
Test status
Simulation time	180274931 ps
CPU time	4.08 seconds
Started	Jun 23 06:16:46 PM PDT 24
Finished	Jun 23 06:16:51 PM PDT 24
Peak memory	211104 kb
Host	smart-3cd46f0b-4578-43f8-b4a4-2a5240e0116b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195320632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.195320632
Directory	/workspace/5.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2628637048
Short name	T1001
Test name
Test status
Simulation time	296706698 ps
CPU time	1.5 seconds
Started	Jun 23 06:16:38 PM PDT 24
Finished	Jun 23 06:16:40 PM PDT 24
Peak memory	211076 kb
Host	smart-7ff19c87-ba99-446a-952f-c16fb64865d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628637048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.2628637048
Directory	/workspace/5.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.181944860
Short name	T970
Test name
Test status
Simulation time	79631548 ps
CPU time	2.58 seconds
Started	Jun 23 06:16:39 PM PDT 24
Finished	Jun 23 06:16:42 PM PDT 24
Peak memory	211208 kb
Host	smart-84ba8964-daff-49b9-bb44-4ca69b7c01a4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181944860 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.181944860
Directory	/workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.39963203
Short name	T105
Test name
Test status
Simulation time	40292242 ps
CPU time	0.71 seconds
Started	Jun 23 06:16:38 PM PDT 24
Finished	Jun 23 06:16:39 PM PDT 24
Peak memory	202616 kb
Host	smart-072487b1-be09-4e31-9f43-47f1c4a387db
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 6.sram_ctrl_csr_rw.39963203
Directory	/workspace/6.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2626909995
Short name	T978
Test name
Test status
Simulation time	206784310 ps
CPU time	2 seconds
Started	Jun 23 06:16:45 PM PDT 24
Finished	Jun 23 06:16:48 PM PDT 24
Peak memory	202860 kb
Host	smart-48164028-e6ab-4dba-b695-016905fa5aff
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626909995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2626909995
Directory	/workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1775820363
Short name	T988
Test name
Test status
Simulation time	25290220 ps
CPU time	0.8 seconds
Started	Jun 23 06:16:46 PM PDT 24
Finished	Jun 23 06:16:47 PM PDT 24
Peak memory	202580 kb
Host	smart-44147501-cbcb-42b5-9964-fa27d6d2b201
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775820363 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1775820363
Directory	/workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2631776658
Short name	T935
Test name
Test status
Simulation time	134711382 ps
CPU time	2.37 seconds
Started	Jun 23 06:16:45 PM PDT 24
Finished	Jun 23 06:16:49 PM PDT 24
Peak memory	211108 kb
Host	smart-ecc1be85-6229-499e-b457-8f72b738d72a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631776658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.2631776658
Directory	/workspace/6.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1188314912
Short name	T123
Test name
Test status
Simulation time	105255745 ps
CPU time	1.52 seconds
Started	Jun 23 06:16:39 PM PDT 24
Finished	Jun 23 06:16:41 PM PDT 24
Peak memory	211132 kb
Host	smart-10b2fa91-5abb-4b7a-b7b5-f8c7de6968dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188314912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1188314912
Directory	/workspace/6.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.155447871
Short name	T943
Test name
Test status
Simulation time	38788257 ps
CPU time	0.69 seconds
Started	Jun 23 06:16:45 PM PDT 24
Finished	Jun 23 06:16:47 PM PDT 24
Peak memory	202576 kb
Host	smart-8b256391-bc9f-4d52-9332-24e9acb7f90a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155447871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_csr_rw.155447871
Directory	/workspace/7.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3135341658
Short name	T79
Test name
Test status
Simulation time	1513965205 ps
CPU time	3.07 seconds
Started	Jun 23 06:16:41 PM PDT 24
Finished	Jun 23 06:16:45 PM PDT 24
Peak memory	203056 kb
Host	smart-a1e2359f-ba5f-49fd-a408-4a02540a636a
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135341658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3135341658
Directory	/workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2215660402
Short name	T95
Test name
Test status
Simulation time	23192871 ps
CPU time	0.76 seconds
Started	Jun 23 06:16:45 PM PDT 24
Finished	Jun 23 06:16:47 PM PDT 24
Peak memory	202632 kb
Host	smart-dc629618-978a-402a-b1a9-16474f744e03
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215660402 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.2215660402
Directory	/workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3754483900
Short name	T1006
Test name
Test status
Simulation time	148081903 ps
CPU time	5.05 seconds
Started	Jun 23 06:16:46 PM PDT 24
Finished	Jun 23 06:16:52 PM PDT 24
Peak memory	212200 kb
Host	smart-6d2694de-1c44-4f5c-b183-dc8207e06aa5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754483900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.3754483900
Directory	/workspace/7.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.589527488
Short name	T979
Test name
Test status
Simulation time	176863731 ps
CPU time	1.47 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:57 PM PDT 24
Peak memory	202808 kb
Host	smart-0c7285b6-e70f-4e88-b5fc-d8e8044f96a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589527488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.sram_ctrl_tl_intg_err.589527488
Directory	/workspace/7.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.392642107
Short name	T1013
Test name
Test status
Simulation time	25971147 ps
CPU time	0.96 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:57 PM PDT 24
Peak memory	210848 kb
Host	smart-e2560a98-d964-41aa-b7d5-61f4b669f158
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392642107 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.392642107
Directory	/workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.282997256
Short name	T74
Test name
Test status
Simulation time	41948014 ps
CPU time	0.7 seconds
Started	Jun 23 06:16:47 PM PDT 24
Finished	Jun 23 06:16:49 PM PDT 24
Peak memory	202688 kb
Host	smart-135b09f5-f9b2-41bb-b4d7-734c2d0b9bda
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282997256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_csr_rw.282997256
Directory	/workspace/8.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3795053777
Short name	T990
Test name
Test status
Simulation time	462466036 ps
CPU time	3.23 seconds
Started	Jun 23 06:16:55 PM PDT 24
Finished	Jun 23 06:16:59 PM PDT 24
Peak memory	203004 kb
Host	smart-fa4bd7ef-5148-4401-8e14-4785d03ae655
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795053777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3795053777
Directory	/workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2465432831
Short name	T998
Test name
Test status
Simulation time	27697792 ps
CPU time	0.76 seconds
Started	Jun 23 06:16:45 PM PDT 24
Finished	Jun 23 06:16:47 PM PDT 24
Peak memory	202652 kb
Host	smart-71265b46-2472-474a-8931-99429a8b512a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465432831 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2465432831
Directory	/workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.527631194
Short name	T973
Test name
Test status
Simulation time	539553907 ps
CPU time	4.82 seconds
Started	Jun 23 06:16:45 PM PDT 24
Finished	Jun 23 06:16:51 PM PDT 24
Peak memory	211120 kb
Host	smart-766c11ad-8b2d-41fe-a119-b92f594e9335
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527631194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.527631194
Directory	/workspace/8.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4009684105
Short name	T62
Test name
Test status
Simulation time	146490962 ps
CPU time	1.76 seconds
Started	Jun 23 06:16:47 PM PDT 24
Finished	Jun 23 06:16:50 PM PDT 24
Peak memory	211104 kb
Host	smart-2b2bfff9-8090-4421-b571-e520c7ec8d88
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009684105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.4009684105
Directory	/workspace/8.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2835210782
Short name	T949
Test name
Test status
Simulation time	12615391 ps
CPU time	0.72 seconds
Started	Jun 23 06:16:47 PM PDT 24
Finished	Jun 23 06:16:49 PM PDT 24
Peak memory	202660 kb
Host	smart-7a155a3f-cf15-43b7-9f99-2a1fbdbdb78a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835210782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.2835210782
Directory	/workspace/9.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.833018027
Short name	T1014
Test name
Test status
Simulation time	460948097 ps
CPU time	3.09 seconds
Started	Jun 23 06:16:44 PM PDT 24
Finished	Jun 23 06:16:48 PM PDT 24
Peak memory	203036 kb
Host	smart-7b522da2-17c3-4ff8-acd6-7c9854762698
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833018027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.833018027
Directory	/workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1169446944
Short name	T962
Test name
Test status
Simulation time	64993920 ps
CPU time	0.76 seconds
Started	Jun 23 06:16:45 PM PDT 24
Finished	Jun 23 06:16:47 PM PDT 24
Peak memory	202632 kb
Host	smart-0ce7d496-d6a4-4fd4-baa4-8f2fd8a451e6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169446944 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1169446944
Directory	/workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.195900277
Short name	T956
Test name
Test status
Simulation time	124986416 ps
CPU time	2.42 seconds
Started	Jun 23 06:16:44 PM PDT 24
Finished	Jun 23 06:16:46 PM PDT 24
Peak memory	202932 kb
Host	smart-8939b4f1-949b-4d68-8471-2e2a34dd4139
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195900277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.195900277
Directory	/workspace/9.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2675542000
Short name	T126
Test name
Test status
Simulation time	182017328 ps
CPU time	1.42 seconds
Started	Jun 23 06:16:45 PM PDT 24
Finished	Jun 23 06:16:48 PM PDT 24
Peak memory	211056 kb
Host	smart-18ed21bd-772e-4db4-bce9-581c5df586df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675542000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.2675542000
Directory	/workspace/9.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1035410404
Short name	T86
Test name
Test status
Simulation time	4121297837 ps
CPU time	227.35 seconds
Started	Jun 23 06:24:20 PM PDT 24
Finished	Jun 23 06:28:08 PM PDT 24
Peak memory	376792 kb
Host	smart-d0dd041c-983e-41e5-b65c-46e16edd91e3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035410404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.1035410404
Directory	/workspace/0.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/0.sram_ctrl_alert_test.1172404066
Short name	T457
Test name
Test status
Simulation time	14805436 ps
CPU time	0.67 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:24:31 PM PDT 24
Peak memory	202940 kb
Host	smart-027534a9-ad28-426e-8ca4-ccc66462a49d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172404066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1172404066
Directory	/workspace/0.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.sram_ctrl_bijection.2753223980
Short name	T187
Test name
Test status
Simulation time	6347590018 ps
CPU time	32.87 seconds
Started	Jun 23 06:24:21 PM PDT 24
Finished	Jun 23 06:24:54 PM PDT 24
Peak memory	203120 kb
Host	smart-bc08d7e7-2785-4195-8d12-e40d411eb6ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753223980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 2753223980
Directory	/workspace/0.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/0.sram_ctrl_executable.1918357346
Short name	T227
Test name
Test status
Simulation time	6273039535 ps
CPU time	941.42 seconds
Started	Jun 23 06:24:22 PM PDT 24
Finished	Jun 23 06:40:04 PM PDT 24
Peak memory	373928 kb
Host	smart-a83e0aaa-5d53-4a05-94e2-7c346347ae8e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918357346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.1918357346
Directory	/workspace/0.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/0.sram_ctrl_lc_escalation.385759104
Short name	T590
Test name
Test status
Simulation time	832575557 ps
CPU time	2.69 seconds
Started	Jun 23 06:24:22 PM PDT 24
Finished	Jun 23 06:24:25 PM PDT 24
Peak memory	203144 kb
Host	smart-c72e2800-40c1-4a4a-9812-4e18e5191773
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385759104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca lation.385759104
Directory	/workspace/0.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/0.sram_ctrl_max_throughput.1819204169
Short name	T874
Test name
Test status
Simulation time	100226626 ps
CPU time	50.55 seconds
Started	Jun 23 06:24:22 PM PDT 24
Finished	Jun 23 06:25:12 PM PDT 24
Peak memory	304376 kb
Host	smart-25b84aaa-8719-4b2f-9d91-a213fe0d1b66
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819204169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.1819204169
Directory	/workspace/0.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_partial_access.827318999
Short name	T701
Test name
Test status
Simulation time	182979944 ps
CPU time	4.95 seconds
Started	Jun 23 06:24:25 PM PDT 24
Finished	Jun 23 06:24:30 PM PDT 24
Peak memory	211312 kb
Host	smart-47bc587c-0297-402b-b004-fd4f2c127ea7
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827318999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_mem_partial_access.827318999
Directory	/workspace/0.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_walk.390387050
Short name	T818
Test name
Test status
Simulation time	506323659 ps
CPU time	10.4 seconds
Started	Jun 23 06:24:27 PM PDT 24
Finished	Jun 23 06:24:37 PM PDT 24
Peak memory	211284 kb
Host	smart-bf14d04f-1508-43da-9ac9-40153ca0e974
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390387050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ mem_walk.390387050
Directory	/workspace/0.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/0.sram_ctrl_multiple_keys.33181555
Short name	T687
Test name
Test status
Simulation time	1342139400 ps
CPU time	35.75 seconds
Started	Jun 23 06:24:25 PM PDT 24
Finished	Jun 23 06:25:01 PM PDT 24
Peak memory	297312 kb
Host	smart-306c8823-62c7-4aa7-bdc2-602589d80092
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33181555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple _keys.33181555
Directory	/workspace/0.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access.3931380494
Short name	T280
Test name
Test status
Simulation time	803560122 ps
CPU time	10.53 seconds
Started	Jun 23 06:24:21 PM PDT 24
Finished	Jun 23 06:24:32 PM PDT 24
Peak memory	203140 kb
Host	smart-2eabb95e-b013-4cf2-8c8e-7cda8c161d8c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931380494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.3931380494
Directory	/workspace/0.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.253638603
Short name	T471
Test name
Test status
Simulation time	6825445903 ps
CPU time	421.98 seconds
Started	Jun 23 06:24:20 PM PDT 24
Finished	Jun 23 06:31:22 PM PDT 24
Peak memory	203156 kb
Host	smart-580320ba-da86-444c-b1d1-6f872b57e21d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253638603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.sram_ctrl_partial_access_b2b.253638603
Directory	/workspace/0.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/0.sram_ctrl_ram_cfg.1106151466
Short name	T366
Test name
Test status
Simulation time	36149750 ps
CPU time	0.78 seconds
Started	Jun 23 06:24:27 PM PDT 24
Finished	Jun 23 06:24:29 PM PDT 24
Peak memory	203108 kb
Host	smart-c37da2f1-ef84-41f9-ada6-70ede534e7f8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106151466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1106151466
Directory	/workspace/0.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/0.sram_ctrl_smoke.1555424567
Short name	T777
Test name
Test status
Simulation time	556765522 ps
CPU time	58.88 seconds
Started	Jun 23 06:24:25 PM PDT 24
Finished	Jun 23 06:25:24 PM PDT 24
Peak memory	309980 kb
Host	smart-b3cf32ee-1e58-4957-98f4-509709d79e62
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555424567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1555424567
Directory	/workspace/0.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all.3954062111
Short name	T879
Test name
Test status
Simulation time	4337066124 ps
CPU time	886.44 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:39:18 PM PDT 24
Peak memory	369708 kb
Host	smart-eed8b81c-ab8a-4b2d-a507-c33ad8554cc9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954062111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.3954062111
Directory	/workspace/0.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.531802449
Short name	T490
Test name
Test status
Simulation time	2050004993 ps
CPU time	649.64 seconds
Started	Jun 23 06:24:31 PM PDT 24
Finished	Jun 23 06:35:22 PM PDT 24
Peak memory	377056 kb
Host	smart-5f83eefc-6285-4d21-ac37-1d7f73d3c944
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=531802449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.531802449
Directory	/workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2989255727
Short name	T563
Test name
Test status
Simulation time	2857678040 ps
CPU time	261.09 seconds
Started	Jun 23 06:24:21 PM PDT 24
Finished	Jun 23 06:28:42 PM PDT 24
Peak memory	203156 kb
Host	smart-12611c10-fac1-4485-88e2-b8da3c3e642f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989255727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.2989255727
Directory	/workspace/0.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.371328217
Short name	T528
Test name
Test status
Simulation time	98659958 ps
CPU time	18.48 seconds
Started	Jun 23 06:24:25 PM PDT 24
Finished	Jun 23 06:24:44 PM PDT 24
Peak memory	271612 kb
Host	smart-6bf7c699-a5bf-40f9-83e8-5d8aa7471d25
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371328217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_throughput_w_partial_write.371328217
Directory	/workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1628065172
Short name	T892
Test name
Test status
Simulation time	3659960879 ps
CPU time	416.72 seconds
Started	Jun 23 06:24:29 PM PDT 24
Finished	Jun 23 06:31:26 PM PDT 24
Peak memory	373532 kb
Host	smart-d05b5224-059a-45f2-9b0b-6af09c99e35c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628065172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.1628065172
Directory	/workspace/1.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/1.sram_ctrl_alert_test.4150988075
Short name	T347
Test name
Test status
Simulation time	16472526 ps
CPU time	0.64 seconds
Started	Jun 23 06:24:31 PM PDT 24
Finished	Jun 23 06:24:32 PM PDT 24
Peak memory	202912 kb
Host	smart-c97d30ac-5721-4e46-8bb9-98f40e83755a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150988075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.4150988075
Directory	/workspace/1.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.sram_ctrl_bijection.2626440887
Short name	T915
Test name
Test status
Simulation time	1107936951 ps
CPU time	18.7 seconds
Started	Jun 23 06:24:27 PM PDT 24
Finished	Jun 23 06:24:46 PM PDT 24
Peak memory	203056 kb
Host	smart-8a8c5b4d-d025-40e3-a783-1cb121faefc7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626440887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 2626440887
Directory	/workspace/1.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/1.sram_ctrl_executable.2845909933
Short name	T543
Test name
Test status
Simulation time	8338546085 ps
CPU time	1015.03 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:41:26 PM PDT 24
Peak memory	375848 kb
Host	smart-c482a185-0a23-4785-8ebb-be4f222cd3fb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845909933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.2845909933
Directory	/workspace/1.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/1.sram_ctrl_max_throughput.3740252283
Short name	T933
Test name
Test status
Simulation time	726853279 ps
CPU time	46.25 seconds
Started	Jun 23 06:24:27 PM PDT 24
Finished	Jun 23 06:25:13 PM PDT 24
Peak memory	295304 kb
Host	smart-16f7bc8e-a7f9-4e49-9592-12afb7559e61
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740252283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.3740252283
Directory	/workspace/1.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3789582949
Short name	T237
Test name
Test status
Simulation time	46249199 ps
CPU time	2.6 seconds
Started	Jun 23 06:24:31 PM PDT 24
Finished	Jun 23 06:24:35 PM PDT 24
Peak memory	211320 kb
Host	smart-950a13a4-fd59-4752-8c6b-941f598786f3
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789582949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.3789582949
Directory	/workspace/1.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_walk.502475284
Short name	T54
Test name
Test status
Simulation time	496455986 ps
CPU time	6.12 seconds
Started	Jun 23 06:24:24 PM PDT 24
Finished	Jun 23 06:24:31 PM PDT 24
Peak memory	211256 kb
Host	smart-34944991-c67f-4d3d-b55d-87262470a0e8
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502475284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ mem_walk.502475284
Directory	/workspace/1.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/1.sram_ctrl_multiple_keys.178222703
Short name	T147
Test name
Test status
Simulation time	7214269879 ps
CPU time	681.89 seconds
Started	Jun 23 06:24:28 PM PDT 24
Finished	Jun 23 06:35:50 PM PDT 24
Peak memory	368728 kb
Host	smart-7cd0e8e1-8f23-4430-84f3-a79ff9c376b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178222703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multipl e_keys.178222703
Directory	/workspace/1.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access.2966545728
Short name	T611
Test name
Test status
Simulation time	162014572 ps
CPU time	42.44 seconds
Started	Jun 23 06:24:26 PM PDT 24
Finished	Jun 23 06:25:09 PM PDT 24
Peak memory	300988 kb
Host	smart-28ea0fcc-995a-4c19-954b-712c6fb98845
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966545728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.2966545728
Directory	/workspace/1.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.96806934
Short name	T214
Test name
Test status
Simulation time	1964787472 ps
CPU time	146.92 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:26:58 PM PDT 24
Peak memory	202968 kb
Host	smart-273c5992-b796-4f61-86bc-24f253fec2b0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96806934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_partial_access_b2b.96806934
Directory	/workspace/1.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/1.sram_ctrl_regwen.4066869039
Short name	T704
Test name
Test status
Simulation time	2572926310 ps
CPU time	859.91 seconds
Started	Jun 23 06:24:31 PM PDT 24
Finished	Jun 23 06:38:52 PM PDT 24
Peak memory	372316 kb
Host	smart-d9b3b049-09b0-468b-9e20-173db5c2c0c8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066869039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.4066869039
Directory	/workspace/1.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/1.sram_ctrl_sec_cm.3436319499
Short name	T17
Test name
Test status
Simulation time	220019581 ps
CPU time	1.78 seconds
Started	Jun 23 06:24:31 PM PDT 24
Finished	Jun 23 06:24:34 PM PDT 24
Peak memory	221872 kb
Host	smart-6c561eb0-7bbd-4534-9b38-a337c118e932
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436319499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3436319499
Directory	/workspace/1.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.sram_ctrl_smoke.2192133103
Short name	T918
Test name
Test status
Simulation time	846507802 ps
CPU time	14.46 seconds
Started	Jun 23 06:24:24 PM PDT 24
Finished	Jun 23 06:24:39 PM PDT 24
Peak memory	203032 kb
Host	smart-e539ad4a-8c19-4784-b9e5-ec643f0157ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192133103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2192133103
Directory	/workspace/1.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all.1781132032
Short name	T898
Test name
Test status
Simulation time	179519713860 ps
CPU time	4623.96 seconds
Started	Jun 23 06:24:32 PM PDT 24
Finished	Jun 23 07:41:37 PM PDT 24
Peak memory	377052 kb
Host	smart-89e4f747-6b25-4f19-bf9f-7535944865a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781132032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.1781132032
Directory	/workspace/1.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3940407782
Short name	T107
Test name
Test status
Simulation time	638269223 ps
CPU time	10.62 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:24:42 PM PDT 24
Peak memory	219456 kb
Host	smart-cc9b9628-0cca-4daa-a67f-fda2b2e7df29
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3940407782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3940407782
Directory	/workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1187643480
Short name	T548
Test name
Test status
Simulation time	12972908093 ps
CPU time	324.96 seconds
Started	Jun 23 06:24:28 PM PDT 24
Finished	Jun 23 06:29:54 PM PDT 24
Peak memory	203032 kb
Host	smart-5538c809-72b0-46ac-a80d-f3e20ac21322
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187643480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1187643480
Directory	/workspace/1.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.323668537
Short name	T170
Test name
Test status
Simulation time	38434689 ps
CPU time	1.07 seconds
Started	Jun 23 06:24:25 PM PDT 24
Finished	Jun 23 06:24:27 PM PDT 24
Peak memory	202868 kb
Host	smart-5ee3793a-040f-44a1-b87f-4f0c58b1188d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323668537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.323668537
Directory	/workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3610215746
Short name	T691
Test name
Test status
Simulation time	4452082837 ps
CPU time	2807.8 seconds
Started	Jun 23 06:25:15 PM PDT 24
Finished	Jun 23 07:12:04 PM PDT 24
Peak memory	374944 kb
Host	smart-b4c7ca0e-d855-44ef-8174-14b807d140e4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610215746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.3610215746
Directory	/workspace/10.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/10.sram_ctrl_alert_test.3928118321
Short name	T846
Test name
Test status
Simulation time	42233556 ps
CPU time	0.66 seconds
Started	Jun 23 06:25:16 PM PDT 24
Finished	Jun 23 06:25:17 PM PDT 24
Peak memory	202940 kb
Host	smart-15c18446-46d5-4085-b3fd-99a0179bdbaf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928118321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3928118321
Directory	/workspace/10.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.sram_ctrl_bijection.2618979848
Short name	T517
Test name
Test status
Simulation time	27894347171 ps
CPU time	80.9 seconds
Started	Jun 23 06:25:06 PM PDT 24
Finished	Jun 23 06:26:27 PM PDT 24
Peak memory	203132 kb
Host	smart-a3ccaa67-74e2-427e-8922-9facffdfb781
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618979848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .2618979848
Directory	/workspace/10.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/10.sram_ctrl_executable.643897417
Short name	T928
Test name
Test status
Simulation time	21409868120 ps
CPU time	1625.98 seconds
Started	Jun 23 06:25:16 PM PDT 24
Finished	Jun 23 06:52:23 PM PDT 24
Peak memory	375292 kb
Host	smart-d72f7a79-c5e1-4a6e-99eb-4b476b23d2dc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643897417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl e.643897417
Directory	/workspace/10.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/10.sram_ctrl_lc_escalation.1966057422
Short name	T578
Test name
Test status
Simulation time	1635252528 ps
CPU time	4.89 seconds
Started	Jun 23 06:25:11 PM PDT 24
Finished	Jun 23 06:25:16 PM PDT 24
Peak memory	211300 kb
Host	smart-9c8d4d4e-2594-4654-8ffd-e55faefbf524
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966057422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.1966057422
Directory	/workspace/10.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/10.sram_ctrl_max_throughput.821785165
Short name	T279
Test name
Test status
Simulation time	702931673 ps
CPU time	132.94 seconds
Started	Jun 23 06:25:13 PM PDT 24
Finished	Jun 23 06:27:26 PM PDT 24
Peak memory	367396 kb
Host	smart-2f6d75b4-a1ab-4aeb-87ff-ca911c6a4d5c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821785165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.sram_ctrl_max_throughput.821785165
Directory	/workspace/10.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3675771478
Short name	T436
Test name
Test status
Simulation time	340187336 ps
CPU time	5.02 seconds
Started	Jun 23 06:25:15 PM PDT 24
Finished	Jun 23 06:25:20 PM PDT 24
Peak memory	211276 kb
Host	smart-5f959e1b-fb2c-400a-bc42-ac868c8f23a1
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675771478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.3675771478
Directory	/workspace/10.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_walk.1858418014
Short name	T424
Test name
Test status
Simulation time	1829581018 ps
CPU time	10 seconds
Started	Jun 23 06:25:12 PM PDT 24
Finished	Jun 23 06:25:23 PM PDT 24
Peak memory	211248 kb
Host	smart-0e196800-f85b-4b9c-915c-605cedf07319
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858418014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.1858418014
Directory	/workspace/10.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/10.sram_ctrl_multiple_keys.28845329
Short name	T356
Test name
Test status
Simulation time	235225095344 ps
CPU time	1294.39 seconds
Started	Jun 23 06:25:08 PM PDT 24
Finished	Jun 23 06:46:43 PM PDT 24
Peak memory	364716 kb
Host	smart-20922247-4c48-4de7-9796-5136b95e8de9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28845329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multipl e_keys.28845329
Directory	/workspace/10.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access.3047609332
Short name	T647
Test name
Test status
Simulation time	589429032 ps
CPU time	76.71 seconds
Started	Jun 23 06:25:07 PM PDT 24
Finished	Jun 23 06:26:24 PM PDT 24
Peak memory	317496 kb
Host	smart-e4925681-f85a-4f89-851e-5ed9c39e5780
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047609332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.3047609332
Directory	/workspace/10.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3387405942
Short name	T1
Test name
Test status
Simulation time	41216774740 ps
CPU time	409.63 seconds
Started	Jun 23 06:25:09 PM PDT 24
Finished	Jun 23 06:31:59 PM PDT 24
Peak memory	203200 kb
Host	smart-64e89ea2-b484-4ea7-a7e3-c0a0ad55b39c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387405942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.3387405942
Directory	/workspace/10.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/10.sram_ctrl_ram_cfg.2158088775
Short name	T565
Test name
Test status
Simulation time	30304500 ps
CPU time	0.75 seconds
Started	Jun 23 06:25:13 PM PDT 24
Finished	Jun 23 06:25:15 PM PDT 24
Peak memory	203096 kb
Host	smart-c18cbe3c-0a12-482c-a0a3-bc17600e1be9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158088775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2158088775
Directory	/workspace/10.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/10.sram_ctrl_regwen.2450252444
Short name	T803
Test name
Test status
Simulation time	28792806668 ps
CPU time	685.13 seconds
Started	Jun 23 06:25:12 PM PDT 24
Finished	Jun 23 06:36:38 PM PDT 24
Peak memory	372712 kb
Host	smart-3306283e-d3c1-42ba-bf96-d894c035a366
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450252444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2450252444
Directory	/workspace/10.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/10.sram_ctrl_smoke.2356652213
Short name	T156
Test name
Test status
Simulation time	264398503 ps
CPU time	8.22 seconds
Started	Jun 23 06:25:06 PM PDT 24
Finished	Jun 23 06:25:14 PM PDT 24
Peak memory	203024 kb
Host	smart-c190508d-ec33-4c32-bbd4-34229c99622c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356652213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2356652213
Directory	/workspace/10.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all.386948167
Short name	T738
Test name
Test status
Simulation time	1719593669 ps
CPU time	161.28 seconds
Started	Jun 23 06:25:13 PM PDT 24
Finished	Jun 23 06:27:55 PM PDT 24
Peak memory	362020 kb
Host	smart-42e39ac2-0969-49c4-ba49-7b46d0f4014c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386948167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_stress_all.386948167
Directory	/workspace/10.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2685487035
Short name	T337
Test name
Test status
Simulation time	12317505358 ps
CPU time	767.83 seconds
Started	Jun 23 06:25:17 PM PDT 24
Finished	Jun 23 06:38:06 PM PDT 24
Peak memory	374996 kb
Host	smart-05d0524b-2db8-486f-8b3c-3f69ee87c8d7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2685487035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.2685487035
Directory	/workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1908503593
Short name	T707
Test name
Test status
Simulation time	4893113784 ps
CPU time	109.11 seconds
Started	Jun 23 06:25:09 PM PDT 24
Finished	Jun 23 06:26:58 PM PDT 24
Peak memory	203084 kb
Host	smart-0ee5f6a3-7d16-4dbe-84e7-64ba1ae7587d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908503593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.1908503593
Directory	/workspace/10.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.226109976
Short name	T673
Test name
Test status
Simulation time	128776136 ps
CPU time	33.64 seconds
Started	Jun 23 06:25:13 PM PDT 24
Finished	Jun 23 06:25:47 PM PDT 24
Peak memory	301176 kb
Host	smart-998548a8-2448-4764-8284-adf504f1e4e8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226109976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.226109976
Directory	/workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2168408959
Short name	T41
Test name
Test status
Simulation time	19501067931 ps
CPU time	1020.78 seconds
Started	Jun 23 06:25:13 PM PDT 24
Finished	Jun 23 06:42:14 PM PDT 24
Peak memory	366204 kb
Host	smart-a1bc5231-4497-4dcc-8d5d-0af8585044a1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168408959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.2168408959
Directory	/workspace/11.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/11.sram_ctrl_alert_test.3326359894
Short name	T660
Test name
Test status
Simulation time	14655468 ps
CPU time	0.67 seconds
Started	Jun 23 06:25:25 PM PDT 24
Finished	Jun 23 06:25:26 PM PDT 24
Peak memory	203136 kb
Host	smart-6cdcd233-cdd6-47e3-9b9f-024a4cd888c0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326359894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3326359894
Directory	/workspace/11.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.sram_ctrl_bijection.3704619733
Short name	T626
Test name
Test status
Simulation time	1982992125 ps
CPU time	65.29 seconds
Started	Jun 23 06:25:15 PM PDT 24
Finished	Jun 23 06:26:21 PM PDT 24
Peak memory	203032 kb
Host	smart-e53fee4e-3020-449b-a6a7-455cfc2b7795
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704619733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .3704619733
Directory	/workspace/11.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/11.sram_ctrl_executable.1906192682
Short name	T34
Test name
Test status
Simulation time	317987602 ps
CPU time	188.96 seconds
Started	Jun 23 06:25:24 PM PDT 24
Finished	Jun 23 06:28:33 PM PDT 24
Peak memory	358664 kb
Host	smart-34af8a36-0911-4289-874c-6b10c79b88bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906192682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.1906192682
Directory	/workspace/11.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/11.sram_ctrl_lc_escalation.3234070512
Short name	T604
Test name
Test status
Simulation time	390687884 ps
CPU time	4.53 seconds
Started	Jun 23 06:25:15 PM PDT 24
Finished	Jun 23 06:25:20 PM PDT 24
Peak memory	211256 kb
Host	smart-592d003e-67fb-4341-af0d-f484d805f3ca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234070512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.3234070512
Directory	/workspace/11.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/11.sram_ctrl_max_throughput.113557048
Short name	T302
Test name
Test status
Simulation time	151867616 ps
CPU time	107.67 seconds
Started	Jun 23 06:25:13 PM PDT 24
Finished	Jun 23 06:27:01 PM PDT 24
Peak memory	357084 kb
Host	smart-79be098f-24fb-432d-a5e5-6ec3a8e484ad
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113557048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.sram_ctrl_max_throughput.113557048
Directory	/workspace/11.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.755654910
Short name	T216
Test name
Test status
Simulation time	195708653 ps
CPU time	6.05 seconds
Started	Jun 23 06:25:18 PM PDT 24
Finished	Jun 23 06:25:25 PM PDT 24
Peak memory	211224 kb
Host	smart-88c276c4-6678-44fb-9256-746c3ae49853
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755654910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sram_ctrl_mem_partial_access.755654910
Directory	/workspace/11.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_walk.3580820217
Short name	T754
Test name
Test status
Simulation time	4057633838 ps
CPU time	10.97 seconds
Started	Jun 23 06:25:19 PM PDT 24
Finished	Jun 23 06:25:31 PM PDT 24
Peak memory	211340 kb
Host	smart-a14304f0-fd2e-4ef4-97d2-67c61d00b55d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580820217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.3580820217
Directory	/workspace/11.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/11.sram_ctrl_multiple_keys.2671392775
Short name	T418
Test name
Test status
Simulation time	176286011644 ps
CPU time	1822.09 seconds
Started	Jun 23 06:25:14 PM PDT 24
Finished	Jun 23 06:55:37 PM PDT 24
Peak memory	375944 kb
Host	smart-e61c3d71-b116-41d7-a0c0-0861624ae5da
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671392775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.2671392775
Directory	/workspace/11.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access.1842107843
Short name	T514
Test name
Test status
Simulation time	111909702 ps
CPU time	1.36 seconds
Started	Jun 23 06:25:17 PM PDT 24
Finished	Jun 23 06:25:18 PM PDT 24
Peak memory	203324 kb
Host	smart-88a2c137-c986-4494-9b97-933e17bd47d9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842107843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.1842107843
Directory	/workspace/11.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3796076721
Short name	T275
Test name
Test status
Simulation time	4956387085 ps
CPU time	359.34 seconds
Started	Jun 23 06:25:15 PM PDT 24
Finished	Jun 23 06:31:15 PM PDT 24
Peak memory	203152 kb
Host	smart-3c5b1b7b-9120-498d-a69e-ff56bbfb8e23
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796076721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.3796076721
Directory	/workspace/11.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/11.sram_ctrl_ram_cfg.3629778969
Short name	T445
Test name
Test status
Simulation time	82505817 ps
CPU time	0.78 seconds
Started	Jun 23 06:25:17 PM PDT 24
Finished	Jun 23 06:25:19 PM PDT 24
Peak memory	203124 kb
Host	smart-8dbd5101-946d-4a62-b96e-6653ed4a2003
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629778969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3629778969
Directory	/workspace/11.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/11.sram_ctrl_regwen.2358986675
Short name	T178
Test name
Test status
Simulation time	29101607242 ps
CPU time	922.09 seconds
Started	Jun 23 06:25:18 PM PDT 24
Finished	Jun 23 06:40:41 PM PDT 24
Peak memory	374208 kb
Host	smart-df59227b-d587-4290-b84c-c1dd7bf11db7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358986675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2358986675
Directory	/workspace/11.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/11.sram_ctrl_smoke.2404881587
Short name	T830
Test name
Test status
Simulation time	666544553 ps
CPU time	34.66 seconds
Started	Jun 23 06:25:14 PM PDT 24
Finished	Jun 23 06:25:49 PM PDT 24
Peak memory	282708 kb
Host	smart-b37c3eab-9063-4e59-a4cb-d9e9a054c1c6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404881587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2404881587
Directory	/workspace/11.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2884100649
Short name	T98
Test name
Test status
Simulation time	7337074434 ps
CPU time	371.75 seconds
Started	Jun 23 06:25:18 PM PDT 24
Finished	Jun 23 06:31:30 PM PDT 24
Peak memory	203408 kb
Host	smart-db3958b4-f6e1-4bd6-b5d4-4082553fe953
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884100649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.2884100649
Directory	/workspace/11.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2763020287
Short name	T787
Test name
Test status
Simulation time	101664950 ps
CPU time	34.28 seconds
Started	Jun 23 06:25:13 PM PDT 24
Finished	Jun 23 06:25:48 PM PDT 24
Peak memory	291832 kb
Host	smart-81f99104-a5e4-4c6c-a224-e05c88f5b911
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763020287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.2763020287
Directory	/workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.765301991
Short name	T305
Test name
Test status
Simulation time	1972364942 ps
CPU time	736.75 seconds
Started	Jun 23 06:25:16 PM PDT 24
Finished	Jun 23 06:37:34 PM PDT 24
Peak memory	373632 kb
Host	smart-00a7d9b8-5d47-41e9-80cd-28dad0c7fd96
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765301991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_access_during_key_req.765301991
Directory	/workspace/12.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/12.sram_ctrl_alert_test.3844304160
Short name	T743
Test name
Test status
Simulation time	12977611 ps
CPU time	0.65 seconds
Started	Jun 23 06:25:23 PM PDT 24
Finished	Jun 23 06:25:24 PM PDT 24
Peak memory	202928 kb
Host	smart-b0542c31-667e-4e5d-a02a-afb7c2f91841
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844304160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3844304160
Directory	/workspace/12.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.sram_ctrl_bijection.924653533
Short name	T600
Test name
Test status
Simulation time	12625134327 ps
CPU time	52.3 seconds
Started	Jun 23 06:25:18 PM PDT 24
Finished	Jun 23 06:26:11 PM PDT 24
Peak memory	203136 kb
Host	smart-593bbe31-5438-401f-bfaa-28b9a2860924
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924653533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection. 924653533
Directory	/workspace/12.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/12.sram_ctrl_executable.3395081969
Short name	T697
Test name
Test status
Simulation time	37683866299 ps
CPU time	635.58 seconds
Started	Jun 23 06:25:17 PM PDT 24
Finished	Jun 23 06:35:53 PM PDT 24
Peak memory	348404 kb
Host	smart-3d63d113-7365-4353-bdc7-47b076045338
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395081969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.3395081969
Directory	/workspace/12.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/12.sram_ctrl_lc_escalation.1789408879
Short name	T899
Test name
Test status
Simulation time	526376758 ps
CPU time	2.09 seconds
Started	Jun 23 06:25:19 PM PDT 24
Finished	Jun 23 06:25:21 PM PDT 24
Peak memory	203052 kb
Host	smart-a6cf28e1-9156-46be-b8b2-1c8bc4398733
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789408879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.1789408879
Directory	/workspace/12.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/12.sram_ctrl_max_throughput.3927958262
Short name	T845
Test name
Test status
Simulation time	555617025 ps
CPU time	128.99 seconds
Started	Jun 23 06:25:17 PM PDT 24
Finished	Jun 23 06:27:27 PM PDT 24
Peak memory	366272 kb
Host	smart-4bff13c2-4a44-46f1-b0e2-8293b7964b51
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927958262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.3927958262
Directory	/workspace/12.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1638864556
Short name	T685
Test name
Test status
Simulation time	44380286 ps
CPU time	2.67 seconds
Started	Jun 23 06:25:22 PM PDT 24
Finished	Jun 23 06:25:25 PM PDT 24
Peak memory	211256 kb
Host	smart-d9c90143-79aa-4296-b6da-f5ce70fed215
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638864556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.1638864556
Directory	/workspace/12.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_walk.2506513891
Short name	T329
Test name
Test status
Simulation time	458403697 ps
CPU time	11.12 seconds
Started	Jun 23 06:25:23 PM PDT 24
Finished	Jun 23 06:25:34 PM PDT 24
Peak memory	211244 kb
Host	smart-f7d5d1a2-d715-4404-921a-ac85100f7168
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506513891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.2506513891
Directory	/workspace/12.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/12.sram_ctrl_multiple_keys.3779946705
Short name	T344
Test name
Test status
Simulation time	5280866069 ps
CPU time	383.88 seconds
Started	Jun 23 06:25:18 PM PDT 24
Finished	Jun 23 06:31:42 PM PDT 24
Peak memory	345560 kb
Host	smart-086acbd4-a9ed-4edc-8f61-db313b7828fc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779946705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.3779946705
Directory	/workspace/12.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access.1566300427
Short name	T836
Test name
Test status
Simulation time	514179981 ps
CPU time	13.84 seconds
Started	Jun 23 06:25:23 PM PDT 24
Finished	Jun 23 06:25:37 PM PDT 24
Peak memory	247356 kb
Host	smart-eab60056-0fdc-4e0e-bde9-d3f0529321ff
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566300427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.1566300427
Directory	/workspace/12.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1575617713
Short name	T137
Test name
Test status
Simulation time	23911771821 ps
CPU time	619.61 seconds
Started	Jun 23 06:25:17 PM PDT 24
Finished	Jun 23 06:35:38 PM PDT 24
Peak memory	203184 kb
Host	smart-c12873c1-aeb0-4324-b1d0-b1ef30104296
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575617713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.1575617713
Directory	/workspace/12.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/12.sram_ctrl_ram_cfg.4215132455
Short name	T444
Test name
Test status
Simulation time	74743430 ps
CPU time	0.76 seconds
Started	Jun 23 06:25:23 PM PDT 24
Finished	Jun 23 06:25:24 PM PDT 24
Peak memory	203116 kb
Host	smart-5814eecc-a26c-4e15-a192-0e0dad2f5229
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215132455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.4215132455
Directory	/workspace/12.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/12.sram_ctrl_regwen.1452366402
Short name	T532
Test name
Test status
Simulation time	9441052975 ps
CPU time	872.81 seconds
Started	Jun 23 06:25:20 PM PDT 24
Finished	Jun 23 06:39:53 PM PDT 24
Peak memory	374900 kb
Host	smart-143ff99b-15a6-4935-8458-e2a3dd2846ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452366402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1452366402
Directory	/workspace/12.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/12.sram_ctrl_smoke.3771719460
Short name	T793
Test name
Test status
Simulation time	477336486 ps
CPU time	62.38 seconds
Started	Jun 23 06:25:19 PM PDT 24
Finished	Jun 23 06:26:22 PM PDT 24
Peak memory	329104 kb
Host	smart-f60e1fdc-27d7-4c45-ab6e-c4fb37430c4a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771719460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3771719460
Directory	/workspace/12.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all.1963264881
Short name	T345
Test name
Test status
Simulation time	9999783112 ps
CPU time	735.83 seconds
Started	Jun 23 06:25:22 PM PDT 24
Finished	Jun 23 06:37:38 PM PDT 24
Peak memory	375904 kb
Host	smart-b119f1e7-b6fa-41c1-bcec-e24e76cecbda
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963264881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.1963264881
Directory	/workspace/12.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3106926640
Short name	T332
Test name
Test status
Simulation time	9187100110 ps
CPU time	68.75 seconds
Started	Jun 23 06:25:21 PM PDT 24
Finished	Jun 23 06:26:30 PM PDT 24
Peak memory	285928 kb
Host	smart-c4073e89-076b-4128-a1a6-8ed9ab902874
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3106926640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3106926640
Directory	/workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1561228045
Short name	T521
Test name
Test status
Simulation time	5748396398 ps
CPU time	280.84 seconds
Started	Jun 23 06:25:17 PM PDT 24
Finished	Jun 23 06:29:58 PM PDT 24
Peak memory	203104 kb
Host	smart-b856b9d7-f0c8-455b-aaaa-7eaa41a1dc8f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561228045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.1561228045
Directory	/workspace/12.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3208779690
Short name	T848
Test name
Test status
Simulation time	546206161 ps
CPU time	148.06 seconds
Started	Jun 23 06:25:23 PM PDT 24
Finished	Jun 23 06:27:51 PM PDT 24
Peak memory	370972 kb
Host	smart-e8097401-a4e1-44ab-a224-9ab2229d2492
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208779690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.3208779690
Directory	/workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3067421766
Short name	T595
Test name
Test status
Simulation time	8754523179 ps
CPU time	397.75 seconds
Started	Jun 23 06:25:22 PM PDT 24
Finished	Jun 23 06:32:00 PM PDT 24
Peak memory	354396 kb
Host	smart-e6731d10-5e70-4ceb-a171-05fd563aa880
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067421766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.3067421766
Directory	/workspace/13.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/13.sram_ctrl_alert_test.4189336868
Short name	T655
Test name
Test status
Simulation time	30687161 ps
CPU time	0.66 seconds
Started	Jun 23 06:25:26 PM PDT 24
Finished	Jun 23 06:25:27 PM PDT 24
Peak memory	202932 kb
Host	smart-87f2bffd-f470-407b-b0b3-49d0fdc38409
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189336868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.4189336868
Directory	/workspace/13.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.sram_ctrl_bijection.1338102191
Short name	T251
Test name
Test status
Simulation time	1472773785 ps
CPU time	47.93 seconds
Started	Jun 23 06:25:22 PM PDT 24
Finished	Jun 23 06:26:10 PM PDT 24
Peak memory	203068 kb
Host	smart-f47b2f33-ad86-4344-9dad-355b679e849e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338102191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .1338102191
Directory	/workspace/13.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/13.sram_ctrl_executable.1619985187
Short name	T916
Test name
Test status
Simulation time	4404871093 ps
CPU time	270.14 seconds
Started	Jun 23 06:25:23 PM PDT 24
Finished	Jun 23 06:29:53 PM PDT 24
Peak memory	364756 kb
Host	smart-db77ecf8-cf2e-4e57-89f7-65a99684fbe0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619985187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.1619985187
Directory	/workspace/13.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/13.sram_ctrl_lc_escalation.2911094107
Short name	T110
Test name
Test status
Simulation time	847282643 ps
CPU time	3.71 seconds
Started	Jun 23 06:25:21 PM PDT 24
Finished	Jun 23 06:25:25 PM PDT 24
Peak memory	203132 kb
Host	smart-d21f7c67-ddc6-4ea8-8aec-002183d9a30c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911094107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.2911094107
Directory	/workspace/13.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/13.sram_ctrl_max_throughput.2940491448
Short name	T506
Test name
Test status
Simulation time	466083586 ps
CPU time	85.32 seconds
Started	Jun 23 06:25:24 PM PDT 24
Finished	Jun 23 06:26:49 PM PDT 24
Peak memory	341084 kb
Host	smart-7caf4296-a8af-4f4b-8978-bd2005afa8c9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940491448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.2940491448
Directory	/workspace/13.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.3048291231
Short name	T398
Test name
Test status
Simulation time	62740859 ps
CPU time	3.11 seconds
Started	Jun 23 06:25:21 PM PDT 24
Finished	Jun 23 06:25:25 PM PDT 24
Peak memory	211260 kb
Host	smart-d12e363d-ad0f-4edc-a2d9-a33082da7e25
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048291231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.3048291231
Directory	/workspace/13.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_walk.2189055921
Short name	T878
Test name
Test status
Simulation time	2739462340 ps
CPU time	10.54 seconds
Started	Jun 23 06:25:24 PM PDT 24
Finished	Jun 23 06:25:35 PM PDT 24
Peak memory	211288 kb
Host	smart-1c9810b4-96ff-43f5-9c05-16533ef9c68c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189055921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.2189055921
Directory	/workspace/13.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/13.sram_ctrl_multiple_keys.3544484018
Short name	T583
Test name
Test status
Simulation time	21424576138 ps
CPU time	336.4 seconds
Started	Jun 23 06:25:23 PM PDT 24
Finished	Jun 23 06:31:00 PM PDT 24
Peak memory	362168 kb
Host	smart-63ff23ed-5d57-4893-ab0a-c55ad9379715
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544484018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.3544484018
Directory	/workspace/13.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access.2367027228
Short name	T285
Test name
Test status
Simulation time	175921467 ps
CPU time	7.45 seconds
Started	Jun 23 06:25:21 PM PDT 24
Finished	Jun 23 06:25:29 PM PDT 24
Peak memory	229044 kb
Host	smart-bd7e3ad2-3729-40eb-b179-186a75bdc66a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367027228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.2367027228
Directory	/workspace/13.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2225560461
Short name	T829
Test name
Test status
Simulation time	14271850738 ps
CPU time	382.23 seconds
Started	Jun 23 06:25:21 PM PDT 24
Finished	Jun 23 06:31:43 PM PDT 24
Peak memory	203196 kb
Host	smart-58690997-e657-4d2a-92d4-5628c8169c7f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225560461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.2225560461
Directory	/workspace/13.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/13.sram_ctrl_ram_cfg.1865466252
Short name	T26
Test name
Test status
Simulation time	77064912 ps
CPU time	0.76 seconds
Started	Jun 23 06:25:22 PM PDT 24
Finished	Jun 23 06:25:24 PM PDT 24
Peak memory	203096 kb
Host	smart-aec2c3f2-2ff8-4502-9e13-c0e0392fda32
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865466252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1865466252
Directory	/workspace/13.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/13.sram_ctrl_regwen.3435984314
Short name	T318
Test name
Test status
Simulation time	17993452491 ps
CPU time	1076.48 seconds
Started	Jun 23 06:25:22 PM PDT 24
Finished	Jun 23 06:43:19 PM PDT 24
Peak memory	368856 kb
Host	smart-c71cf875-38c0-429b-9605-ab77e777138c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435984314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3435984314
Directory	/workspace/13.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/13.sram_ctrl_smoke.799090059
Short name	T198
Test name
Test status
Simulation time	646295168 ps
CPU time	125.09 seconds
Started	Jun 23 06:25:22 PM PDT 24
Finished	Jun 23 06:27:27 PM PDT 24
Peak memory	364560 kb
Host	smart-93fb12d5-d746-4223-a844-cda8fff2bbfb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799090059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.799090059
Directory	/workspace/13.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3712231425
Short name	T632
Test name
Test status
Simulation time	2323234016 ps
CPU time	207.97 seconds
Started	Jun 23 06:25:21 PM PDT 24
Finished	Jun 23 06:28:49 PM PDT 24
Peak memory	203068 kb
Host	smart-b47b6721-544a-4915-9f25-4eefce5e8c3a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712231425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.3712231425
Directory	/workspace/13.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2227951424
Short name	T511
Test name
Test status
Simulation time	115156931 ps
CPU time	51.73 seconds
Started	Jun 23 06:25:24 PM PDT 24
Finished	Jun 23 06:26:17 PM PDT 24
Peak memory	308744 kb
Host	smart-d8c2cd8b-aac5-4afa-bbb9-436744e81eff
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227951424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2227951424
Directory	/workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.810674513
Short name	T238
Test name
Test status
Simulation time	200326825 ps
CPU time	93.15 seconds
Started	Jun 23 06:25:33 PM PDT 24
Finished	Jun 23 06:27:06 PM PDT 24
Peak memory	336948 kb
Host	smart-ea6956c6-2d42-4ca1-9efc-97fda7c826a6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810674513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_access_during_key_req.810674513
Directory	/workspace/14.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/14.sram_ctrl_alert_test.2345438376
Short name	T919
Test name
Test status
Simulation time	33276472 ps
CPU time	0.67 seconds
Started	Jun 23 06:25:33 PM PDT 24
Finished	Jun 23 06:25:34 PM PDT 24
Peak memory	202936 kb
Host	smart-b8336565-adce-4b1d-bad5-8f629dd221a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345438376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.2345438376
Directory	/workspace/14.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.sram_ctrl_bijection.4052945328
Short name	T231
Test name
Test status
Simulation time	493678294 ps
CPU time	32.29 seconds
Started	Jun 23 06:25:34 PM PDT 24
Finished	Jun 23 06:26:07 PM PDT 24
Peak memory	203000 kb
Host	smart-9b2253dc-03be-4dc8-a116-d8ff7e1bf3a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052945328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .4052945328
Directory	/workspace/14.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/14.sram_ctrl_executable.3682447658
Short name	T363
Test name
Test status
Simulation time	13569760896 ps
CPU time	1019.2 seconds
Started	Jun 23 06:25:31 PM PDT 24
Finished	Jun 23 06:42:30 PM PDT 24
Peak memory	370972 kb
Host	smart-a57cbb00-ca2c-4426-a996-cfb8ee7a4408
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682447658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.3682447658
Directory	/workspace/14.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/14.sram_ctrl_lc_escalation.1154853914
Short name	T709
Test name
Test status
Simulation time	448699188 ps
CPU time	4.65 seconds
Started	Jun 23 06:25:34 PM PDT 24
Finished	Jun 23 06:25:40 PM PDT 24
Peak memory	214604 kb
Host	smart-0688692f-8c02-4abf-bf29-af9ad20764a5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154853914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.1154853914
Directory	/workspace/14.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/14.sram_ctrl_max_throughput.1287831228
Short name	T719
Test name
Test status
Simulation time	136794462 ps
CPU time	133.54 seconds
Started	Jun 23 06:25:34 PM PDT 24
Finished	Jun 23 06:27:49 PM PDT 24
Peak memory	369592 kb
Host	smart-aa9a313f-e2bc-4e36-a5c6-dda62086f927
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287831228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.1287831228
Directory	/workspace/14.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1927708207
Short name	T425
Test name
Test status
Simulation time	156706231 ps
CPU time	2.64 seconds
Started	Jun 23 06:25:31 PM PDT 24
Finished	Jun 23 06:25:34 PM PDT 24
Peak memory	211324 kb
Host	smart-f5af4ca9-4ae1-4352-8bc9-7d64a2df3287
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927708207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.1927708207
Directory	/workspace/14.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_walk.583186435
Short name	T485
Test name
Test status
Simulation time	445734646 ps
CPU time	10.59 seconds
Started	Jun 23 06:25:41 PM PDT 24
Finished	Jun 23 06:25:51 PM PDT 24
Peak memory	211272 kb
Host	smart-5f2e95e1-9d9f-4ae5-bf7d-b9001d6339f3
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583186435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _mem_walk.583186435
Directory	/workspace/14.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/14.sram_ctrl_multiple_keys.2135048959
Short name	T204
Test name
Test status
Simulation time	45840182157 ps
CPU time	1799.99 seconds
Started	Jun 23 06:25:25 PM PDT 24
Finished	Jun 23 06:55:26 PM PDT 24
Peak memory	376144 kb
Host	smart-91b2e84d-7948-4602-9898-47964bbbdb2a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135048959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.2135048959
Directory	/workspace/14.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access.2761453464
Short name	T146
Test name
Test status
Simulation time	2606371730 ps
CPU time	93.99 seconds
Started	Jun 23 06:25:34 PM PDT 24
Finished	Jun 23 06:27:08 PM PDT 24
Peak memory	354212 kb
Host	smart-46b18e6a-c6ea-47e2-a416-a9f5a06b3866
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761453464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.2761453464
Directory	/workspace/14.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3152427852
Short name	T407
Test name
Test status
Simulation time	6437899953 ps
CPU time	235.83 seconds
Started	Jun 23 06:25:26 PM PDT 24
Finished	Jun 23 06:29:22 PM PDT 24
Peak memory	203340 kb
Host	smart-7c56b3a0-bf72-4032-9b9c-a05e2e0faa1d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152427852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.3152427852
Directory	/workspace/14.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/14.sram_ctrl_ram_cfg.2361905314
Short name	T822
Test name
Test status
Simulation time	80823247 ps
CPU time	0.78 seconds
Started	Jun 23 06:25:34 PM PDT 24
Finished	Jun 23 06:25:35 PM PDT 24
Peak memory	203124 kb
Host	smart-13c3dc29-49ab-4c4c-bc56-5a6ec18da8b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361905314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2361905314
Directory	/workspace/14.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/14.sram_ctrl_regwen.1997944151
Short name	T173
Test name
Test status
Simulation time	11592384005 ps
CPU time	391.34 seconds
Started	Jun 23 06:25:31 PM PDT 24
Finished	Jun 23 06:32:03 PM PDT 24
Peak memory	363404 kb
Host	smart-ec6505cb-17c2-4556-95a9-a16019acbcc9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997944151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1997944151
Directory	/workspace/14.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/14.sram_ctrl_smoke.2044462654
Short name	T605
Test name
Test status
Simulation time	4275502703 ps
CPU time	19.15 seconds
Started	Jun 23 06:25:34 PM PDT 24
Finished	Jun 23 06:25:54 PM PDT 24
Peak memory	203104 kb
Host	smart-14cd3821-e036-4d03-978d-13ca03b3135f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044462654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2044462654
Directory	/workspace/14.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all.1435794702
Short name	T591
Test name
Test status
Simulation time	127809623383 ps
CPU time	2924.34 seconds
Started	Jun 23 06:25:33 PM PDT 24
Finished	Jun 23 07:14:18 PM PDT 24
Peak memory	376960 kb
Host	smart-d5b84768-d92e-413f-bb49-3e3831fb092b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435794702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.1435794702
Directory	/workspace/14.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2623388643
Short name	T921
Test name
Test status
Simulation time	13308996096 ps
CPU time	350.81 seconds
Started	Jun 23 06:25:25 PM PDT 24
Finished	Jun 23 06:31:16 PM PDT 24
Peak memory	203156 kb
Host	smart-1be5cbb0-84c3-4eae-862b-0636eb799c28
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623388643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.2623388643
Directory	/workspace/14.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1931420083
Short name	T399
Test name
Test status
Simulation time	71325858 ps
CPU time	13.91 seconds
Started	Jun 23 06:25:34 PM PDT 24
Finished	Jun 23 06:25:49 PM PDT 24
Peak memory	253156 kb
Host	smart-b715b6b7-0740-44f8-b1f3-b85d2ebef5df
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931420083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1931420083
Directory	/workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.796650696
Short name	T413
Test name
Test status
Simulation time	2815500082 ps
CPU time	798.85 seconds
Started	Jun 23 06:25:36 PM PDT 24
Finished	Jun 23 06:38:55 PM PDT 24
Peak memory	372880 kb
Host	smart-61c7d273-3037-4586-8449-2e4d891de51d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796650696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_access_during_key_req.796650696
Directory	/workspace/15.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/15.sram_ctrl_alert_test.2610808596
Short name	T320
Test name
Test status
Simulation time	20196888 ps
CPU time	0.67 seconds
Started	Jun 23 06:25:39 PM PDT 24
Finished	Jun 23 06:25:40 PM PDT 24
Peak memory	202936 kb
Host	smart-0c1bbb40-f7bb-4404-a3b0-78d8cad20934
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610808596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.2610808596
Directory	/workspace/15.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.sram_ctrl_bijection.375597782
Short name	T922
Test name
Test status
Simulation time	3786989125 ps
CPU time	18.61 seconds
Started	Jun 23 06:25:34 PM PDT 24
Finished	Jun 23 06:25:53 PM PDT 24
Peak memory	203176 kb
Host	smart-27861967-02ad-4925-ab44-fd4677c9aa74
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375597782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection. 375597782
Directory	/workspace/15.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/15.sram_ctrl_executable.3560408135
Short name	T453
Test name
Test status
Simulation time	8271773237 ps
CPU time	287.01 seconds
Started	Jun 23 06:25:39 PM PDT 24
Finished	Jun 23 06:30:27 PM PDT 24
Peak memory	371844 kb
Host	smart-d343915c-d1c8-4b05-bad6-64e8a0479844
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560408135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.3560408135
Directory	/workspace/15.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/15.sram_ctrl_lc_escalation.1584105608
Short name	T734
Test name
Test status
Simulation time	985229489 ps
CPU time	8.25 seconds
Started	Jun 23 06:25:37 PM PDT 24
Finished	Jun 23 06:25:46 PM PDT 24
Peak memory	202996 kb
Host	smart-3bfcfc7d-8fc5-452e-8572-6a54a863458e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584105608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.1584105608
Directory	/workspace/15.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/15.sram_ctrl_max_throughput.352159670
Short name	T154
Test name
Test status
Simulation time	116710766 ps
CPU time	89.43 seconds
Started	Jun 23 06:25:32 PM PDT 24
Finished	Jun 23 06:27:02 PM PDT 24
Peak memory	333460 kb
Host	smart-22bf6b46-56f8-4498-9135-6b3f5c1139fb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352159670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.sram_ctrl_max_throughput.352159670
Directory	/workspace/15.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3189148434
Short name	T794
Test name
Test status
Simulation time	1301228533 ps
CPU time	3.16 seconds
Started	Jun 23 06:25:35 PM PDT 24
Finished	Jun 23 06:25:38 PM PDT 24
Peak memory	211272 kb
Host	smart-6e033bf3-7cdf-487b-870b-ba36d68e9ebf
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189148434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.3189148434
Directory	/workspace/15.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_walk.1274386702
Short name	T712
Test name
Test status
Simulation time	295053772 ps
CPU time	4.63 seconds
Started	Jun 23 06:25:36 PM PDT 24
Finished	Jun 23 06:25:41 PM PDT 24
Peak memory	203120 kb
Host	smart-0a69ae87-4bd6-489d-83d9-88f52de08679
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274386702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.1274386702
Directory	/workspace/15.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/15.sram_ctrl_multiple_keys.1646083791
Short name	T150
Test name
Test status
Simulation time	4535408504 ps
CPU time	1665.64 seconds
Started	Jun 23 06:25:31 PM PDT 24
Finished	Jun 23 06:53:18 PM PDT 24
Peak memory	375624 kb
Host	smart-975de731-2725-4d9c-ab1d-bcbd2d8880b6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646083791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.1646083791
Directory	/workspace/15.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access.873871792
Short name	T920
Test name
Test status
Simulation time	1199774069 ps
CPU time	120.48 seconds
Started	Jun 23 06:25:39 PM PDT 24
Finished	Jun 23 06:27:40 PM PDT 24
Peak memory	354112 kb
Host	smart-854e569c-2ea9-46ef-b89d-0f7ffe4a1846
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873871792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s ram_ctrl_partial_access.873871792
Directory	/workspace/15.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3816526709
Short name	T891
Test name
Test status
Simulation time	47785120145 ps
CPU time	647.25 seconds
Started	Jun 23 06:25:33 PM PDT 24
Finished	Jun 23 06:36:21 PM PDT 24
Peak memory	203136 kb
Host	smart-baa2da19-1f72-41a7-b098-e674d393d219
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816526709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.3816526709
Directory	/workspace/15.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/15.sram_ctrl_ram_cfg.3279279135
Short name	T358
Test name
Test status
Simulation time	51573265 ps
CPU time	0.76 seconds
Started	Jun 23 06:25:38 PM PDT 24
Finished	Jun 23 06:25:39 PM PDT 24
Peak memory	203092 kb
Host	smart-98b908d6-5a08-4cf5-b78e-41a2850d7617
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279279135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3279279135
Directory	/workspace/15.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/15.sram_ctrl_regwen.3807135892
Short name	T431
Test name
Test status
Simulation time	11515012795 ps
CPU time	543.52 seconds
Started	Jun 23 06:25:36 PM PDT 24
Finished	Jun 23 06:34:40 PM PDT 24
Peak memory	371128 kb
Host	smart-e8039c7f-aac4-492c-9dab-6b5d5210212b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807135892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3807135892
Directory	/workspace/15.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/15.sram_ctrl_smoke.3569691564
Short name	T7
Test name
Test status
Simulation time	212429145 ps
CPU time	2.63 seconds
Started	Jun 23 06:25:32 PM PDT 24
Finished	Jun 23 06:25:35 PM PDT 24
Peak memory	203104 kb
Host	smart-ab2a672d-005e-46a6-a91b-13ea06e7065b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569691564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3569691564
Directory	/workspace/15.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all.1241915434
Short name	T236
Test name
Test status
Simulation time	7105675543 ps
CPU time	1963.02 seconds
Started	Jun 23 06:25:38 PM PDT 24
Finished	Jun 23 06:58:22 PM PDT 24
Peak memory	384952 kb
Host	smart-3b576549-1a2c-4743-83c8-023fe900adef
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241915434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.1241915434
Directory	/workspace/15.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.315842876
Short name	T689
Test name
Test status
Simulation time	1724763456 ps
CPU time	342.59 seconds
Started	Jun 23 06:25:36 PM PDT 24
Finished	Jun 23 06:31:19 PM PDT 24
Peak memory	368624 kb
Host	smart-ff4cf96f-86a7-4dec-b6d9-d58e32154a17
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=315842876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.315842876
Directory	/workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1738248485
Short name	T190
Test name
Test status
Simulation time	2685814017 ps
CPU time	245.75 seconds
Started	Jun 23 06:25:31 PM PDT 24
Finished	Jun 23 06:29:37 PM PDT 24
Peak memory	203184 kb
Host	smart-aefb6d15-3529-4aa2-861f-fd4463d4242a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738248485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.1738248485
Directory	/workspace/15.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2845209877
Short name	T782
Test name
Test status
Simulation time	261842154 ps
CPU time	107.47 seconds
Started	Jun 23 06:25:32 PM PDT 24
Finished	Jun 23 06:27:20 PM PDT 24
Peak memory	345072 kb
Host	smart-5a06635e-9e14-4060-9272-551f5618224d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845209877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2845209877
Directory	/workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3416394098
Short name	T489
Test name
Test status
Simulation time	1628904160 ps
CPU time	616.19 seconds
Started	Jun 23 06:25:40 PM PDT 24
Finished	Jun 23 06:35:57 PM PDT 24
Peak memory	368800 kb
Host	smart-78f458b0-b3ed-4777-90e9-6093fc13ff2c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416394098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.3416394098
Directory	/workspace/16.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/16.sram_ctrl_alert_test.2827848085
Short name	T556
Test name
Test status
Simulation time	87255568 ps
CPU time	0.66 seconds
Started	Jun 23 06:25:40 PM PDT 24
Finished	Jun 23 06:25:41 PM PDT 24
Peak memory	202944 kb
Host	smart-109e7fd7-6b9e-46d5-bde2-8455f53419ed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827848085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.2827848085
Directory	/workspace/16.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.sram_ctrl_bijection.3447165602
Short name	T167
Test name
Test status
Simulation time	1457923794 ps
CPU time	33.05 seconds
Started	Jun 23 06:25:40 PM PDT 24
Finished	Jun 23 06:26:13 PM PDT 24
Peak memory	203112 kb
Host	smart-62bdc9bf-b2e8-4338-9fe3-88ba91abccfe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447165602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .3447165602
Directory	/workspace/16.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/16.sram_ctrl_executable.1273659391
Short name	T309
Test name
Test status
Simulation time	56071243144 ps
CPU time	782.62 seconds
Started	Jun 23 06:25:41 PM PDT 24
Finished	Jun 23 06:38:44 PM PDT 24
Peak memory	374900 kb
Host	smart-e864cc3d-c6cd-46fd-9de9-0e09f1b270cf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273659391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.1273659391
Directory	/workspace/16.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/16.sram_ctrl_lc_escalation.2510136445
Short name	T261
Test name
Test status
Simulation time	389081742 ps
CPU time	4.63 seconds
Started	Jun 23 06:25:41 PM PDT 24
Finished	Jun 23 06:25:46 PM PDT 24
Peak memory	203200 kb
Host	smart-b7e21049-4cee-44cc-9994-96d238d604a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510136445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2510136445
Directory	/workspace/16.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/16.sram_ctrl_max_throughput.825798830
Short name	T151
Test name
Test status
Simulation time	714801599 ps
CPU time	55.73 seconds
Started	Jun 23 06:25:40 PM PDT 24
Finished	Jun 23 06:26:36 PM PDT 24
Peak memory	317572 kb
Host	smart-3da3ab06-8a54-4cb9-946d-34512ca3d6f3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825798830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.sram_ctrl_max_throughput.825798830
Directory	/workspace/16.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.1139798825
Short name	T472
Test name
Test status
Simulation time	799044880 ps
CPU time	5.96 seconds
Started	Jun 23 06:25:44 PM PDT 24
Finished	Jun 23 06:25:50 PM PDT 24
Peak memory	211272 kb
Host	smart-819617b8-4540-4d8f-8e55-94f12463d6e8
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139798825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.1139798825
Directory	/workspace/16.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_walk.3931950743
Short name	T859
Test name
Test status
Simulation time	685489165 ps
CPU time	12.12 seconds
Started	Jun 23 06:25:44 PM PDT 24
Finished	Jun 23 06:25:56 PM PDT 24
Peak memory	211272 kb
Host	smart-7e1b62ed-03bc-4b47-924b-6a9cc0bc17fa
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931950743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.3931950743
Directory	/workspace/16.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/16.sram_ctrl_multiple_keys.414181154
Short name	T319
Test name
Test status
Simulation time	16816236250 ps
CPU time	1321.66 seconds
Started	Jun 23 06:25:40 PM PDT 24
Finished	Jun 23 06:47:42 PM PDT 24
Peak memory	375296 kb
Host	smart-d5f44409-d1b3-4e3a-9088-7e9426d83a89
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414181154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multip le_keys.414181154
Directory	/workspace/16.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access.3289117397
Short name	T218
Test name
Test status
Simulation time	170691986 ps
CPU time	23.54 seconds
Started	Jun 23 06:25:36 PM PDT 24
Finished	Jun 23 06:26:00 PM PDT 24
Peak memory	274504 kb
Host	smart-2c3d2895-6129-4383-a761-300b28577ffd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289117397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.3289117397
Directory	/workspace/16.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1795475406
Short name	T641
Test name
Test status
Simulation time	11672658428 ps
CPU time	201.99 seconds
Started	Jun 23 06:25:41 PM PDT 24
Finished	Jun 23 06:29:03 PM PDT 24
Peak memory	202164 kb
Host	smart-87c7e0de-e902-477b-a4d0-3f2b8d1ed749
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795475406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.1795475406
Directory	/workspace/16.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/16.sram_ctrl_ram_cfg.2743506029
Short name	T594
Test name
Test status
Simulation time	187547414 ps
CPU time	0.82 seconds
Started	Jun 23 06:25:43 PM PDT 24
Finished	Jun 23 06:25:44 PM PDT 24
Peak memory	203088 kb
Host	smart-0fbb3c88-6eba-4ac6-9c58-ffdec201aa51
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743506029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2743506029
Directory	/workspace/16.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/16.sram_ctrl_regwen.3404793685
Short name	T833
Test name
Test status
Simulation time	809980145 ps
CPU time	88.52 seconds
Started	Jun 23 06:25:41 PM PDT 24
Finished	Jun 23 06:27:10 PM PDT 24
Peak memory	337280 kb
Host	smart-d37fc9de-c4f8-439d-a2b5-c2efec0d6996
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404793685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3404793685
Directory	/workspace/16.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/16.sram_ctrl_smoke.1831415943
Short name	T361
Test name
Test status
Simulation time	411170022 ps
CPU time	2.41 seconds
Started	Jun 23 06:25:38 PM PDT 24
Finished	Jun 23 06:25:41 PM PDT 24
Peak memory	203072 kb
Host	smart-3ca7bd48-136c-4893-a419-ca2863813867
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831415943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1831415943
Directory	/workspace/16.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1565919456
Short name	T442
Test name
Test status
Simulation time	610238617 ps
CPU time	12.56 seconds
Started	Jun 23 06:25:44 PM PDT 24
Finished	Jun 23 06:25:57 PM PDT 24
Peak memory	211380 kb
Host	smart-a75b0a7f-615e-47b3-9cde-cd4001c86557
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1565919456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1565919456
Directory	/workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.830596776
Short name	T725
Test name
Test status
Simulation time	21882900117 ps
CPU time	339.44 seconds
Started	Jun 23 06:25:41 PM PDT 24
Finished	Jun 23 06:31:20 PM PDT 24
Peak memory	202316 kb
Host	smart-ac8c3641-2c13-4984-aeea-da89fc020989
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830596776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_stress_pipeline.830596776
Directory	/workspace/16.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2988283158
Short name	T550
Test name
Test status
Simulation time	116703343 ps
CPU time	23.47 seconds
Started	Jun 23 06:25:36 PM PDT 24
Finished	Jun 23 06:26:00 PM PDT 24
Peak memory	284712 kb
Host	smart-6fbc1a70-ea0d-435a-ad2d-1d70820da181
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988283158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2988283158
Directory	/workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.788601877
Short name	T912
Test name
Test status
Simulation time	15735069320 ps
CPU time	1325.06 seconds
Started	Jun 23 06:25:48 PM PDT 24
Finished	Jun 23 06:47:53 PM PDT 24
Peak memory	372936 kb
Host	smart-4345c6f5-46c2-4551-a6e7-d3840d6a0bde
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788601877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_access_during_key_req.788601877
Directory	/workspace/17.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/17.sram_ctrl_alert_test.4261599143
Short name	T736
Test name
Test status
Simulation time	121078321 ps
CPU time	0.69 seconds
Started	Jun 23 06:25:47 PM PDT 24
Finished	Jun 23 06:25:48 PM PDT 24
Peak memory	202936 kb
Host	smart-248ee944-3014-484b-8a03-2209c7ff1809
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261599143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.4261599143
Directory	/workspace/17.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.sram_ctrl_bijection.686065549
Short name	T19
Test name
Test status
Simulation time	3685613331 ps
CPU time	79.89 seconds
Started	Jun 23 06:25:49 PM PDT 24
Finished	Jun 23 06:27:09 PM PDT 24
Peak memory	203120 kb
Host	smart-7c26f321-ea9c-485d-bb95-39c4da58635c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686065549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection. 686065549
Directory	/workspace/17.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/17.sram_ctrl_executable.2578838279
Short name	T435
Test name
Test status
Simulation time	43383382614 ps
CPU time	1215.68 seconds
Started	Jun 23 06:25:54 PM PDT 24
Finished	Jun 23 06:46:10 PM PDT 24
Peak memory	369492 kb
Host	smart-62fa565a-f6e4-409f-b586-91bb41ef016c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578838279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.2578838279
Directory	/workspace/17.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/17.sram_ctrl_lc_escalation.50014117
Short name	T465
Test name
Test status
Simulation time	2344190763 ps
CPU time	7.85 seconds
Started	Jun 23 06:25:48 PM PDT 24
Finished	Jun 23 06:25:56 PM PDT 24
Peak memory	203168 kb
Host	smart-74c5cd47-38bc-4761-a9cf-d387a53d9106
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50014117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esca lation.50014117
Directory	/workspace/17.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/17.sram_ctrl_max_throughput.4206171145
Short name	T148
Test name
Test status
Simulation time	67513645 ps
CPU time	7.16 seconds
Started	Jun 23 06:25:48 PM PDT 24
Finished	Jun 23 06:25:56 PM PDT 24
Peak memory	236860 kb
Host	smart-247b6f34-2b9e-49e7-9334-4f513eb07b80
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206171145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.4206171145
Directory	/workspace/17.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.4072426546
Short name	T884
Test name
Test status
Simulation time	82247355 ps
CPU time	2.75 seconds
Started	Jun 23 06:25:54 PM PDT 24
Finished	Jun 23 06:25:57 PM PDT 24
Peak memory	211336 kb
Host	smart-a838abef-428f-4fcd-b158-e27815d55ea7
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072426546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.4072426546
Directory	/workspace/17.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_walk.3021775246
Short name	T143
Test name
Test status
Simulation time	79805414 ps
CPU time	4.71 seconds
Started	Jun 23 06:25:47 PM PDT 24
Finished	Jun 23 06:25:52 PM PDT 24
Peak memory	211308 kb
Host	smart-f5b5cbeb-683f-4701-9c72-a583cf00a285
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021775246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.3021775246
Directory	/workspace/17.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/17.sram_ctrl_multiple_keys.977975970
Short name	T553
Test name
Test status
Simulation time	11600195842 ps
CPU time	669.56 seconds
Started	Jun 23 06:25:48 PM PDT 24
Finished	Jun 23 06:36:58 PM PDT 24
Peak memory	374900 kb
Host	smart-b01a16af-4442-4eaa-bd78-2af986a30fba
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977975970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multip le_keys.977975970
Directory	/workspace/17.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access.15348925
Short name	T856
Test name
Test status
Simulation time	238552862 ps
CPU time	2.64 seconds
Started	Jun 23 06:25:47 PM PDT 24
Finished	Jun 23 06:25:50 PM PDT 24
Peak memory	203120 kb
Host	smart-7cd3147a-937f-4e38-aa9b-8a2ab2f315f6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15348925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sr am_ctrl_partial_access.15348925
Directory	/workspace/17.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3552218632
Short name	T484
Test name
Test status
Simulation time	11952720006 ps
CPU time	313.9 seconds
Started	Jun 23 06:25:47 PM PDT 24
Finished	Jun 23 06:31:01 PM PDT 24
Peak memory	203164 kb
Host	smart-e0ad9e99-d9f3-4ab2-96b5-5e2a75cdfcc2
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552218632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.3552218632
Directory	/workspace/17.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/17.sram_ctrl_ram_cfg.1450830831
Short name	T287
Test name
Test status
Simulation time	107798069 ps
CPU time	0.77 seconds
Started	Jun 23 06:25:46 PM PDT 24
Finished	Jun 23 06:25:47 PM PDT 24
Peak memory	203120 kb
Host	smart-873ebff3-3d1d-4995-9653-3052723d482e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450830831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1450830831
Directory	/workspace/17.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/17.sram_ctrl_regwen.2828396724
Short name	T202
Test name
Test status
Simulation time	6278510631 ps
CPU time	434.77 seconds
Started	Jun 23 06:25:47 PM PDT 24
Finished	Jun 23 06:33:02 PM PDT 24
Peak memory	355516 kb
Host	smart-35276ebe-0d79-46a4-a58b-4ce3c97939f4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828396724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2828396724
Directory	/workspace/17.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/17.sram_ctrl_smoke.3568858972
Short name	T862
Test name
Test status
Simulation time	249458780 ps
CPU time	2.82 seconds
Started	Jun 23 06:25:42 PM PDT 24
Finished	Jun 23 06:25:46 PM PDT 24
Peak memory	203052 kb
Host	smart-7fdb1a11-1d5f-4e53-97b5-93f976031459
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568858972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3568858972
Directory	/workspace/17.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all.1591280588
Short name	T42
Test name
Test status
Simulation time	40058432676 ps
CPU time	4016.22 seconds
Started	Jun 23 06:25:49 PM PDT 24
Finished	Jun 23 07:32:46 PM PDT 24
Peak memory	376012 kb
Host	smart-e0aa8524-5d12-4dff-916a-36db273b196d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591280588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.1591280588
Directory	/workspace/17.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_pipeline.4031724529
Short name	T271
Test name
Test status
Simulation time	2703664144 ps
CPU time	257.33 seconds
Started	Jun 23 06:25:45 PM PDT 24
Finished	Jun 23 06:30:03 PM PDT 24
Peak memory	203092 kb
Host	smart-a6380620-0f21-45ef-aa78-b87a02b8b2de
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031724529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.4031724529
Directory	/workspace/17.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4062318352
Short name	T276
Test name
Test status
Simulation time	453299348 ps
CPU time	58.15 seconds
Started	Jun 23 06:25:47 PM PDT 24
Finished	Jun 23 06:26:46 PM PDT 24
Peak memory	317372 kb
Host	smart-6f8b55ad-ea0d-4c4f-bfc8-7ce35613b6bd
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062318352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.4062318352
Directory	/workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2280464825
Short name	T87
Test name
Test status
Simulation time	315027217 ps
CPU time	75.4 seconds
Started	Jun 23 06:25:52 PM PDT 24
Finished	Jun 23 06:27:07 PM PDT 24
Peak memory	320604 kb
Host	smart-e77bc153-9e37-49af-887f-155f90eaa536
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280464825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.2280464825
Directory	/workspace/18.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/18.sram_ctrl_alert_test.2607903545
Short name	T412
Test name
Test status
Simulation time	17514221 ps
CPU time	0.69 seconds
Started	Jun 23 06:25:52 PM PDT 24
Finished	Jun 23 06:25:53 PM PDT 24
Peak memory	202936 kb
Host	smart-b4f75465-59ac-4445-80c2-ed23fe327da0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607903545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2607903545
Directory	/workspace/18.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.sram_ctrl_bijection.3292779826
Short name	T437
Test name
Test status
Simulation time	585042944 ps
CPU time	37.86 seconds
Started	Jun 23 06:25:52 PM PDT 24
Finished	Jun 23 06:26:30 PM PDT 24
Peak memory	203020 kb
Host	smart-20075a6d-b6e5-41ba-8d24-b721aeda9f82
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292779826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .3292779826
Directory	/workspace/18.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/18.sram_ctrl_lc_escalation.4063584819
Short name	T375
Test name
Test status
Simulation time	299474943 ps
CPU time	4.01 seconds
Started	Jun 23 06:26:00 PM PDT 24
Finished	Jun 23 06:26:05 PM PDT 24
Peak memory	203088 kb
Host	smart-f5a097d2-eb42-4bd2-9750-c3b493b814fa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063584819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.4063584819
Directory	/workspace/18.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/18.sram_ctrl_max_throughput.913463425
Short name	T160
Test name
Test status
Simulation time	99844114 ps
CPU time	9.87 seconds
Started	Jun 23 06:25:51 PM PDT 24
Finished	Jun 23 06:26:01 PM PDT 24
Peak memory	241700 kb
Host	smart-006b8fca-8663-47d6-89a4-c9bd178bd8eb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913463425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.sram_ctrl_max_throughput.913463425
Directory	/workspace/18.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.4282972925
Short name	T729
Test name
Test status
Simulation time	65400813 ps
CPU time	4.74 seconds
Started	Jun 23 06:25:53 PM PDT 24
Finished	Jun 23 06:25:58 PM PDT 24
Peak memory	211304 kb
Host	smart-9f54c791-d789-4662-8c80-aea80cd10767
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282972925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.4282972925
Directory	/workspace/18.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_walk.2616386874
Short name	T184
Test name
Test status
Simulation time	349687242 ps
CPU time	10.25 seconds
Started	Jun 23 06:25:52 PM PDT 24
Finished	Jun 23 06:26:03 PM PDT 24
Peak memory	211300 kb
Host	smart-e6773d2b-5569-448f-81da-ce2b40c9bb57
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616386874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.2616386874
Directory	/workspace/18.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/18.sram_ctrl_multiple_keys.2302761591
Short name	T906
Test name
Test status
Simulation time	7387026871 ps
CPU time	555.5 seconds
Started	Jun 23 06:25:47 PM PDT 24
Finished	Jun 23 06:35:03 PM PDT 24
Peak memory	373924 kb
Host	smart-0eaba70e-0c27-4cb4-8a28-1c78e83de139
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302761591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.2302761591
Directory	/workspace/18.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access.1154973952
Short name	T139
Test name
Test status
Simulation time	811307067 ps
CPU time	134.51 seconds
Started	Jun 23 06:25:52 PM PDT 24
Finished	Jun 23 06:28:07 PM PDT 24
Peak memory	356272 kb
Host	smart-5afe8d23-3b16-4a79-a7bb-bdc18648fef0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154973952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.1154973952
Directory	/workspace/18.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3706373422
Short name	T395
Test name
Test status
Simulation time	7543221868 ps
CPU time	197.02 seconds
Started	Jun 23 06:25:51 PM PDT 24
Finished	Jun 23 06:29:09 PM PDT 24
Peak memory	203200 kb
Host	smart-81243e69-8594-4342-ae2d-623994755fbd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706373422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.3706373422
Directory	/workspace/18.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/18.sram_ctrl_ram_cfg.738472148
Short name	T298
Test name
Test status
Simulation time	88441630 ps
CPU time	0.75 seconds
Started	Jun 23 06:25:50 PM PDT 24
Finished	Jun 23 06:25:51 PM PDT 24
Peak memory	203012 kb
Host	smart-bf13a0ac-da40-4922-9521-476d2ea4528c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738472148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.738472148
Directory	/workspace/18.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/18.sram_ctrl_regwen.2872876696
Short name	T11
Test name
Test status
Simulation time	1083066243 ps
CPU time	249.89 seconds
Started	Jun 23 06:25:51 PM PDT 24
Finished	Jun 23 06:30:02 PM PDT 24
Peak memory	363052 kb
Host	smart-a5ec6c62-e053-4e85-8ea2-65bdb271ab77
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872876696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2872876696
Directory	/workspace/18.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/18.sram_ctrl_smoke.1896240127
Short name	T527
Test name
Test status
Simulation time	180749013 ps
CPU time	7.05 seconds
Started	Jun 23 06:25:46 PM PDT 24
Finished	Jun 23 06:25:53 PM PDT 24
Peak memory	233836 kb
Host	smart-fff9c38b-4713-4e0e-b98a-def83edd1b0d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896240127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1896240127
Directory	/workspace/18.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all.687429587
Short name	T877
Test name
Test status
Simulation time	82036778599 ps
CPU time	2927.74 seconds
Started	Jun 23 06:25:52 PM PDT 24
Finished	Jun 23 07:14:40 PM PDT 24
Peak memory	376328 kb
Host	smart-faa65a41-a85e-4d72-ac17-934e32758a96
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687429587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_stress_all.687429587
Directory	/workspace/18.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2076994558
Short name	T24
Test name
Test status
Simulation time	2654830066 ps
CPU time	23.65 seconds
Started	Jun 23 06:25:50 PM PDT 24
Finished	Jun 23 06:26:15 PM PDT 24
Peak memory	218712 kb
Host	smart-eab4753f-648c-4471-a5b3-e194ed8749f9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2076994558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2076994558
Directory	/workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2507689400
Short name	T620
Test name
Test status
Simulation time	7519756291 ps
CPU time	195.43 seconds
Started	Jun 23 06:25:51 PM PDT 24
Finished	Jun 23 06:29:07 PM PDT 24
Peak memory	203172 kb
Host	smart-4373705f-1f0b-4c91-b551-853f7b75fe34
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507689400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.2507689400
Directory	/workspace/18.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1206751433
Short name	T33
Test name
Test status
Simulation time	682123849 ps
CPU time	89.98 seconds
Started	Jun 23 06:25:51 PM PDT 24
Finished	Jun 23 06:27:22 PM PDT 24
Peak memory	338848 kb
Host	smart-14a6db16-75c0-4646-9aa5-1e9787f04f2e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206751433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1206751433
Directory	/workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3234477682
Short name	T633
Test name
Test status
Simulation time	1153628213 ps
CPU time	285.75 seconds
Started	Jun 23 06:25:57 PM PDT 24
Finished	Jun 23 06:30:43 PM PDT 24
Peak memory	347804 kb
Host	smart-d8caf312-9c0a-46a8-8a53-ac74c4fe9261
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234477682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.3234477682
Directory	/workspace/19.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/19.sram_ctrl_alert_test.796664979
Short name	T247
Test name
Test status
Simulation time	16132491 ps
CPU time	0.7 seconds
Started	Jun 23 06:26:00 PM PDT 24
Finished	Jun 23 06:26:01 PM PDT 24
Peak memory	202900 kb
Host	smart-2410fa82-3b64-4d6c-8cfe-dba807e6f2b3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796664979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.796664979
Directory	/workspace/19.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.sram_ctrl_bijection.2269098872
Short name	T849
Test name
Test status
Simulation time	3698171787 ps
CPU time	57.59 seconds
Started	Jun 23 06:25:59 PM PDT 24
Finished	Jun 23 06:26:57 PM PDT 24
Peak memory	203124 kb
Host	smart-817dc562-64bf-4044-92af-fba1c8f144b2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269098872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .2269098872
Directory	/workspace/19.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/19.sram_ctrl_executable.202964262
Short name	T850
Test name
Test status
Simulation time	21703031511 ps
CPU time	1078.28 seconds
Started	Jun 23 06:25:58 PM PDT 24
Finished	Jun 23 06:43:56 PM PDT 24
Peak memory	374968 kb
Host	smart-3b426ca9-d067-434d-88eb-61e78aaf29d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202964262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl e.202964262
Directory	/workspace/19.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/19.sram_ctrl_lc_escalation.68051572
Short name	T686
Test name
Test status
Simulation time	578214795 ps
CPU time	6.47 seconds
Started	Jun 23 06:25:57 PM PDT 24
Finished	Jun 23 06:26:03 PM PDT 24
Peak memory	214904 kb
Host	smart-45390243-f0e0-41cc-8222-8d55381788e3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68051572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esca lation.68051572
Directory	/workspace/19.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/19.sram_ctrl_max_throughput.4198493499
Short name	T815
Test name
Test status
Simulation time	141734065 ps
CPU time	136.32 seconds
Started	Jun 23 06:25:57 PM PDT 24
Finished	Jun 23 06:28:14 PM PDT 24
Peak memory	370340 kb
Host	smart-c43075ba-40b6-47ea-bb6f-a48519dac92c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198493499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.4198493499
Directory	/workspace/19.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1365820140
Short name	T700
Test name
Test status
Simulation time	412235264 ps
CPU time	3.44 seconds
Started	Jun 23 06:26:01 PM PDT 24
Finished	Jun 23 06:26:05 PM PDT 24
Peak memory	211232 kb
Host	smart-bb5d4ead-fb0b-4d99-90df-d7dc08eed776
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365820140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.1365820140
Directory	/workspace/19.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_walk.3590155852
Short name	T796
Test name
Test status
Simulation time	2620038402 ps
CPU time	11.16 seconds
Started	Jun 23 06:26:01 PM PDT 24
Finished	Jun 23 06:26:12 PM PDT 24
Peak memory	203112 kb
Host	smart-8c9acd01-2349-4e71-9da4-a470ced9804f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590155852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.3590155852
Directory	/workspace/19.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/19.sram_ctrl_multiple_keys.2349499122
Short name	T518
Test name
Test status
Simulation time	54158397198 ps
CPU time	1557.9 seconds
Started	Jun 23 06:25:57 PM PDT 24
Finished	Jun 23 06:51:55 PM PDT 24
Peak memory	375980 kb
Host	smart-6d996a4e-19f2-4be8-bf80-f171502ae2ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349499122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.2349499122
Directory	/workspace/19.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access.162868635
Short name	T380
Test name
Test status
Simulation time	1888658172 ps
CPU time	71.23 seconds
Started	Jun 23 06:25:57 PM PDT 24
Finished	Jun 23 06:27:09 PM PDT 24
Peak memory	308940 kb
Host	smart-6d9db0fe-2d57-4dbf-be5d-f410074e2da6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162868635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s ram_ctrl_partial_access.162868635
Directory	/workspace/19.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2962791830
Short name	T761
Test name
Test status
Simulation time	115291906880 ps
CPU time	639.58 seconds
Started	Jun 23 06:25:57 PM PDT 24
Finished	Jun 23 06:36:37 PM PDT 24
Peak memory	203152 kb
Host	smart-2381b0c8-f642-44f8-89f5-4ba1cad3ec23
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962791830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.2962791830
Directory	/workspace/19.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/19.sram_ctrl_ram_cfg.628289749
Short name	T886
Test name
Test status
Simulation time	81286114 ps
CPU time	0.78 seconds
Started	Jun 23 06:26:01 PM PDT 24
Finished	Jun 23 06:26:02 PM PDT 24
Peak memory	203096 kb
Host	smart-61be8875-a673-4cd3-aa45-408ffa79a6d6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628289749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.628289749
Directory	/workspace/19.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/19.sram_ctrl_regwen.4093331691
Short name	T664
Test name
Test status
Simulation time	97429946240 ps
CPU time	1013.03 seconds
Started	Jun 23 06:25:59 PM PDT 24
Finished	Jun 23 06:42:52 PM PDT 24
Peak memory	370792 kb
Host	smart-bbfd829e-74b6-40cd-af10-66498526e533
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093331691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4093331691
Directory	/workspace/19.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/19.sram_ctrl_smoke.307336621
Short name	T152
Test name
Test status
Simulation time	466625133 ps
CPU time	6.6 seconds
Started	Jun 23 06:25:58 PM PDT 24
Finished	Jun 23 06:26:05 PM PDT 24
Peak memory	202992 kb
Host	smart-38f9a245-771f-4330-81da-59817d794c6b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307336621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.307336621
Directory	/workspace/19.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all.1389148945
Short name	T393
Test name
Test status
Simulation time	14214965498 ps
CPU time	766.36 seconds
Started	Jun 23 06:26:02 PM PDT 24
Finished	Jun 23 06:38:49 PM PDT 24
Peak memory	356224 kb
Host	smart-17162079-7865-4fc2-addd-582069e5c437
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389148945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.1389148945
Directory	/workspace/19.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2509835583
Short name	T640
Test name
Test status
Simulation time	2898575505 ps
CPU time	232.79 seconds
Started	Jun 23 06:26:00 PM PDT 24
Finished	Jun 23 06:29:53 PM PDT 24
Peak memory	351460 kb
Host	smart-1e0b7e67-abe5-4679-a3d7-c6557b94aa99
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2509835583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2509835583
Directory	/workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.225590917
Short name	T575
Test name
Test status
Simulation time	1385835575 ps
CPU time	131.79 seconds
Started	Jun 23 06:25:57 PM PDT 24
Finished	Jun 23 06:28:09 PM PDT 24
Peak memory	203100 kb
Host	smart-94c8d063-a4c7-45a0-b5da-f36eda65e8f1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225590917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sram_ctrl_stress_pipeline.225590917
Directory	/workspace/19.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1460605676
Short name	T601
Test name
Test status
Simulation time	127554163 ps
CPU time	72.13 seconds
Started	Jun 23 06:25:58 PM PDT 24
Finished	Jun 23 06:27:10 PM PDT 24
Peak memory	321596 kb
Host	smart-824c2b37-31ed-4b58-83e3-e69b1b17b6fe
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460605676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1460605676
Directory	/workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.3284758473
Short name	T455
Test name
Test status
Simulation time	1954426777 ps
CPU time	849.35 seconds
Started	Jun 23 06:24:34 PM PDT 24
Finished	Jun 23 06:38:43 PM PDT 24
Peak memory	375732 kb
Host	smart-58131562-0073-4ebc-b226-1e6c4efe194c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284758473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.3284758473
Directory	/workspace/2.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/2.sram_ctrl_alert_test.4066915095
Short name	T516
Test name
Test status
Simulation time	17239619 ps
CPU time	0.63 seconds
Started	Jun 23 06:24:34 PM PDT 24
Finished	Jun 23 06:24:35 PM PDT 24
Peak memory	202648 kb
Host	smart-42c55a0a-6378-42aa-84fa-3a13e5f6713f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066915095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.4066915095
Directory	/workspace/2.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.sram_ctrl_bijection.1174168901
Short name	T646
Test name
Test status
Simulation time	13287113923 ps
CPU time	37.83 seconds
Started	Jun 23 06:24:32 PM PDT 24
Finished	Jun 23 06:25:10 PM PDT 24
Peak memory	203216 kb
Host	smart-eaff8af6-4e88-4d60-a4b2-546097e87bfe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174168901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 1174168901
Directory	/workspace/2.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/2.sram_ctrl_executable.4169379959
Short name	T133
Test name
Test status
Simulation time	60038553732 ps
CPU time	746.28 seconds
Started	Jun 23 06:24:36 PM PDT 24
Finished	Jun 23 06:37:03 PM PDT 24
Peak memory	365260 kb
Host	smart-01c0dc8a-370b-48ac-bbb6-d6b1d213194b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169379959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.4169379959
Directory	/workspace/2.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/2.sram_ctrl_lc_escalation.3209953456
Short name	T243
Test name
Test status
Simulation time	451938879 ps
CPU time	5.99 seconds
Started	Jun 23 06:24:32 PM PDT 24
Finished	Jun 23 06:24:38 PM PDT 24
Peak memory	211292 kb
Host	smart-2833bd24-eb1a-46f5-ba06-b7c95dc9a40f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209953456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.3209953456
Directory	/workspace/2.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/2.sram_ctrl_max_throughput.1823222940
Short name	T931
Test name
Test status
Simulation time	131228953 ps
CPU time	7.2 seconds
Started	Jun 23 06:24:31 PM PDT 24
Finished	Jun 23 06:24:39 PM PDT 24
Peak memory	237048 kb
Host	smart-28896870-f7fb-4fee-b34c-ab451ce2ee8e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823222940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.1823222940
Directory	/workspace/2.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.400879707
Short name	T597
Test name
Test status
Simulation time	1855133101 ps
CPU time	5.5 seconds
Started	Jun 23 06:24:34 PM PDT 24
Finished	Jun 23 06:24:40 PM PDT 24
Peak memory	211304 kb
Host	smart-64f858d0-d1c2-42b2-9e81-88f72fff1456
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400879707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. sram_ctrl_mem_partial_access.400879707
Directory	/workspace/2.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_walk.167463740
Short name	T549
Test name
Test status
Simulation time	917624918 ps
CPU time	10.31 seconds
Started	Jun 23 06:24:35 PM PDT 24
Finished	Jun 23 06:24:46 PM PDT 24
Peak memory	211280 kb
Host	smart-2005bcf9-0439-47fe-b2a9-91c5f43afe2b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167463740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ mem_walk.167463740
Directory	/workspace/2.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/2.sram_ctrl_multiple_keys.1649245460
Short name	T371
Test name
Test status
Simulation time	17511228924 ps
CPU time	1008.19 seconds
Started	Jun 23 06:24:31 PM PDT 24
Finished	Jun 23 06:41:20 PM PDT 24
Peak memory	375348 kb
Host	smart-ef2cf601-2478-42b2-8a1c-4bc2f99b891b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649245460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.1649245460
Directory	/workspace/2.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access.4987561
Short name	T430
Test name
Test status
Simulation time	25203062 ps
CPU time	0.83 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:24:32 PM PDT 24
Peak memory	202844 kb
Host	smart-99dc8eeb-63f3-4e8b-b28c-2fb8ccba3c59
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4987561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram _ctrl_partial_access.4987561
Directory	/workspace/2.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3560751809
Short name	T477
Test name
Test status
Simulation time	7581790005 ps
CPU time	174.75 seconds
Started	Jun 23 06:24:31 PM PDT 24
Finished	Jun 23 06:27:27 PM PDT 24
Peak memory	203088 kb
Host	smart-400d6641-e9c0-41cf-97fb-d50b20e71b8f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560751809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.3560751809
Directory	/workspace/2.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/2.sram_ctrl_ram_cfg.1464708933
Short name	T510
Test name
Test status
Simulation time	137474780 ps
CPU time	0.78 seconds
Started	Jun 23 06:24:37 PM PDT 24
Finished	Jun 23 06:24:38 PM PDT 24
Peak memory	203060 kb
Host	smart-76a01eb4-1292-4575-88db-abffb6363760
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464708933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1464708933
Directory	/workspace/2.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/2.sram_ctrl_regwen.1667958168
Short name	T20
Test name
Test status
Simulation time	2236896508 ps
CPU time	893.05 seconds
Started	Jun 23 06:24:36 PM PDT 24
Finished	Jun 23 06:39:29 PM PDT 24
Peak memory	375744 kb
Host	smart-ed45a7bb-30b0-4f39-9786-60b0f9ea4b89
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667958168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1667958168
Directory	/workspace/2.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/2.sram_ctrl_sec_cm.2532895947
Short name	T29
Test name
Test status
Simulation time	361269286 ps
CPU time	1.9 seconds
Started	Jun 23 06:24:35 PM PDT 24
Finished	Jun 23 06:24:37 PM PDT 24
Peak memory	221892 kb
Host	smart-ab07bfb2-425d-4670-98a2-f3a6fdece64a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532895947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2532895947
Directory	/workspace/2.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.sram_ctrl_smoke.3523174753
Short name	T923
Test name
Test status
Simulation time	168001064 ps
CPU time	5.67 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:24:36 PM PDT 24
Peak memory	225528 kb
Host	smart-716f2b11-8451-4485-9ef1-06acde612885
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523174753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3523174753
Directory	/workspace/2.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all.2454411814
Short name	T811
Test name
Test status
Simulation time	247617078244 ps
CPU time	2102.4 seconds
Started	Jun 23 06:24:37 PM PDT 24
Finished	Jun 23 06:59:40 PM PDT 24
Peak memory	376340 kb
Host	smart-45958de3-2a3d-4881-b9da-ba0bf2da866a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454411814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.2454411814
Directory	/workspace/2.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3526509525
Short name	T108
Test name
Test status
Simulation time	749917813 ps
CPU time	23.07 seconds
Started	Jun 23 06:24:39 PM PDT 24
Finished	Jun 23 06:25:03 PM PDT 24
Peak memory	211396 kb
Host	smart-66d8cc68-297f-4086-a2af-c5ac0cb4bd78
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3526509525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3526509525
Directory	/workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1232334091
Short name	T414
Test name
Test status
Simulation time	16280908606 ps
CPU time	401.56 seconds
Started	Jun 23 06:24:30 PM PDT 24
Finished	Jun 23 06:31:13 PM PDT 24
Peak memory	203192 kb
Host	smart-8d9500ed-d69a-4633-92dc-be0fe5590d1e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232334091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.1232334091
Directory	/workspace/2.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.664174305
Short name	T411
Test name
Test status
Simulation time	360128976 ps
CPU time	23.96 seconds
Started	Jun 23 06:24:34 PM PDT 24
Finished	Jun 23 06:24:58 PM PDT 24
Peak memory	288920 kb
Host	smart-08eae2d1-ceab-42cf-aae2-a33bc764c280
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664174305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.664174305
Directory	/workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.3222007804
Short name	T342
Test name
Test status
Simulation time	8699704779 ps
CPU time	455.05 seconds
Started	Jun 23 06:26:06 PM PDT 24
Finished	Jun 23 06:33:42 PM PDT 24
Peak memory	301952 kb
Host	smart-949ea70d-cd62-4939-bbc6-3fe231fbae88
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222007804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.3222007804
Directory	/workspace/20.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/20.sram_ctrl_alert_test.4103718129
Short name	T560
Test name
Test status
Simulation time	72864677 ps
CPU time	0.68 seconds
Started	Jun 23 06:26:09 PM PDT 24
Finished	Jun 23 06:26:10 PM PDT 24
Peak memory	202904 kb
Host	smart-24eec275-8368-44d2-92f0-46b54c78a2ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103718129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.4103718129
Directory	/workspace/20.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.sram_ctrl_bijection.199556147
Short name	T838
Test name
Test status
Simulation time	2392769815 ps
CPU time	38.54 seconds
Started	Jun 23 06:26:02 PM PDT 24
Finished	Jun 23 06:26:41 PM PDT 24
Peak memory	203120 kb
Host	smart-5d66496b-464b-465d-beb7-ca42d4539909
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199556147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection. 199556147
Directory	/workspace/20.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/20.sram_ctrl_executable.3266512915
Short name	T530
Test name
Test status
Simulation time	11016557865 ps
CPU time	674.68 seconds
Started	Jun 23 06:26:08 PM PDT 24
Finished	Jun 23 06:37:23 PM PDT 24
Peak memory	354536 kb
Host	smart-e0de55f5-7220-4a35-8a02-84bd9e7105a5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266512915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.3266512915
Directory	/workspace/20.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/20.sram_ctrl_lc_escalation.789437209
Short name	T702
Test name
Test status
Simulation time	960242950 ps
CPU time	5.86 seconds
Started	Jun 23 06:26:06 PM PDT 24
Finished	Jun 23 06:26:13 PM PDT 24
Peak memory	203128 kb
Host	smart-0e1b2773-839f-4a74-81de-af20a7e8eebb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789437209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc alation.789437209
Directory	/workspace/20.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/20.sram_ctrl_max_throughput.1751194331
Short name	T343
Test name
Test status
Simulation time	118190205 ps
CPU time	68.95 seconds
Started	Jun 23 06:26:02 PM PDT 24
Finished	Jun 23 06:27:11 PM PDT 24
Peak memory	341020 kb
Host	smart-c22dd284-e4a3-48b3-8df5-f69ddd00cf12
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751194331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.1751194331
Directory	/workspace/20.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.1506646482
Short name	T542
Test name
Test status
Simulation time	43613366 ps
CPU time	2.68 seconds
Started	Jun 23 06:26:05 PM PDT 24
Finished	Jun 23 06:26:08 PM PDT 24
Peak memory	211220 kb
Host	smart-83b61116-d9b0-4ee7-8c36-bade93052626
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506646482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.1506646482
Directory	/workspace/20.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_walk.2172324060
Short name	T765
Test name
Test status
Simulation time	519148360 ps
CPU time	5.91 seconds
Started	Jun 23 06:26:06 PM PDT 24
Finished	Jun 23 06:26:12 PM PDT 24
Peak memory	211292 kb
Host	smart-854bc6cd-5e98-44cd-8890-2832ce1dc470
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172324060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.2172324060
Directory	/workspace/20.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/20.sram_ctrl_multiple_keys.2601303616
Short name	T613
Test name
Test status
Simulation time	17715880499 ps
CPU time	653.54 seconds
Started	Jun 23 06:26:03 PM PDT 24
Finished	Jun 23 06:36:57 PM PDT 24
Peak memory	362524 kb
Host	smart-39a71246-5199-4341-9e1e-3b2118549a17
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601303616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.2601303616
Directory	/workspace/20.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access.3728028919
Short name	T255
Test name
Test status
Simulation time	29815605 ps
CPU time	0.92 seconds
Started	Jun 23 06:26:01 PM PDT 24
Finished	Jun 23 06:26:03 PM PDT 24
Peak memory	202872 kb
Host	smart-12128a74-3373-4812-b64b-ae705822646f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728028919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.3728028919
Directory	/workspace/20.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3188851181
Short name	T650
Test name
Test status
Simulation time	22825265476 ps
CPU time	332.91 seconds
Started	Jun 23 06:26:02 PM PDT 24
Finished	Jun 23 06:31:35 PM PDT 24
Peak memory	203384 kb
Host	smart-c322166e-e324-4f25-93e9-77cc2affad88
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188851181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.3188851181
Directory	/workspace/20.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/20.sram_ctrl_ram_cfg.3453070982
Short name	T313
Test name
Test status
Simulation time	48053430 ps
CPU time	0.78 seconds
Started	Jun 23 06:26:05 PM PDT 24
Finished	Jun 23 06:26:06 PM PDT 24
Peak memory	203080 kb
Host	smart-6693f2de-5c8e-44c0-b5c7-242239124f7c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453070982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3453070982
Directory	/workspace/20.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/20.sram_ctrl_regwen.1025979934
Short name	T200
Test name
Test status
Simulation time	97486633790 ps
CPU time	556.08 seconds
Started	Jun 23 06:26:08 PM PDT 24
Finished	Jun 23 06:35:25 PM PDT 24
Peak memory	374940 kb
Host	smart-6a1fcc2c-4823-4c4e-9fb5-36afc1064455
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025979934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1025979934
Directory	/workspace/20.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/20.sram_ctrl_smoke.265826200
Short name	T195
Test name
Test status
Simulation time	1870361783 ps
CPU time	4.27 seconds
Started	Jun 23 06:26:01 PM PDT 24
Finished	Jun 23 06:26:05 PM PDT 24
Peak memory	203048 kb
Host	smart-2970862f-ab3a-47b5-bec8-c1e36bf7f4eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265826200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.265826200
Directory	/workspace/20.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all.496237172
Short name	T652
Test name
Test status
Simulation time	167766493911 ps
CPU time	3690.6 seconds
Started	Jun 23 06:26:06 PM PDT 24
Finished	Jun 23 07:27:37 PM PDT 24
Peak memory	377156 kb
Host	smart-192fa5f1-c4c7-4fe5-8627-d244b133bb5a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496237172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_stress_all.496237172
Directory	/workspace/20.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.649756666
Short name	T339
Test name
Test status
Simulation time	10648547796 ps
CPU time	83.18 seconds
Started	Jun 23 06:26:07 PM PDT 24
Finished	Jun 23 06:27:30 PM PDT 24
Peak memory	247116 kb
Host	smart-7d0f2b88-6c8b-4f1d-a175-987aa414f005
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=649756666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.649756666
Directory	/workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3142243648
Short name	T104
Test name
Test status
Simulation time	11986938290 ps
CPU time	301.73 seconds
Started	Jun 23 06:26:04 PM PDT 24
Finished	Jun 23 06:31:06 PM PDT 24
Peak memory	203164 kb
Host	smart-9e4be3f4-cedf-4d54-bd5e-f449bb37c305
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142243648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.3142243648
Directory	/workspace/20.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2217441984
Short name	T544
Test name
Test status
Simulation time	633328451 ps
CPU time	1.55 seconds
Started	Jun 23 06:26:02 PM PDT 24
Finished	Jun 23 06:26:03 PM PDT 24
Peak memory	211248 kb
Host	smart-efc3d63e-4d20-4cd2-970e-af10cbbc2ac3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217441984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.2217441984
Directory	/workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1547510878
Short name	T469
Test name
Test status
Simulation time	29428245713 ps
CPU time	797.25 seconds
Started	Jun 23 06:26:10 PM PDT 24
Finished	Jun 23 06:39:28 PM PDT 24
Peak memory	370912 kb
Host	smart-61836e83-e42b-4f31-b280-ee5326fa056f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547510878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.1547510878
Directory	/workspace/21.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/21.sram_ctrl_alert_test.778788568
Short name	T374
Test name
Test status
Simulation time	67360450 ps
CPU time	0.67 seconds
Started	Jun 23 06:26:16 PM PDT 24
Finished	Jun 23 06:26:17 PM PDT 24
Peak memory	202892 kb
Host	smart-26fd12ac-e806-4edf-bce3-7512cdeae512
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778788568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.778788568
Directory	/workspace/21.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.sram_ctrl_bijection.2756146155
Short name	T648
Test name
Test status
Simulation time	3172972025 ps
CPU time	54.4 seconds
Started	Jun 23 06:26:13 PM PDT 24
Finished	Jun 23 06:27:08 PM PDT 24
Peak memory	203068 kb
Host	smart-62d46b69-632f-4de8-a368-2c596b8240c8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756146155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .2756146155
Directory	/workspace/21.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/21.sram_ctrl_executable.2116870882
Short name	T851
Test name
Test status
Simulation time	85416196716 ps
CPU time	860.01 seconds
Started	Jun 23 06:26:15 PM PDT 24
Finished	Jun 23 06:40:35 PM PDT 24
Peak memory	367948 kb
Host	smart-c0c88b70-c1cc-4766-873e-0aa65146967c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116870882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.2116870882
Directory	/workspace/21.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/21.sram_ctrl_lc_escalation.1953710498
Short name	T808
Test name
Test status
Simulation time	1576250472 ps
CPU time	9.1 seconds
Started	Jun 23 06:26:10 PM PDT 24
Finished	Jun 23 06:26:20 PM PDT 24
Peak memory	203056 kb
Host	smart-68cc4fa2-f620-41b8-8f9c-d7deb1096556
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953710498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.1953710498
Directory	/workspace/21.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/21.sram_ctrl_max_throughput.2880994314
Short name	T869
Test name
Test status
Simulation time	60413751 ps
CPU time	7.72 seconds
Started	Jun 23 06:26:11 PM PDT 24
Finished	Jun 23 06:26:19 PM PDT 24
Peak memory	238000 kb
Host	smart-5000913d-06d7-4b05-94e1-2387f5eb15c6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880994314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.2880994314
Directory	/workspace/21.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.340782425
Short name	T929
Test name
Test status
Simulation time	364197618 ps
CPU time	5.25 seconds
Started	Jun 23 06:26:15 PM PDT 24
Finished	Jun 23 06:26:20 PM PDT 24
Peak memory	211244 kb
Host	smart-17a128ef-e14f-4f5e-bd70-60914ac46ca0
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340782425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_mem_partial_access.340782425
Directory	/workspace/21.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_walk.898630142
Short name	T355
Test name
Test status
Simulation time	1570771081 ps
CPU time	6.06 seconds
Started	Jun 23 06:26:16 PM PDT 24
Finished	Jun 23 06:26:22 PM PDT 24
Peak memory	211240 kb
Host	smart-817955de-40da-4955-96e5-45969bbe7696
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898630142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _mem_walk.898630142
Directory	/workspace/21.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/21.sram_ctrl_multiple_keys.3073926116
Short name	T140
Test name
Test status
Simulation time	22218864954 ps
CPU time	994.44 seconds
Started	Jun 23 06:26:10 PM PDT 24
Finished	Jun 23 06:42:45 PM PDT 24
Peak memory	376008 kb
Host	smart-3aafda0c-be21-4531-9643-32797a7ae157
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073926116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.3073926116
Directory	/workspace/21.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access.4008511366
Short name	T213
Test name
Test status
Simulation time	1348339995 ps
CPU time	117.01 seconds
Started	Jun 23 06:26:12 PM PDT 24
Finished	Jun 23 06:28:09 PM PDT 24
Peak memory	366464 kb
Host	smart-79d5efe5-625b-4f83-9908-3bb491258ae0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008511366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.4008511366
Directory	/workspace/21.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.4127085439
Short name	T723
Test name
Test status
Simulation time	68202760724 ps
CPU time	406.06 seconds
Started	Jun 23 06:26:11 PM PDT 24
Finished	Jun 23 06:32:58 PM PDT 24
Peak memory	203156 kb
Host	smart-250d8875-eb72-45d0-b15e-e533b342ca40
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127085439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.4127085439
Directory	/workspace/21.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/21.sram_ctrl_ram_cfg.2604190185
Short name	T181
Test name
Test status
Simulation time	33967513 ps
CPU time	0.77 seconds
Started	Jun 23 06:26:14 PM PDT 24
Finished	Jun 23 06:26:15 PM PDT 24
Peak memory	203116 kb
Host	smart-0011182a-7486-4819-bf97-388e3cb5aac3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604190185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2604190185
Directory	/workspace/21.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/21.sram_ctrl_regwen.3678549202
Short name	T826
Test name
Test status
Simulation time	76515761086 ps
CPU time	1190.98 seconds
Started	Jun 23 06:26:15 PM PDT 24
Finished	Jun 23 06:46:07 PM PDT 24
Peak memory	375184 kb
Host	smart-e8859af8-500e-4118-97d6-dc173f09985d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678549202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3678549202
Directory	/workspace/21.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/21.sram_ctrl_smoke.1249439782
Short name	T616
Test name
Test status
Simulation time	118771658 ps
CPU time	2.6 seconds
Started	Jun 23 06:26:28 PM PDT 24
Finished	Jun 23 06:26:31 PM PDT 24
Peak memory	209556 kb
Host	smart-20ba25e3-b04d-4b80-b840-57eda5f00dca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249439782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1249439782
Directory	/workspace/21.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all.3407913192
Short name	T417
Test name
Test status
Simulation time	22756958366 ps
CPU time	1581.43 seconds
Started	Jun 23 06:26:16 PM PDT 24
Finished	Jun 23 06:52:38 PM PDT 24
Peak memory	376336 kb
Host	smart-315ae294-eb9a-4d17-a24d-89e50a39cca8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407913192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.3407913192
Directory	/workspace/21.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.4284268025
Short name	T746
Test name
Test status
Simulation time	1104463101 ps
CPU time	315.47 seconds
Started	Jun 23 06:26:16 PM PDT 24
Finished	Jun 23 06:31:31 PM PDT 24
Peak memory	355548 kb
Host	smart-8926379c-3a4d-4208-8649-bc7f300e4cde
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4284268025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.4284268025
Directory	/workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1009851985
Short name	T713
Test name
Test status
Simulation time	2310193984 ps
CPU time	227.58 seconds
Started	Jun 23 06:26:10 PM PDT 24
Finished	Jun 23 06:29:58 PM PDT 24
Peak memory	203140 kb
Host	smart-0cb7079b-bc4e-4449-9d8a-892e764e1363
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009851985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.1009851985
Directory	/workspace/21.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.645504656
Short name	T533
Test name
Test status
Simulation time	61601240 ps
CPU time	5.81 seconds
Started	Jun 23 06:26:13 PM PDT 24
Finished	Jun 23 06:26:19 PM PDT 24
Peak memory	234812 kb
Host	smart-653d8fb7-f108-4a47-a1de-2ef7d4586791
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645504656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.645504656
Directory	/workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/22.sram_ctrl_access_during_key_req.2636898525
Short name	T897
Test name
Test status
Simulation time	1581157843 ps
CPU time	66.51 seconds
Started	Jun 23 06:26:18 PM PDT 24
Finished	Jun 23 06:27:25 PM PDT 24
Peak memory	288344 kb
Host	smart-9f9b46cf-04a1-4fd9-a84a-b27a3cbf88a4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636898525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.2636898525
Directory	/workspace/22.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/22.sram_ctrl_alert_test.3825624933
Short name	T614
Test name
Test status
Simulation time	32014354 ps
CPU time	0.69 seconds
Started	Jun 23 06:26:20 PM PDT 24
Finished	Jun 23 06:26:21 PM PDT 24
Peak memory	202952 kb
Host	smart-ec22f54e-6a25-4d2e-be43-dfd522f31535
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825624933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.3825624933
Directory	/workspace/22.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.sram_ctrl_bijection.2230082639
Short name	T161
Test name
Test status
Simulation time	4549056576 ps
CPU time	18.24 seconds
Started	Jun 23 06:26:18 PM PDT 24
Finished	Jun 23 06:26:36 PM PDT 24
Peak memory	203044 kb
Host	smart-b01d15b5-94e7-4589-aed8-b8a80d9a6b85
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230082639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .2230082639
Directory	/workspace/22.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/22.sram_ctrl_executable.4219608750
Short name	T134
Test name
Test status
Simulation time	44553866687 ps
CPU time	683.43 seconds
Started	Jun 23 06:26:15 PM PDT 24
Finished	Jun 23 06:37:39 PM PDT 24
Peak memory	363692 kb
Host	smart-6282eeac-cb5b-4551-8c1d-d784ccdf3613
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219608750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.4219608750
Directory	/workspace/22.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/22.sram_ctrl_lc_escalation.491627528
Short name	T488
Test name
Test status
Simulation time	2998539422 ps
CPU time	8.9 seconds
Started	Jun 23 06:26:16 PM PDT 24
Finished	Jun 23 06:26:25 PM PDT 24
Peak memory	203276 kb
Host	smart-2d1a636b-7d0b-4c31-833b-b4b11f76db28
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491627528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc alation.491627528
Directory	/workspace/22.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/22.sram_ctrl_max_throughput.773190292
Short name	T141
Test name
Test status
Simulation time	53653186 ps
CPU time	4.46 seconds
Started	Jun 23 06:26:17 PM PDT 24
Finished	Jun 23 06:26:22 PM PDT 24
Peak memory	226872 kb
Host	smart-acae9c58-cb4d-4256-a87b-efa90ddfce51
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773190292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.sram_ctrl_max_throughput.773190292
Directory	/workspace/22.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3840783932
Short name	T89
Test name
Test status
Simulation time	45440017 ps
CPU time	2.77 seconds
Started	Jun 23 06:26:21 PM PDT 24
Finished	Jun 23 06:26:24 PM PDT 24
Peak memory	211284 kb
Host	smart-8c60d03a-226c-40a6-9157-fdf2062ebaed
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840783932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.3840783932
Directory	/workspace/22.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_walk.3983763852
Short name	T188
Test name
Test status
Simulation time	279303903 ps
CPU time	4.89 seconds
Started	Jun 23 06:26:15 PM PDT 24
Finished	Jun 23 06:26:20 PM PDT 24
Peak memory	211304 kb
Host	smart-879429c5-7b5a-4e0a-aa92-6cbdb0a2c8ba
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983763852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.3983763852
Directory	/workspace/22.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/22.sram_ctrl_multiple_keys.4058539491
Short name	T248
Test name
Test status
Simulation time	35958100178 ps
CPU time	1203.22 seconds
Started	Jun 23 06:26:15 PM PDT 24
Finished	Jun 23 06:46:19 PM PDT 24
Peak memory	375948 kb
Host	smart-578f033a-65be-4795-9f34-3b465bfe7134
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058539491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.4058539491
Directory	/workspace/22.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access.1861703711
Short name	T359
Test name
Test status
Simulation time	627898777 ps
CPU time	35.27 seconds
Started	Jun 23 06:26:18 PM PDT 24
Finished	Jun 23 06:26:54 PM PDT 24
Peak memory	303152 kb
Host	smart-2e71a7e5-2d44-48cd-936a-45528e28b72f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861703711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.1861703711
Directory	/workspace/22.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3070473488
Short name	T678
Test name
Test status
Simulation time	28985320472 ps
CPU time	329.99 seconds
Started	Jun 23 06:26:16 PM PDT 24
Finished	Jun 23 06:31:46 PM PDT 24
Peak memory	203116 kb
Host	smart-f7de3751-09da-46a4-96c6-8dd458136dbc
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070473488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.3070473488
Directory	/workspace/22.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/22.sram_ctrl_ram_cfg.2221681887
Short name	T902
Test name
Test status
Simulation time	78652006 ps
CPU time	0.77 seconds
Started	Jun 23 06:26:16 PM PDT 24
Finished	Jun 23 06:26:18 PM PDT 24
Peak memory	203116 kb
Host	smart-1c6e4022-c8b2-45c4-b43a-2b0d0fc49048
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221681887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.2221681887
Directory	/workspace/22.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/22.sram_ctrl_regwen.349748556
Short name	T726
Test name
Test status
Simulation time	2342224204 ps
CPU time	797.06 seconds
Started	Jun 23 06:26:18 PM PDT 24
Finished	Jun 23 06:39:36 PM PDT 24
Peak memory	362660 kb
Host	smart-80c8586f-3489-446f-b98e-a23ade54aa55
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349748556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.349748556
Directory	/workspace/22.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/22.sram_ctrl_smoke.3044891845
Short name	T857
Test name
Test status
Simulation time	243110778 ps
CPU time	3.39 seconds
Started	Jun 23 06:26:14 PM PDT 24
Finished	Jun 23 06:26:18 PM PDT 24
Peak memory	203076 kb
Host	smart-2f5941d5-b002-4c71-99ee-199d0423c485
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044891845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3044891845
Directory	/workspace/22.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all.4130061263
Short name	T820
Test name
Test status
Simulation time	13802745573 ps
CPU time	498.84 seconds
Started	Jun 23 06:26:22 PM PDT 24
Finished	Jun 23 06:34:41 PM PDT 24
Peak memory	368328 kb
Host	smart-4ef069ad-5c2b-48e0-9e4c-82d5970b1f0d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130061263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.4130061263
Directory	/workspace/22.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.281056913
Short name	T557
Test name
Test status
Simulation time	5692110169 ps
CPU time	34.35 seconds
Started	Jun 23 06:26:19 PM PDT 24
Finished	Jun 23 06:26:54 PM PDT 24
Peak memory	211820 kb
Host	smart-5036cf27-5770-4a01-90e4-17ede094ecb4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=281056913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.281056913
Directory	/workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2936683778
Short name	T315
Test name
Test status
Simulation time	12819742580 ps
CPU time	314.2 seconds
Started	Jun 23 06:26:14 PM PDT 24
Finished	Jun 23 06:31:29 PM PDT 24
Peak memory	203124 kb
Host	smart-ec3a6249-b423-44c2-8d6d-8f4d340edd60
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936683778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.2936683778
Directory	/workspace/22.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3116528657
Short name	T409
Test name
Test status
Simulation time	410097050 ps
CPU time	26.37 seconds
Started	Jun 23 06:26:17 PM PDT 24
Finished	Jun 23 06:26:44 PM PDT 24
Peak memory	281616 kb
Host	smart-3db6ad74-5988-43f4-83b2-bff4ae22bdbf
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116528657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3116528657
Directory	/workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.775888684
Short name	T665
Test name
Test status
Simulation time	5193404755 ps
CPU time	2456.33 seconds
Started	Jun 23 06:26:24 PM PDT 24
Finished	Jun 23 07:07:21 PM PDT 24
Peak memory	371784 kb
Host	smart-05adcbe6-ae86-4a79-9ee3-b0acae3b1fea
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775888684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 23.sram_ctrl_access_during_key_req.775888684
Directory	/workspace/23.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/23.sram_ctrl_alert_test.105704917
Short name	T555
Test name
Test status
Simulation time	17850910 ps
CPU time	0.67 seconds
Started	Jun 23 06:26:25 PM PDT 24
Finished	Jun 23 06:26:26 PM PDT 24
Peak memory	202876 kb
Host	smart-3a7fafc3-1aa7-4f9c-9e1a-cadac6431502
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105704917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.105704917
Directory	/workspace/23.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.sram_ctrl_bijection.437777990
Short name	T767
Test name
Test status
Simulation time	515340614 ps
CPU time	37.26 seconds
Started	Jun 23 06:26:24 PM PDT 24
Finished	Jun 23 06:27:01 PM PDT 24
Peak memory	203108 kb
Host	smart-fe815b01-67e4-4e86-ba4e-f81225eb6408
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437777990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection. 437777990
Directory	/workspace/23.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/23.sram_ctrl_executable.132426751
Short name	T657
Test name
Test status
Simulation time	2627618847 ps
CPU time	688.08 seconds
Started	Jun 23 06:26:25 PM PDT 24
Finished	Jun 23 06:37:53 PM PDT 24
Peak memory	365920 kb
Host	smart-16e93d46-9a25-4e5e-b9e2-74152e40b9e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132426751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executabl e.132426751
Directory	/workspace/23.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/23.sram_ctrl_lc_escalation.1150675223
Short name	T254
Test name
Test status
Simulation time	807855595 ps
CPU time	5.92 seconds
Started	Jun 23 06:26:27 PM PDT 24
Finished	Jun 23 06:26:33 PM PDT 24
Peak memory	215040 kb
Host	smart-a752f1ae-8b05-4ce3-bcf4-e0a6e458ae2b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150675223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.1150675223
Directory	/workspace/23.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/23.sram_ctrl_max_throughput.180612551
Short name	T267
Test name
Test status
Simulation time	148312147 ps
CPU time	18.8 seconds
Started	Jun 23 06:26:18 PM PDT 24
Finished	Jun 23 06:26:38 PM PDT 24
Peak memory	268408 kb
Host	smart-ad337b5f-a397-464f-93fa-9d29ef85a8e6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180612551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.sram_ctrl_max_throughput.180612551
Directory	/workspace/23.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.693262081
Short name	T832
Test name
Test status
Simulation time	64993926 ps
CPU time	4.48 seconds
Started	Jun 23 06:26:24 PM PDT 24
Finished	Jun 23 06:26:29 PM PDT 24
Peak memory	211308 kb
Host	smart-9aa7f5f2-a5cd-4f96-93cb-d21cd52e0e08
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693262081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .sram_ctrl_mem_partial_access.693262081
Directory	/workspace/23.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_walk.1805810891
Short name	T50
Test name
Test status
Simulation time	590820481 ps
CPU time	5.75 seconds
Started	Jun 23 06:26:29 PM PDT 24
Finished	Jun 23 06:26:34 PM PDT 24
Peak memory	203028 kb
Host	smart-8a385bd2-368a-4110-bfac-a0f9900f6954
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805810891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.1805810891
Directory	/workspace/23.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/23.sram_ctrl_multiple_keys.1486772424
Short name	T426
Test name
Test status
Simulation time	26730788691 ps
CPU time	679.14 seconds
Started	Jun 23 06:26:20 PM PDT 24
Finished	Jun 23 06:37:40 PM PDT 24
Peak memory	373444 kb
Host	smart-0745bb97-305e-4e8a-a771-8f4700770da7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486772424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.1486772424
Directory	/workspace/23.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access.2838255026
Short name	T585
Test name
Test status
Simulation time	351201309 ps
CPU time	6.85 seconds
Started	Jun 23 06:26:19 PM PDT 24
Finished	Jun 23 06:26:26 PM PDT 24
Peak memory	203108 kb
Host	smart-6b8f1732-fbe4-4da3-bf14-c6be19fbb606
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838255026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.2838255026
Directory	/workspace/23.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3615084746
Short name	T338
Test name
Test status
Simulation time	81599986606 ps
CPU time	483.92 seconds
Started	Jun 23 06:26:24 PM PDT 24
Finished	Jun 23 06:34:28 PM PDT 24
Peak memory	203080 kb
Host	smart-5cbffcc6-d70f-4538-bb28-d1c96084cf63
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615084746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.3615084746
Directory	/workspace/23.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/23.sram_ctrl_ram_cfg.2513234245
Short name	T608
Test name
Test status
Simulation time	58523105 ps
CPU time	0.77 seconds
Started	Jun 23 06:26:26 PM PDT 24
Finished	Jun 23 06:26:27 PM PDT 24
Peak memory	203076 kb
Host	smart-215ab11a-3fd1-4557-b922-2e1a2973bd25
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513234245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2513234245
Directory	/workspace/23.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/23.sram_ctrl_regwen.80400169
Short name	T132
Test name
Test status
Simulation time	29083111808 ps
CPU time	1393.77 seconds
Started	Jun 23 06:26:26 PM PDT 24
Finished	Jun 23 06:49:40 PM PDT 24
Peak memory	375444 kb
Host	smart-e467961b-8f7f-4e1d-aab4-69556af1a8c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80400169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.80400169
Directory	/workspace/23.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/23.sram_ctrl_smoke.3923906342
Short name	T233
Test name
Test status
Simulation time	713920740 ps
CPU time	15.94 seconds
Started	Jun 23 06:26:19 PM PDT 24
Finished	Jun 23 06:26:35 PM PDT 24
Peak memory	203040 kb
Host	smart-cc2dd7d4-7a91-49c8-892f-7396f11c8e86
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923906342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3923906342
Directory	/workspace/23.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all.506628604
Short name	T422
Test name
Test status
Simulation time	6770514194 ps
CPU time	2677.63 seconds
Started	Jun 23 06:26:27 PM PDT 24
Finished	Jun 23 07:11:06 PM PDT 24
Peak memory	374964 kb
Host	smart-6aaf1e25-9889-4152-a293-196368cfe66e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506628604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_stress_all.506628604
Directory	/workspace/23.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2840044929
Short name	T55
Test name
Test status
Simulation time	6484993222 ps
CPU time	50.25 seconds
Started	Jun 23 06:26:26 PM PDT 24
Finished	Jun 23 06:27:17 PM PDT 24
Peak memory	211532 kb
Host	smart-bdfbab81-e4e2-4553-b4ef-8f975c582dbb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2840044929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2840044929
Directory	/workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1426502852
Short name	T526
Test name
Test status
Simulation time	13382350356 ps
CPU time	304.28 seconds
Started	Jun 23 06:26:20 PM PDT 24
Finished	Jun 23 06:31:25 PM PDT 24
Peak memory	203140 kb
Host	smart-0e0c764d-b9ac-48ba-ae56-8ada1211baab
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426502852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.1426502852
Directory	/workspace/23.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.959949939
Short name	T209
Test name
Test status
Simulation time	96552714 ps
CPU time	27.02 seconds
Started	Jun 23 06:26:20 PM PDT 24
Finished	Jun 23 06:26:47 PM PDT 24
Peak memory	284816 kb
Host	smart-858977dd-1823-4d9d-8360-d19c21dff6cd
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959949939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.959949939
Directory	/workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3284528819
Short name	T674
Test name
Test status
Simulation time	14007732540 ps
CPU time	641.76 seconds
Started	Jun 23 06:26:25 PM PDT 24
Finished	Jun 23 06:37:07 PM PDT 24
Peak memory	359564 kb
Host	smart-08824078-16d9-4e29-a622-cc6f93f6153f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284528819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.3284528819
Directory	/workspace/24.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/24.sram_ctrl_alert_test.2637097588
Short name	T492
Test name
Test status
Simulation time	44052646 ps
CPU time	0.67 seconds
Started	Jun 23 06:26:33 PM PDT 24
Finished	Jun 23 06:26:34 PM PDT 24
Peak memory	202952 kb
Host	smart-7f3c0ce8-45b9-4244-b40c-909190123131
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637097588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2637097588
Directory	/workspace/24.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.sram_ctrl_bijection.3935920013
Short name	T498
Test name
Test status
Simulation time	11244771871 ps
CPU time	33.21 seconds
Started	Jun 23 06:26:24 PM PDT 24
Finished	Jun 23 06:26:58 PM PDT 24
Peak memory	203188 kb
Host	smart-70ae1ee7-b6fe-49b8-ae0f-fb535808ba19
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935920013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .3935920013
Directory	/workspace/24.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/24.sram_ctrl_executable.3548727305
Short name	T257
Test name
Test status
Simulation time	2804673687 ps
CPU time	643.86 seconds
Started	Jun 23 06:26:27 PM PDT 24
Finished	Jun 23 06:37:11 PM PDT 24
Peak memory	374984 kb
Host	smart-d1aaee5c-002d-40ab-95a1-f92e15473dd8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548727305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.3548727305
Directory	/workspace/24.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/24.sram_ctrl_lc_escalation.3114542722
Short name	T727
Test name
Test status
Simulation time	1523052112 ps
CPU time	5.67 seconds
Started	Jun 23 06:26:25 PM PDT 24
Finished	Jun 23 06:26:31 PM PDT 24
Peak memory	203148 kb
Host	smart-0f833877-3008-4d82-a58f-66739d4a16a2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114542722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.3114542722
Directory	/workspace/24.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/24.sram_ctrl_max_throughput.1076541246
Short name	T602
Test name
Test status
Simulation time	202167483 ps
CPU time	6.61 seconds
Started	Jun 23 06:26:26 PM PDT 24
Finished	Jun 23 06:26:33 PM PDT 24
Peak memory	235736 kb
Host	smart-f88f2fa5-3bfe-401e-a0f3-974d40f13346
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076541246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.1076541246
Directory	/workspace/24.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2961268699
Short name	T207
Test name
Test status
Simulation time	114455751 ps
CPU time	2.84 seconds
Started	Jun 23 06:26:33 PM PDT 24
Finished	Jun 23 06:26:36 PM PDT 24
Peak memory	211304 kb
Host	smart-844a26af-01c5-4a0c-a137-a220db4f56c3
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961268699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.2961268699
Directory	/workspace/24.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_walk.2689132515
Short name	T392
Test name
Test status
Simulation time	2633013106 ps
CPU time	11.07 seconds
Started	Jun 23 06:26:32 PM PDT 24
Finished	Jun 23 06:26:43 PM PDT 24
Peak memory	211276 kb
Host	smart-642d3bbf-b58d-4af2-a220-f8e2c13b89ee
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689132515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2689132515
Directory	/workspace/24.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/24.sram_ctrl_multiple_keys.1418229490
Short name	T223
Test name
Test status
Simulation time	44034636777 ps
CPU time	1025.68 seconds
Started	Jun 23 06:26:26 PM PDT 24
Finished	Jun 23 06:43:32 PM PDT 24
Peak memory	371540 kb
Host	smart-ed503018-e8c9-4d2c-b027-f4639655651b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418229490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.1418229490
Directory	/workspace/24.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access.3494726658
Short name	T153
Test name
Test status
Simulation time	1260358854 ps
CPU time	114.13 seconds
Started	Jun 23 06:26:27 PM PDT 24
Finished	Jun 23 06:28:22 PM PDT 24
Peak memory	369172 kb
Host	smart-7de0c6b4-64e5-4670-90a4-5db710006509
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494726658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.3494726658
Directory	/workspace/24.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3494666678
Short name	T708
Test name
Test status
Simulation time	16689047492 ps
CPU time	417.65 seconds
Started	Jun 23 06:26:27 PM PDT 24
Finished	Jun 23 06:33:25 PM PDT 24
Peak memory	203132 kb
Host	smart-5f3f7321-13c7-43a8-9a6a-da7d1c1ffa5c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494666678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.3494666678
Directory	/workspace/24.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/24.sram_ctrl_ram_cfg.2137580274
Short name	T672
Test name
Test status
Simulation time	50820028 ps
CPU time	0.79 seconds
Started	Jun 23 06:26:27 PM PDT 24
Finished	Jun 23 06:26:28 PM PDT 24
Peak memory	203076 kb
Host	smart-1ed57a7a-e5ac-424c-8cea-0b200596a255
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137580274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2137580274
Directory	/workspace/24.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/24.sram_ctrl_regwen.898114056
Short name	T786
Test name
Test status
Simulation time	38333286159 ps
CPU time	978.39 seconds
Started	Jun 23 06:26:28 PM PDT 24
Finished	Jun 23 06:42:46 PM PDT 24
Peak memory	375448 kb
Host	smart-42a0ffec-a369-45f1-9eb7-fa4891cb4303
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898114056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.898114056
Directory	/workspace/24.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/24.sram_ctrl_smoke.3590640678
Short name	T525
Test name
Test status
Simulation time	458082913 ps
CPU time	8 seconds
Started	Jun 23 06:26:27 PM PDT 24
Finished	Jun 23 06:26:36 PM PDT 24
Peak memory	203104 kb
Host	smart-ad870132-0c1b-4953-a205-706e94c09f4a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590640678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3590640678
Directory	/workspace/24.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all.3221937795
Short name	T67
Test name
Test status
Simulation time	7862482648 ps
CPU time	2309.78 seconds
Started	Jun 23 06:26:30 PM PDT 24
Finished	Jun 23 07:05:01 PM PDT 24
Peak memory	369816 kb
Host	smart-6f7da6ba-0807-4611-8bbe-7a66cfd28553
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221937795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.3221937795
Directory	/workspace/24.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2554352
Short name	T502
Test name
Test status
Simulation time	7292795428 ps
CPU time	223.57 seconds
Started	Jun 23 06:26:31 PM PDT 24
Finished	Jun 23 06:30:15 PM PDT 24
Peak memory	368240 kb
Host	smart-b11150f5-9dd1-4e1a-8233-2cd3e60cf7b1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2554352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2554352
Directory	/workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1141601747
Short name	T240
Test name
Test status
Simulation time	8356059492 ps
CPU time	399.47 seconds
Started	Jun 23 06:26:24 PM PDT 24
Finished	Jun 23 06:33:04 PM PDT 24
Peak memory	203144 kb
Host	smart-a7137b6d-035c-4de5-9342-b80bb66ba02b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141601747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.1141601747
Directory	/workspace/24.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1412254350
Short name	T576
Test name
Test status
Simulation time	87526762 ps
CPU time	11.2 seconds
Started	Jun 23 06:26:27 PM PDT 24
Finished	Jun 23 06:26:39 PM PDT 24
Peak memory	252040 kb
Host	smart-4c052928-89d5-48e4-9c35-d458a22b4466
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412254350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1412254350
Directory	/workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2799485790
Short name	T387
Test name
Test status
Simulation time	3532195173 ps
CPU time	1613.9 seconds
Started	Jun 23 06:26:31 PM PDT 24
Finished	Jun 23 06:53:26 PM PDT 24
Peak memory	374672 kb
Host	smart-a0fba599-e7d4-4da7-aa5c-4b4aaa90c0fa
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799485790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2799485790
Directory	/workspace/25.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/25.sram_ctrl_alert_test.1659859248
Short name	T242
Test name
Test status
Simulation time	13718610 ps
CPU time	0.65 seconds
Started	Jun 23 06:26:40 PM PDT 24
Finished	Jun 23 06:26:42 PM PDT 24
Peak memory	202944 kb
Host	smart-f3be048c-ac15-429a-8838-273376728700
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659859248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1659859248
Directory	/workspace/25.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.sram_ctrl_bijection.3521327486
Short name	T348
Test name
Test status
Simulation time	3292196918 ps
CPU time	53.71 seconds
Started	Jun 23 06:26:32 PM PDT 24
Finished	Jun 23 06:27:26 PM PDT 24
Peak memory	203204 kb
Host	smart-edce3407-73d0-4369-bb03-a71593243e59
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521327486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .3521327486
Directory	/workspace/25.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/25.sram_ctrl_executable.3973515926
Short name	T270
Test name
Test status
Simulation time	9051988457 ps
CPU time	807.18 seconds
Started	Jun 23 06:26:31 PM PDT 24
Finished	Jun 23 06:39:58 PM PDT 24
Peak memory	369924 kb
Host	smart-dc3daa04-a35b-4ede-9cad-bb9185e82023
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973515926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.3973515926
Directory	/workspace/25.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/25.sram_ctrl_lc_escalation.2007948747
Short name	T169
Test name
Test status
Simulation time	454131526 ps
CPU time	5.29 seconds
Started	Jun 23 06:26:31 PM PDT 24
Finished	Jun 23 06:26:36 PM PDT 24
Peak memory	203316 kb
Host	smart-838c1d23-5980-4879-8ac9-ffe9ef8a3171
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007948747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.2007948747
Directory	/workspace/25.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/25.sram_ctrl_max_throughput.348492859
Short name	T446
Test name
Test status
Simulation time	140307596 ps
CPU time	135.37 seconds
Started	Jun 23 06:26:33 PM PDT 24
Finished	Jun 23 06:28:49 PM PDT 24
Peak memory	369704 kb
Host	smart-7e7348ea-5e42-4d33-bf35-1a8d102a8bde
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348492859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.sram_ctrl_max_throughput.348492859
Directory	/workspace/25.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.694133283
Short name	T554
Test name
Test status
Simulation time	193014476 ps
CPU time	5.62 seconds
Started	Jun 23 06:26:30 PM PDT 24
Finished	Jun 23 06:26:36 PM PDT 24
Peak memory	211280 kb
Host	smart-fe94123d-ec7b-43cb-8842-0a04b118f871
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694133283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_mem_partial_access.694133283
Directory	/workspace/25.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_walk.4061309590
Short name	T824
Test name
Test status
Simulation time	233952941 ps
CPU time	5.4 seconds
Started	Jun 23 06:26:32 PM PDT 24
Finished	Jun 23 06:26:38 PM PDT 24
Peak memory	203112 kb
Host	smart-75b21090-2fbd-4d28-b816-ae74eec91904
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061309590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.4061309590
Directory	/workspace/25.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/25.sram_ctrl_multiple_keys.1909959925
Short name	T269
Test name
Test status
Simulation time	16294707432 ps
CPU time	785.4 seconds
Started	Jun 23 06:26:34 PM PDT 24
Finished	Jun 23 06:39:40 PM PDT 24
Peak memory	374580 kb
Host	smart-62df1bdb-f922-44fc-ae07-bc33a0639f81
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909959925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.1909959925
Directory	/workspace/25.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access.3058423531
Short name	T766
Test name
Test status
Simulation time	417061920 ps
CPU time	4.52 seconds
Started	Jun 23 06:26:33 PM PDT 24
Finished	Jun 23 06:26:38 PM PDT 24
Peak memory	217516 kb
Host	smart-8a70df4f-7c66-45fd-8658-972e0cd03e74
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058423531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3058423531
Directory	/workspace/25.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2412458067
Short name	T246
Test name
Test status
Simulation time	12621614361 ps
CPU time	227.88 seconds
Started	Jun 23 06:26:34 PM PDT 24
Finished	Jun 23 06:30:23 PM PDT 24
Peak memory	203148 kb
Host	smart-362f3ec6-99f1-44c6-8712-a54aa105ab93
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412458067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.2412458067
Directory	/workspace/25.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/25.sram_ctrl_ram_cfg.4194116460
Short name	T763
Test name
Test status
Simulation time	46708991 ps
CPU time	0.76 seconds
Started	Jun 23 06:26:31 PM PDT 24
Finished	Jun 23 06:26:32 PM PDT 24
Peak memory	203124 kb
Host	smart-c499027f-95f5-418f-9b88-91850496a441
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194116460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.4194116460
Directory	/workspace/25.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/25.sram_ctrl_regwen.2081289360
Short name	T427
Test name
Test status
Simulation time	10084797526 ps
CPU time	766.32 seconds
Started	Jun 23 06:26:32 PM PDT 24
Finished	Jun 23 06:39:19 PM PDT 24
Peak memory	374320 kb
Host	smart-f07ab90b-2527-4c2e-ae38-a7948dfc2da8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081289360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2081289360
Directory	/workspace/25.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/25.sram_ctrl_smoke.3489628264
Short name	T663
Test name
Test status
Simulation time	943472217 ps
CPU time	15.32 seconds
Started	Jun 23 06:26:32 PM PDT 24
Finished	Jun 23 06:26:48 PM PDT 24
Peak memory	203064 kb
Host	smart-9466ebfc-eac1-43e2-8005-f0a4de814e58
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489628264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3489628264
Directory	/workspace/25.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all.2158124865
Short name	T635
Test name
Test status
Simulation time	49381645393 ps
CPU time	2911.96 seconds
Started	Jun 23 06:26:38 PM PDT 24
Finished	Jun 23 07:15:11 PM PDT 24
Peak memory	375896 kb
Host	smart-5a9a7df7-75e3-47a3-8541-7eccab9b004e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158124865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.2158124865
Directory	/workspace/25.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2753074531
Short name	T443
Test name
Test status
Simulation time	8948066010 ps
CPU time	209.85 seconds
Started	Jun 23 06:26:32 PM PDT 24
Finished	Jun 23 06:30:02 PM PDT 24
Peak memory	276728 kb
Host	smart-18804cb8-ec00-467c-9641-86098b4094c2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2753074531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2753074531
Directory	/workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.4278679271
Short name	T755
Test name
Test status
Simulation time	17382533115 ps
CPU time	410.78 seconds
Started	Jun 23 06:26:31 PM PDT 24
Finished	Jun 23 06:33:22 PM PDT 24
Peak memory	203132 kb
Host	smart-9d55d7e8-b9ae-4fcb-9b19-b3ce5b3ddb14
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278679271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.4278679271
Directory	/workspace/25.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.231682301
Short name	T295
Test name
Test status
Simulation time	284422988 ps
CPU time	79.09 seconds
Started	Jun 23 06:26:32 PM PDT 24
Finished	Jun 23 06:27:51 PM PDT 24
Peak memory	328000 kb
Host	smart-b847c781-e3aa-42bf-99ae-8fe646342cd9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231682301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.231682301
Directory	/workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.1074674387
Short name	T369
Test name
Test status
Simulation time	39479697317 ps
CPU time	568.67 seconds
Started	Jun 23 06:26:38 PM PDT 24
Finished	Jun 23 06:36:08 PM PDT 24
Peak memory	363600 kb
Host	smart-313e3810-8303-4263-b9d5-5f65e05ef451
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074674387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.1074674387
Directory	/workspace/26.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/26.sram_ctrl_alert_test.759757739
Short name	T835
Test name
Test status
Simulation time	38677867 ps
CPU time	0.66 seconds
Started	Jun 23 06:26:42 PM PDT 24
Finished	Jun 23 06:26:43 PM PDT 24
Peak memory	202904 kb
Host	smart-d48dc703-f29c-4275-bf9a-c94eedc62c4a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759757739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.759757739
Directory	/workspace/26.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.sram_ctrl_bijection.1835101312
Short name	T828
Test name
Test status
Simulation time	2851247617 ps
CPU time	68.96 seconds
Started	Jun 23 06:26:35 PM PDT 24
Finished	Jun 23 06:27:45 PM PDT 24
Peak memory	203112 kb
Host	smart-f623160b-b100-4ea8-ba6b-bd215466f646
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835101312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .1835101312
Directory	/workspace/26.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/26.sram_ctrl_executable.4275738173
Short name	T377
Test name
Test status
Simulation time	4318835835 ps
CPU time	217.65 seconds
Started	Jun 23 06:26:38 PM PDT 24
Finished	Jun 23 06:30:16 PM PDT 24
Peak memory	349460 kb
Host	smart-f1545c3e-8acd-468b-80b3-6f54fb5079f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275738173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.4275738173
Directory	/workspace/26.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/26.sram_ctrl_lc_escalation.3678808045
Short name	T281
Test name
Test status
Simulation time	527809392 ps
CPU time	5.4 seconds
Started	Jun 23 06:26:35 PM PDT 24
Finished	Jun 23 06:26:41 PM PDT 24
Peak memory	211264 kb
Host	smart-caffee65-71ea-4e3f-aca8-7eb7bec4ce05
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678808045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.3678808045
Directory	/workspace/26.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/26.sram_ctrl_max_throughput.104333782
Short name	T476
Test name
Test status
Simulation time	564944465 ps
CPU time	1.65 seconds
Started	Jun 23 06:26:37 PM PDT 24
Finished	Jun 23 06:26:40 PM PDT 24
Peak memory	211264 kb
Host	smart-750dccc5-13d9-402b-b62a-ad74d1f8ac3c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104333782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.sram_ctrl_max_throughput.104333782
Directory	/workspace/26.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1361387558
Short name	T535
Test name
Test status
Simulation time	106917619 ps
CPU time	3.12 seconds
Started	Jun 23 06:26:41 PM PDT 24
Finished	Jun 23 06:26:45 PM PDT 24
Peak memory	211272 kb
Host	smart-6476b37a-11e6-4c06-a37d-8f62a935fcc7
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361387558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.1361387558
Directory	/workspace/26.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_walk.3088524504
Short name	T840
Test name
Test status
Simulation time	2728815910 ps
CPU time	11.26 seconds
Started	Jun 23 06:26:41 PM PDT 24
Finished	Jun 23 06:26:54 PM PDT 24
Peak memory	211392 kb
Host	smart-94bb6365-ff0a-4e55-8e76-e43caa98f404
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088524504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.3088524504
Directory	/workspace/26.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/26.sram_ctrl_multiple_keys.3398671825
Short name	T658
Test name
Test status
Simulation time	2895398236 ps
CPU time	935.81 seconds
Started	Jun 23 06:26:36 PM PDT 24
Finished	Jun 23 06:42:12 PM PDT 24
Peak memory	359632 kb
Host	smart-8b74b48f-2ab3-481b-9c1c-64b6ecb0d471
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398671825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.3398671825
Directory	/workspace/26.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access.394665099
Short name	T166
Test name
Test status
Simulation time	227627812 ps
CPU time	153.09 seconds
Started	Jun 23 06:26:38 PM PDT 24
Finished	Jun 23 06:29:11 PM PDT 24
Peak memory	366528 kb
Host	smart-bf92dabc-c6e0-4064-90c5-7a6fd1811ea9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394665099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s ram_ctrl_partial_access.394665099
Directory	/workspace/26.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1073275722
Short name	T483
Test name
Test status
Simulation time	155728979650 ps
CPU time	338.92 seconds
Started	Jun 23 06:26:35 PM PDT 24
Finished	Jun 23 06:32:14 PM PDT 24
Peak memory	203100 kb
Host	smart-e4a2e41f-4a36-4daa-960a-47458de49f83
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073275722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.1073275722
Directory	/workspace/26.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/26.sram_ctrl_ram_cfg.424553840
Short name	T186
Test name
Test status
Simulation time	74916054 ps
CPU time	0.78 seconds
Started	Jun 23 06:26:38 PM PDT 24
Finished	Jun 23 06:26:39 PM PDT 24
Peak memory	203120 kb
Host	smart-7ca74ccf-bfa8-42c6-8658-459db7acaeec
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424553840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.424553840
Directory	/workspace/26.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/26.sram_ctrl_regwen.3197345608
Short name	T889
Test name
Test status
Simulation time	1416804044 ps
CPU time	28.39 seconds
Started	Jun 23 06:26:37 PM PDT 24
Finished	Jun 23 06:27:06 PM PDT 24
Peak memory	203032 kb
Host	smart-aca48db7-cad4-419e-b809-7afef9f2efa7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197345608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3197345608
Directory	/workspace/26.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/26.sram_ctrl_smoke.1788273410
Short name	T157
Test name
Test status
Simulation time	78537006 ps
CPU time	4.96 seconds
Started	Jun 23 06:26:38 PM PDT 24
Finished	Jun 23 06:26:43 PM PDT 24
Peak memory	225552 kb
Host	smart-aec6c883-a06f-45db-a16e-f9e1ae69bb83
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788273410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1788273410
Directory	/workspace/26.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all.1812047516
Short name	T456
Test name
Test status
Simulation time	55599414403 ps
CPU time	1873.98 seconds
Started	Jun 23 06:26:41 PM PDT 24
Finished	Jun 23 06:57:57 PM PDT 24
Peak memory	373808 kb
Host	smart-4f16bb86-0598-4687-a66e-e821f7d16826
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812047516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.1812047516
Directory	/workspace/26.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1837458152
Short name	T827
Test name
Test status
Simulation time	443297225 ps
CPU time	321 seconds
Started	Jun 23 06:26:41 PM PDT 24
Finished	Jun 23 06:32:03 PM PDT 24
Peak memory	376824 kb
Host	smart-bf4c6996-4f08-4422-9c5f-0a379838d0da
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1837458152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1837458152
Directory	/workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.4070726928
Short name	T102
Test name
Test status
Simulation time	3400430633 ps
CPU time	327.32 seconds
Started	Jun 23 06:26:37 PM PDT 24
Finished	Jun 23 06:32:05 PM PDT 24
Peak memory	203152 kb
Host	smart-4a85ef42-4906-4509-876e-53e4374d23f3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070726928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.4070726928
Directory	/workspace/26.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2528491365
Short name	T196
Test name
Test status
Simulation time	170848892 ps
CPU time	23.2 seconds
Started	Jun 23 06:26:37 PM PDT 24
Finished	Jun 23 06:27:00 PM PDT 24
Peak memory	268460 kb
Host	smart-cf5ec523-b9f6-4cb8-8d3e-c29b5c09c832
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528491365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2528491365
Directory	/workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1404044876
Short name	T781
Test name
Test status
Simulation time	5170606180 ps
CPU time	1488.95 seconds
Started	Jun 23 06:26:40 PM PDT 24
Finished	Jun 23 06:51:30 PM PDT 24
Peak memory	371848 kb
Host	smart-f34db78e-6eab-42b9-8f54-3a17039833b0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404044876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.1404044876
Directory	/workspace/27.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/27.sram_ctrl_alert_test.1841444254
Short name	T895
Test name
Test status
Simulation time	17184120 ps
CPU time	0.64 seconds
Started	Jun 23 06:26:45 PM PDT 24
Finished	Jun 23 06:26:46 PM PDT 24
Peak memory	202884 kb
Host	smart-3b154dec-c9fc-4153-ac0b-cf24ead75f6e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841444254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1841444254
Directory	/workspace/27.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.sram_ctrl_bijection.1001082037
Short name	T212
Test name
Test status
Simulation time	15546965757 ps
CPU time	47.17 seconds
Started	Jun 23 06:26:40 PM PDT 24
Finished	Jun 23 06:27:28 PM PDT 24
Peak memory	203144 kb
Host	smart-cb77590a-9f08-4790-b878-7534a40b2cb0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001082037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .1001082037
Directory	/workspace/27.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/27.sram_ctrl_executable.3219513333
Short name	T714
Test name
Test status
Simulation time	19549724083 ps
CPU time	836.62 seconds
Started	Jun 23 06:26:41 PM PDT 24
Finished	Jun 23 06:40:39 PM PDT 24
Peak memory	365324 kb
Host	smart-ab682105-6d75-4b34-a468-ed546d307987
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219513333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.3219513333
Directory	/workspace/27.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/27.sram_ctrl_lc_escalation.616501328
Short name	T634
Test name
Test status
Simulation time	346706108 ps
CPU time	5.31 seconds
Started	Jun 23 06:26:42 PM PDT 24
Finished	Jun 23 06:26:48 PM PDT 24
Peak memory	203228 kb
Host	smart-c7600e72-ce5c-4f34-9137-ea66d542a189
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616501328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_esc alation.616501328
Directory	/workspace/27.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/27.sram_ctrl_max_throughput.3364782834
Short name	T880
Test name
Test status
Simulation time	507118926 ps
CPU time	126 seconds
Started	Jun 23 06:26:43 PM PDT 24
Finished	Jun 23 06:28:49 PM PDT 24
Peak memory	357472 kb
Host	smart-c7992a80-24b2-43f3-bb99-dbdb695e40ad
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364782834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.3364782834
Directory	/workspace/27.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1094847948
Short name	T8
Test name
Test status
Simulation time	47487996 ps
CPU time	2.72 seconds
Started	Jun 23 06:26:40 PM PDT 24
Finished	Jun 23 06:26:44 PM PDT 24
Peak memory	211300 kb
Host	smart-b99c6edf-55a9-4af9-a28d-4da716a30b4f
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094847948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.1094847948
Directory	/workspace/27.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_walk.3799106719
Short name	T402
Test name
Test status
Simulation time	988047205 ps
CPU time	4.59 seconds
Started	Jun 23 06:26:42 PM PDT 24
Finished	Jun 23 06:26:48 PM PDT 24
Peak memory	211240 kb
Host	smart-4b7e443f-7180-472a-a982-9127824f24b0
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799106719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.3799106719
Directory	/workspace/27.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/27.sram_ctrl_multiple_keys.4056905491
Short name	T138
Test name
Test status
Simulation time	11288057031 ps
CPU time	672.67 seconds
Started	Jun 23 06:26:40 PM PDT 24
Finished	Jun 23 06:37:53 PM PDT 24
Peak memory	367792 kb
Host	smart-ac0e2b2b-b3eb-4857-b055-a6c58ff69945
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056905491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.4056905491
Directory	/workspace/27.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access.2390313265
Short name	T144
Test name
Test status
Simulation time	508497346 ps
CPU time	5.01 seconds
Started	Jun 23 06:26:41 PM PDT 24
Finished	Jun 23 06:26:47 PM PDT 24
Peak memory	222116 kb
Host	smart-bda5900d-16ba-47ce-88ac-5a41265b2b80
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390313265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.2390313265
Directory	/workspace/27.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1086779355
Short name	T439
Test name
Test status
Simulation time	15195897095 ps
CPU time	399.77 seconds
Started	Jun 23 06:26:42 PM PDT 24
Finished	Jun 23 06:33:23 PM PDT 24
Peak memory	203124 kb
Host	smart-639793fb-6589-4942-aafe-0277f2ff2a4a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086779355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.1086779355
Directory	/workspace/27.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/27.sram_ctrl_ram_cfg.406357063
Short name	T27
Test name
Test status
Simulation time	389573657 ps
CPU time	0.88 seconds
Started	Jun 23 06:26:41 PM PDT 24
Finished	Jun 23 06:26:43 PM PDT 24
Peak memory	203096 kb
Host	smart-ea8e9362-789e-49e2-96e3-3da4cb364311
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406357063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.406357063
Directory	/workspace/27.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/27.sram_ctrl_regwen.3847619109
Short name	T495
Test name
Test status
Simulation time	10984418077 ps
CPU time	775.34 seconds
Started	Jun 23 06:26:42 PM PDT 24
Finished	Jun 23 06:39:38 PM PDT 24
Peak memory	374124 kb
Host	smart-f30ac3ac-9e11-4079-b57d-dd1ef7e57971
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847619109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3847619109
Directory	/workspace/27.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/27.sram_ctrl_smoke.2727024219
Short name	T333
Test name
Test status
Simulation time	557522363 ps
CPU time	9.17 seconds
Started	Jun 23 06:26:42 PM PDT 24
Finished	Jun 23 06:26:52 PM PDT 24
Peak memory	203092 kb
Host	smart-f0e4a64f-1d01-43a2-84e3-dfb187e31665
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727024219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2727024219
Directory	/workspace/27.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3730906685
Short name	T582
Test name
Test status
Simulation time	2912876531 ps
CPU time	1142.93 seconds
Started	Jun 23 06:26:42 PM PDT 24
Finished	Jun 23 06:45:46 PM PDT 24
Peak memory	376968 kb
Host	smart-22583ab4-53dc-48d9-8c61-36d91c421e63
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3730906685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3730906685
Directory	/workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2601479736
Short name	T290
Test name
Test status
Simulation time	14030823847 ps
CPU time	321.69 seconds
Started	Jun 23 06:26:42 PM PDT 24
Finished	Jun 23 06:32:04 PM PDT 24
Peak memory	203168 kb
Host	smart-31e36d8e-a1b0-453d-9f3a-9310affb347d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601479736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.2601479736
Directory	/workspace/27.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2878626408
Short name	T682
Test name
Test status
Simulation time	65233175 ps
CPU time	9.88 seconds
Started	Jun 23 06:26:42 PM PDT 24
Finished	Jun 23 06:26:53 PM PDT 24
Peak memory	242180 kb
Host	smart-22a33165-af8e-440b-b925-8a306d60eff5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878626408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2878626408
Directory	/workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2582044961
Short name	T639
Test name
Test status
Simulation time	19462015802 ps
CPU time	274.9 seconds
Started	Jun 23 06:26:52 PM PDT 24
Finished	Jun 23 06:31:27 PM PDT 24
Peak memory	375208 kb
Host	smart-f5faf7ed-0171-47eb-97e5-6828f5d53413
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582044961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.2582044961
Directory	/workspace/28.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/28.sram_ctrl_alert_test.3651650418
Short name	T368
Test name
Test status
Simulation time	21680974 ps
CPU time	0.65 seconds
Started	Jun 23 06:26:51 PM PDT 24
Finished	Jun 23 06:26:52 PM PDT 24
Peak memory	202864 kb
Host	smart-4af39199-f642-4503-9bf3-f6e20a986d2c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651650418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3651650418
Directory	/workspace/28.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.sram_ctrl_bijection.1717979379
Short name	T396
Test name
Test status
Simulation time	847493644 ps
CPU time	57.11 seconds
Started	Jun 23 06:26:47 PM PDT 24
Finished	Jun 23 06:27:44 PM PDT 24
Peak memory	203108 kb
Host	smart-9f84f0f4-328c-4038-82d0-32847bb21be9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717979379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .1717979379
Directory	/workspace/28.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/28.sram_ctrl_executable.3153938745
Short name	T666
Test name
Test status
Simulation time	7355584390 ps
CPU time	187.79 seconds
Started	Jun 23 06:26:50 PM PDT 24
Finished	Jun 23 06:29:59 PM PDT 24
Peak memory	291092 kb
Host	smart-cdfbeedf-0c6e-47d4-b0dc-94f4e20cfa01
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153938745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.3153938745
Directory	/workspace/28.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/28.sram_ctrl_lc_escalation.645125549
Short name	T432
Test name
Test status
Simulation time	254732124 ps
CPU time	1.3 seconds
Started	Jun 23 06:26:45 PM PDT 24
Finished	Jun 23 06:26:47 PM PDT 24
Peak memory	202916 kb
Host	smart-0fc046c9-2493-491f-bab8-d6f045a9fc85
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645125549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc alation.645125549
Directory	/workspace/28.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/28.sram_ctrl_max_throughput.369827276
Short name	T637
Test name
Test status
Simulation time	153292782 ps
CPU time	3.68 seconds
Started	Jun 23 06:26:50 PM PDT 24
Finished	Jun 23 06:26:54 PM PDT 24
Peak memory	220960 kb
Host	smart-3a843ce3-82aa-4427-a255-cc23b7c46fd9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369827276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.sram_ctrl_max_throughput.369827276
Directory	/workspace/28.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.1085003087
Short name	T90
Test name
Test status
Simulation time	349054040 ps
CPU time	5.08 seconds
Started	Jun 23 06:26:52 PM PDT 24
Finished	Jun 23 06:26:57 PM PDT 24
Peak memory	211336 kb
Host	smart-9cc0e826-89d4-4cef-b5c3-553b549e9f3d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085003087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.1085003087
Directory	/workspace/28.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_walk.79150401
Short name	T774
Test name
Test status
Simulation time	448636831 ps
CPU time	5.51 seconds
Started	Jun 23 06:26:51 PM PDT 24
Finished	Jun 23 06:26:57 PM PDT 24
Peak memory	211288 kb
Host	smart-f98fd244-6667-4c0c-9aaf-5281850f1761
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79150401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ mem_walk.79150401
Directory	/workspace/28.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/28.sram_ctrl_multiple_keys.2508091875
Short name	T552
Test name
Test status
Simulation time	5440183458 ps
CPU time	198.75 seconds
Started	Jun 23 06:26:48 PM PDT 24
Finished	Jun 23 06:30:07 PM PDT 24
Peak memory	339652 kb
Host	smart-83480a83-80e1-47c6-b956-502a97e58411
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508091875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.2508091875
Directory	/workspace/28.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access.1507279708
Short name	T210
Test name
Test status
Simulation time	213447944 ps
CPU time	84.51 seconds
Started	Jun 23 06:26:46 PM PDT 24
Finished	Jun 23 06:28:11 PM PDT 24
Peak memory	351144 kb
Host	smart-096cdd42-2c99-456a-b424-5c917553d111
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507279708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.1507279708
Directory	/workspace/28.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2823683961
Short name	T690
Test name
Test status
Simulation time	11712593370 ps
CPU time	241.37 seconds
Started	Jun 23 06:26:47 PM PDT 24
Finished	Jun 23 06:30:49 PM PDT 24
Peak memory	203088 kb
Host	smart-517da053-ccab-45be-8397-bec791012e90
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823683961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.2823683961
Directory	/workspace/28.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/28.sram_ctrl_ram_cfg.3009192929
Short name	T799
Test name
Test status
Simulation time	27222626 ps
CPU time	0.77 seconds
Started	Jun 23 06:26:50 PM PDT 24
Finished	Jun 23 06:26:51 PM PDT 24
Peak memory	203064 kb
Host	smart-ca6c20ec-72a9-4379-bebc-9f5163f5025a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009192929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3009192929
Directory	/workspace/28.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/28.sram_ctrl_regwen.2462430647
Short name	T217
Test name
Test status
Simulation time	6465887054 ps
CPU time	46.97 seconds
Started	Jun 23 06:26:54 PM PDT 24
Finished	Jun 23 06:27:41 PM PDT 24
Peak memory	250984 kb
Host	smart-ec9c0c7e-a3af-4563-8af8-92deb2ae1da2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462430647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2462430647
Directory	/workspace/28.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/28.sram_ctrl_smoke.3293953398
Short name	T220
Test name
Test status
Simulation time	186596013 ps
CPU time	12.51 seconds
Started	Jun 23 06:26:47 PM PDT 24
Finished	Jun 23 06:27:00 PM PDT 24
Peak memory	247920 kb
Host	smart-9c82c425-c229-4dc5-a966-e07cf04bec33
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293953398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3293953398
Directory	/workspace/28.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all.2841985864
Short name	T308
Test name
Test status
Simulation time	59405334549 ps
CPU time	6154.53 seconds
Started	Jun 23 06:26:51 PM PDT 24
Finished	Jun 23 08:09:26 PM PDT 24
Peak memory	376992 kb
Host	smart-67e099da-6bf2-48ef-b68b-326de45a97cd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841985864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.2841985864
Directory	/workspace/28.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2510390202
Short name	T277
Test name
Test status
Simulation time	8688572749 ps
CPU time	202.74 seconds
Started	Jun 23 06:26:45 PM PDT 24
Finished	Jun 23 06:30:09 PM PDT 24
Peak memory	203140 kb
Host	smart-0b1ac3b8-4d67-4c81-a636-e6f8e87c0f7c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510390202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.2510390202
Directory	/workspace/28.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.761865192
Short name	T772
Test name
Test status
Simulation time	140015315 ps
CPU time	89.06 seconds
Started	Jun 23 06:26:46 PM PDT 24
Finished	Jun 23 06:28:15 PM PDT 24
Peak memory	348620 kb
Host	smart-2c3902bf-8cef-493b-82fa-a87595e7b85e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761865192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_throughput_w_partial_write.761865192
Directory	/workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2332096055
Short name	T423
Test name
Test status
Simulation time	4751644723 ps
CPU time	1751.93 seconds
Started	Jun 23 06:26:57 PM PDT 24
Finished	Jun 23 06:56:09 PM PDT 24
Peak memory	374992 kb
Host	smart-c0e3b255-346b-4e41-8221-bd3d56796974
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332096055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.2332096055
Directory	/workspace/29.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/29.sram_ctrl_alert_test.558053990
Short name	T894
Test name
Test status
Simulation time	45704811 ps
CPU time	0.66 seconds
Started	Jun 23 06:26:57 PM PDT 24
Finished	Jun 23 06:26:57 PM PDT 24
Peak memory	202932 kb
Host	smart-3853e024-c20b-458c-8a76-a6ad707b4c67
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558053990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.558053990
Directory	/workspace/29.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.sram_ctrl_bijection.444808469
Short name	T870
Test name
Test status
Simulation time	1369415053 ps
CPU time	26.83 seconds
Started	Jun 23 06:26:50 PM PDT 24
Finished	Jun 23 06:27:18 PM PDT 24
Peak memory	203112 kb
Host	smart-dec6bfb8-dece-45ec-a201-bc13e293f9fa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444808469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection. 444808469
Directory	/workspace/29.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/29.sram_ctrl_lc_escalation.251410357
Short name	T174
Test name
Test status
Simulation time	2351461315 ps
CPU time	6.25 seconds
Started	Jun 23 06:26:54 PM PDT 24
Finished	Jun 23 06:27:01 PM PDT 24
Peak memory	214996 kb
Host	smart-84d107ce-3784-4d8a-a038-f078f669b93a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251410357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esc alation.251410357
Directory	/workspace/29.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/29.sram_ctrl_max_throughput.4223399209
Short name	T844
Test name
Test status
Simulation time	136724385 ps
CPU time	98.52 seconds
Started	Jun 23 06:26:56 PM PDT 24
Finished	Jun 23 06:28:35 PM PDT 24
Peak memory	350528 kb
Host	smart-7819a1d5-308c-4d8a-a999-0960a3dc44fd
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223399209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.4223399209
Directory	/workspace/29.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2240698272
Short name	T679
Test name
Test status
Simulation time	950781888 ps
CPU time	3.64 seconds
Started	Jun 23 06:26:59 PM PDT 24
Finished	Jun 23 06:27:03 PM PDT 24
Peak memory	211308 kb
Host	smart-d2bddff2-0ec1-44c1-beb4-12dc28360bf6
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240698272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.2240698272
Directory	/workspace/29.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_walk.911766443
Short name	T618
Test name
Test status
Simulation time	296002658 ps
CPU time	6.08 seconds
Started	Jun 23 06:26:54 PM PDT 24
Finished	Jun 23 06:27:01 PM PDT 24
Peak memory	211284 kb
Host	smart-6acd8a8b-1de1-4df7-bfa9-8ac5b91751fa
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911766443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _mem_walk.911766443
Directory	/workspace/29.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/29.sram_ctrl_multiple_keys.870995016
Short name	T230
Test name
Test status
Simulation time	14224945021 ps
CPU time	1482.45 seconds
Started	Jun 23 06:26:53 PM PDT 24
Finished	Jun 23 06:51:36 PM PDT 24
Peak memory	373936 kb
Host	smart-bd374221-7d49-4bbc-92dc-ed726e070126
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870995016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip le_keys.870995016
Directory	/workspace/29.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access.2930267106
Short name	T294
Test name
Test status
Simulation time	410739957 ps
CPU time	37.66 seconds
Started	Jun 23 06:26:51 PM PDT 24
Finished	Jun 23 06:27:29 PM PDT 24
Peak memory	297332 kb
Host	smart-ac2ee30d-40ce-4e3a-b9f0-daa2f5c3210d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930267106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.2930267106
Directory	/workspace/29.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.281145163
Short name	T831
Test name
Test status
Simulation time	12011584155 ps
CPU time	222.7 seconds
Started	Jun 23 06:26:49 PM PDT 24
Finished	Jun 23 06:30:32 PM PDT 24
Peak memory	203080 kb
Host	smart-92836b9a-b14d-4d5c-b2bb-b5213ff280eb
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281145163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.sram_ctrl_partial_access_b2b.281145163
Directory	/workspace/29.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/29.sram_ctrl_ram_cfg.2788670957
Short name	T232
Test name
Test status
Simulation time	29100670 ps
CPU time	0.8 seconds
Started	Jun 23 06:26:58 PM PDT 24
Finished	Jun 23 06:26:59 PM PDT 24
Peak memory	203088 kb
Host	smart-00d40595-c02a-4067-a617-0e986357bddd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788670957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2788670957
Directory	/workspace/29.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/29.sram_ctrl_regwen.1906034970
Short name	T504
Test name
Test status
Simulation time	127193272250 ps
CPU time	1340.26 seconds
Started	Jun 23 06:26:54 PM PDT 24
Finished	Jun 23 06:49:15 PM PDT 24
Peak memory	374964 kb
Host	smart-fe4f7d44-db0f-4127-a069-b0e782765dd5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906034970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1906034970
Directory	/workspace/29.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/29.sram_ctrl_smoke.3027651291
Short name	T821
Test name
Test status
Simulation time	3138124453 ps
CPU time	11.07 seconds
Started	Jun 23 06:26:50 PM PDT 24
Finished	Jun 23 06:27:02 PM PDT 24
Peak memory	203168 kb
Host	smart-4ce2f2ec-dcd6-4e6c-8b5f-dc1d31dfaaed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027651291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3027651291
Directory	/workspace/29.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all.758846177
Short name	T715
Test name
Test status
Simulation time	26756530431 ps
CPU time	2031.04 seconds
Started	Jun 23 06:26:59 PM PDT 24
Finished	Jun 23 07:00:51 PM PDT 24
Peak memory	375116 kb
Host	smart-fe8b359e-ee65-430a-a6ab-46c654d42010
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758846177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_stress_all.758846177
Directory	/workspace/29.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3045342807
Short name	T69
Test name
Test status
Simulation time	645425453 ps
CPU time	29.09 seconds
Started	Jun 23 06:26:54 PM PDT 24
Finished	Jun 23 06:27:24 PM PDT 24
Peak memory	211368 kb
Host	smart-b8ec7151-800a-44a8-93c8-1d1d08662b05
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3045342807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3045342807
Directory	/workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3139817410
Short name	T30
Test name
Test status
Simulation time	4275177303 ps
CPU time	254.34 seconds
Started	Jun 23 06:26:50 PM PDT 24
Finished	Jun 23 06:31:04 PM PDT 24
Peak memory	203108 kb
Host	smart-1b77c3ef-d17d-47ae-a1ad-0ac4c424e0b0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139817410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3139817410
Directory	/workspace/29.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.447079762
Short name	T913
Test name
Test status
Simulation time	1825576038 ps
CPU time	128.95 seconds
Started	Jun 23 06:26:54 PM PDT 24
Finished	Jun 23 06:29:03 PM PDT 24
Peak memory	367232 kb
Host	smart-63454902-7a53-4d04-a938-626508b07b47
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447079762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_throughput_w_partial_write.447079762
Directory	/workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1589219255
Short name	T819
Test name
Test status
Simulation time	2168664209 ps
CPU time	184.74 seconds
Started	Jun 23 06:24:41 PM PDT 24
Finished	Jun 23 06:27:46 PM PDT 24
Peak memory	343596 kb
Host	smart-3ca0e5fa-21af-4d65-8b1c-9a55c9e586c7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589219255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.1589219255
Directory	/workspace/3.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/3.sram_ctrl_alert_test.961321412
Short name	T699
Test name
Test status
Simulation time	45036465 ps
CPU time	0.65 seconds
Started	Jun 23 06:24:44 PM PDT 24
Finished	Jun 23 06:24:45 PM PDT 24
Peak memory	202852 kb
Host	smart-7cb39866-309b-45cd-a692-718085089500
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961321412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.961321412
Directory	/workspace/3.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.sram_ctrl_bijection.2946678314
Short name	T323
Test name
Test status
Simulation time	1072557900 ps
CPU time	71.34 seconds
Started	Jun 23 06:24:34 PM PDT 24
Finished	Jun 23 06:25:45 PM PDT 24
Peak memory	203048 kb
Host	smart-8627e115-4173-4432-8255-d91f31e87289
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946678314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 2946678314
Directory	/workspace/3.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/3.sram_ctrl_executable.1914282687
Short name	T776
Test name
Test status
Simulation time	9635055797 ps
CPU time	616.3 seconds
Started	Jun 23 06:24:43 PM PDT 24
Finished	Jun 23 06:35:00 PM PDT 24
Peak memory	369868 kb
Host	smart-2ebf78ff-22c9-46c9-a697-922a30dec88d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914282687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.1914282687
Directory	/workspace/3.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/3.sram_ctrl_lc_escalation.2034562980
Short name	T306
Test name
Test status
Simulation time	1144740730 ps
CPU time	6.3 seconds
Started	Jun 23 06:24:43 PM PDT 24
Finished	Jun 23 06:24:50 PM PDT 24
Peak memory	203004 kb
Host	smart-f90d4e06-809f-486b-8230-dfe6805e8721
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034562980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.2034562980
Directory	/workspace/3.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/3.sram_ctrl_max_throughput.4191782447
Short name	T580
Test name
Test status
Simulation time	805100314 ps
CPU time	6.24 seconds
Started	Jun 23 06:24:36 PM PDT 24
Finished	Jun 23 06:24:43 PM PDT 24
Peak memory	235404 kb
Host	smart-d5e6b2e2-1c8e-42b2-a557-0daf627d7267
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191782447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.4191782447
Directory	/workspace/3.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.4005824624
Short name	T645
Test name
Test status
Simulation time	99336610 ps
CPU time	3.36 seconds
Started	Jun 23 06:24:40 PM PDT 24
Finished	Jun 23 06:24:44 PM PDT 24
Peak memory	211216 kb
Host	smart-e1f2eedf-50b4-4810-8801-798208603e05
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005824624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.4005824624
Directory	/workspace/3.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_walk.2891768276
Short name	T376
Test name
Test status
Simulation time	901478769 ps
CPU time	10.66 seconds
Started	Jun 23 06:24:39 PM PDT 24
Finished	Jun 23 06:24:50 PM PDT 24
Peak memory	211248 kb
Host	smart-a41d86fc-80fa-4a91-b34c-6859619cf297
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891768276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.2891768276
Directory	/workspace/3.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/3.sram_ctrl_multiple_keys.1233627245
Short name	T183
Test name
Test status
Simulation time	16011923316 ps
CPU time	821.6 seconds
Started	Jun 23 06:24:39 PM PDT 24
Finished	Jun 23 06:38:21 PM PDT 24
Peak memory	363952 kb
Host	smart-73297b07-8c68-4ed5-a77a-fb87ae46f0ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233627245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.1233627245
Directory	/workspace/3.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access.543398738
Short name	T192
Test name
Test status
Simulation time	994072846 ps
CPU time	19.05 seconds
Started	Jun 23 06:24:37 PM PDT 24
Finished	Jun 23 06:24:56 PM PDT 24
Peak memory	203100 kb
Host	smart-e0ea1cdb-cd8c-4dc8-9dce-04865f9379ab
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543398738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr am_ctrl_partial_access.543398738
Directory	/workspace/3.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.249585398
Short name	T286
Test name
Test status
Simulation time	2465964768 ps
CPU time	161.92 seconds
Started	Jun 23 06:24:36 PM PDT 24
Finished	Jun 23 06:27:18 PM PDT 24
Peak memory	203156 kb
Host	smart-d5f1c23a-3884-49e7-97b7-2cc816c1c264
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249585398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 3.sram_ctrl_partial_access_b2b.249585398
Directory	/workspace/3.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/3.sram_ctrl_ram_cfg.2282576440
Short name	T773
Test name
Test status
Simulation time	84288989 ps
CPU time	0.77 seconds
Started	Jun 23 06:24:41 PM PDT 24
Finished	Jun 23 06:24:42 PM PDT 24
Peak memory	203120 kb
Host	smart-74af18b3-e60d-4ad1-ac54-e002a5c43823
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282576440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2282576440
Directory	/workspace/3.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/3.sram_ctrl_regwen.912898166
Short name	T130
Test name
Test status
Simulation time	19111159033 ps
CPU time	1463.17 seconds
Started	Jun 23 06:24:40 PM PDT 24
Finished	Jun 23 06:49:04 PM PDT 24
Peak memory	375888 kb
Host	smart-becef970-eae5-4a60-bb66-6f2c28799314
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912898166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.912898166
Directory	/workspace/3.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/3.sram_ctrl_sec_cm.2020451910
Short name	T16
Test name
Test status
Simulation time	306059359 ps
CPU time	2.05 seconds
Started	Jun 23 06:24:42 PM PDT 24
Finished	Jun 23 06:24:44 PM PDT 24
Peak memory	222004 kb
Host	smart-11bc814c-28be-497a-9e0b-c8374edddd35
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020451910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.2020451910
Directory	/workspace/3.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.sram_ctrl_smoke.2836483145
Short name	T571
Test name
Test status
Simulation time	542457872 ps
CPU time	8.67 seconds
Started	Jun 23 06:24:39 PM PDT 24
Finished	Jun 23 06:24:48 PM PDT 24
Peak memory	203112 kb
Host	smart-f00a8a64-b727-461e-8f7d-073116ce9fcb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836483145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2836483145
Directory	/workspace/3.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all.2636921347
Short name	T681
Test name
Test status
Simulation time	204041169047 ps
CPU time	2681.28 seconds
Started	Jun 23 06:24:39 PM PDT 24
Finished	Jun 23 07:09:21 PM PDT 24
Peak memory	375964 kb
Host	smart-cabf0145-0e0c-4489-9d81-3d420ae7a9a3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636921347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.2636921347
Directory	/workspace/3.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2827357229
Short name	T893
Test name
Test status
Simulation time	4410892406 ps
CPU time	324.18 seconds
Started	Jun 23 06:24:38 PM PDT 24
Finished	Jun 23 06:30:03 PM PDT 24
Peak memory	355668 kb
Host	smart-2ff87cdc-6ab4-4c4e-beb2-e516bc60940a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2827357229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2827357229
Directory	/workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1129321789
Short name	T304
Test name
Test status
Simulation time	4359138758 ps
CPU time	106.99 seconds
Started	Jun 23 06:24:35 PM PDT 24
Finished	Jun 23 06:26:23 PM PDT 24
Peak memory	203168 kb
Host	smart-117b0713-c1de-44e2-9334-f03ec847e62c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129321789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.1129321789
Directory	/workspace/3.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.145491145
Short name	T670
Test name
Test status
Simulation time	156433801 ps
CPU time	2.48 seconds
Started	Jun 23 06:24:35 PM PDT 24
Finished	Jun 23 06:24:38 PM PDT 24
Peak memory	219068 kb
Host	smart-2552597a-dfa2-4942-b562-51848622a946
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145491145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.145491145
Directory	/workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2281542996
Short name	T770
Test name
Test status
Simulation time	2107166337 ps
CPU time	231.44 seconds
Started	Jun 23 06:27:03 PM PDT 24
Finished	Jun 23 06:30:55 PM PDT 24
Peak memory	363524 kb
Host	smart-c3762631-b242-4d09-8363-99a7caf37be0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281542996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.2281542996
Directory	/workspace/30.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/30.sram_ctrl_alert_test.382862871
Short name	T312
Test name
Test status
Simulation time	38382920 ps
CPU time	0.66 seconds
Started	Jun 23 06:27:06 PM PDT 24
Finished	Jun 23 06:27:07 PM PDT 24
Peak memory	202944 kb
Host	smart-15393a6a-caf3-41cd-84a2-baafb194c275
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382862871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.382862871
Directory	/workspace/30.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.sram_ctrl_bijection.3218041399
Short name	T868
Test name
Test status
Simulation time	4452631528 ps
CPU time	73.11 seconds
Started	Jun 23 06:26:59 PM PDT 24
Finished	Jun 23 06:28:13 PM PDT 24
Peak memory	203124 kb
Host	smart-6d55d734-e0d1-49ce-9e4c-633a06354485
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218041399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .3218041399
Directory	/workspace/30.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/30.sram_ctrl_executable.4169779902
Short name	T872
Test name
Test status
Simulation time	12038592329 ps
CPU time	554.45 seconds
Started	Jun 23 06:27:03 PM PDT 24
Finished	Jun 23 06:36:18 PM PDT 24
Peak memory	370556 kb
Host	smart-32edb33a-236f-4d4d-8b53-ea4cd6d3ca83
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169779902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.4169779902
Directory	/workspace/30.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/30.sram_ctrl_lc_escalation.1926272743
Short name	T6
Test name
Test status
Simulation time	1752233367 ps
CPU time	6.93 seconds
Started	Jun 23 06:27:00 PM PDT 24
Finished	Jun 23 06:27:08 PM PDT 24
Peak memory	203020 kb
Host	smart-d5ea22fd-d900-4134-a29a-7be4c4350bd4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926272743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.1926272743
Directory	/workspace/30.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/30.sram_ctrl_max_throughput.1029715115
Short name	T340
Test name
Test status
Simulation time	77877661 ps
CPU time	2.14 seconds
Started	Jun 23 06:26:58 PM PDT 24
Finished	Jun 23 06:27:01 PM PDT 24
Peak memory	212332 kb
Host	smart-eff25294-a9ac-432f-aaad-2a7bcf89422a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029715115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.1029715115
Directory	/workspace/30.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3387154178
Short name	T675
Test name
Test status
Simulation time	46374395 ps
CPU time	2.6 seconds
Started	Jun 23 06:27:04 PM PDT 24
Finished	Jun 23 06:27:07 PM PDT 24
Peak memory	211280 kb
Host	smart-35cb9ec4-94da-4b03-b2d1-5bdc7e9c51b0
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387154178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.3387154178
Directory	/workspace/30.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_walk.2470206416
Short name	T505
Test name
Test status
Simulation time	190100496 ps
CPU time	5.54 seconds
Started	Jun 23 06:27:06 PM PDT 24
Finished	Jun 23 06:27:12 PM PDT 24
Peak memory	211280 kb
Host	smart-0579654f-e196-4c1c-a9ab-6989b397aee9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470206416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.2470206416
Directory	/workspace/30.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/30.sram_ctrl_multiple_keys.554144045
Short name	T930
Test name
Test status
Simulation time	11594138689 ps
CPU time	1032.25 seconds
Started	Jun 23 06:27:02 PM PDT 24
Finished	Jun 23 06:44:15 PM PDT 24
Peak memory	373300 kb
Host	smart-7ac932bf-d6b2-43ea-ae12-f84b2b22199f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554144045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multip le_keys.554144045
Directory	/workspace/30.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access.1562023276
Short name	T814
Test name
Test status
Simulation time	2844169147 ps
CPU time	13.89 seconds
Started	Jun 23 06:27:00 PM PDT 24
Finished	Jun 23 06:27:15 PM PDT 24
Peak memory	203144 kb
Host	smart-1d17271d-bc00-4eb5-89bf-4015f62fcc0f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562023276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.1562023276
Directory	/workspace/30.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3711145961
Short name	T353
Test name
Test status
Simulation time	6255931431 ps
CPU time	217.57 seconds
Started	Jun 23 06:27:01 PM PDT 24
Finished	Jun 23 06:30:39 PM PDT 24
Peak memory	203172 kb
Host	smart-6957d512-736c-4d29-b1eb-5874d4365e2e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711145961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3711145961
Directory	/workspace/30.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/30.sram_ctrl_ram_cfg.3744764227
Short name	T802
Test name
Test status
Simulation time	144528821 ps
CPU time	0.82 seconds
Started	Jun 23 06:27:01 PM PDT 24
Finished	Jun 23 06:27:02 PM PDT 24
Peak memory	203012 kb
Host	smart-921a85c3-b209-494a-99b5-0fe854920cea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744764227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3744764227
Directory	/workspace/30.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/30.sram_ctrl_regwen.4203607238
Short name	T487
Test name
Test status
Simulation time	2812797977 ps
CPU time	917.26 seconds
Started	Jun 23 06:27:00 PM PDT 24
Finished	Jun 23 06:42:18 PM PDT 24
Peak memory	375864 kb
Host	smart-fed4563f-c98d-4238-a45d-636f7018f15d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203607238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.4203607238
Directory	/workspace/30.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/30.sram_ctrl_smoke.3247550602
Short name	T866
Test name
Test status
Simulation time	152303629 ps
CPU time	6.63 seconds
Started	Jun 23 06:26:57 PM PDT 24
Finished	Jun 23 06:27:04 PM PDT 24
Peak memory	229592 kb
Host	smart-628df33b-b4ee-4d26-a4de-4d9fe45bc73a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247550602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3247550602
Directory	/workspace/30.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.879304077
Short name	T416
Test name
Test status
Simulation time	5178081022 ps
CPU time	106.83 seconds
Started	Jun 23 06:27:05 PM PDT 24
Finished	Jun 23 06:28:52 PM PDT 24
Peak memory	347376 kb
Host	smart-9c5761b3-e790-4db8-a54d-68c25a05d2d5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=879304077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.879304077
Directory	/workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.930374483
Short name	T421
Test name
Test status
Simulation time	10895705431 ps
CPU time	270.37 seconds
Started	Jun 23 06:26:59 PM PDT 24
Finished	Jun 23 06:31:30 PM PDT 24
Peak memory	203120 kb
Host	smart-31d77795-78bb-4c4a-be7d-399f8d756bfa
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930374483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .sram_ctrl_stress_pipeline.930374483
Directory	/workspace/30.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.533765929
Short name	T797
Test name
Test status
Simulation time	57665323 ps
CPU time	1.06 seconds
Started	Jun 23 06:27:00 PM PDT 24
Finished	Jun 23 06:27:01 PM PDT 24
Peak memory	202916 kb
Host	smart-9531baae-6b41-4703-af76-2b922ee734b3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533765929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_throughput_w_partial_write.533765929
Directory	/workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.1322065640
Short name	T189
Test name
Test status
Simulation time	7434584731 ps
CPU time	648.87 seconds
Started	Jun 23 06:27:06 PM PDT 24
Finished	Jun 23 06:37:55 PM PDT 24
Peak memory	368152 kb
Host	smart-ec25250c-2d76-4e26-b3fd-2b6907fc7386
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322065640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.1322065640
Directory	/workspace/31.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/31.sram_ctrl_alert_test.350845137
Short name	T864
Test name
Test status
Simulation time	41959287 ps
CPU time	0.66 seconds
Started	Jun 23 06:27:08 PM PDT 24
Finished	Jun 23 06:27:10 PM PDT 24
Peak memory	202936 kb
Host	smart-fee6abae-7c79-437e-9f8c-57df5168b260
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350845137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.350845137
Directory	/workspace/31.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.sram_ctrl_bijection.318476109
Short name	T221
Test name
Test status
Simulation time	7943830270 ps
CPU time	51.02 seconds
Started	Jun 23 06:27:04 PM PDT 24
Finished	Jun 23 06:27:55 PM PDT 24
Peak memory	203104 kb
Host	smart-5c7ddb49-f97d-40dc-9ebb-4594c0d2ca85
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318476109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection. 318476109
Directory	/workspace/31.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/31.sram_ctrl_executable.1437864934
Short name	T718
Test name
Test status
Simulation time	90049743866 ps
CPU time	942.43 seconds
Started	Jun 23 06:27:05 PM PDT 24
Finished	Jun 23 06:42:48 PM PDT 24
Peak memory	371860 kb
Host	smart-5ae23231-aafa-46cb-b0b3-154e13d5c88b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437864934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.1437864934
Directory	/workspace/31.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/31.sram_ctrl_lc_escalation.3436890118
Short name	T610
Test name
Test status
Simulation time	1459644817 ps
CPU time	4.21 seconds
Started	Jun 23 06:27:05 PM PDT 24
Finished	Jun 23 06:27:09 PM PDT 24
Peak memory	203092 kb
Host	smart-fdb0f8c1-59b8-477a-bdc2-025bcf5ffce8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436890118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.3436890118
Directory	/workspace/31.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/31.sram_ctrl_max_throughput.433684341
Short name	T684
Test name
Test status
Simulation time	209257573 ps
CPU time	51.32 seconds
Started	Jun 23 06:27:06 PM PDT 24
Finished	Jun 23 06:27:58 PM PDT 24
Peak memory	315756 kb
Host	smart-bcee8cb7-e8ec-4417-a1a9-1ae8fd092756
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433684341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.sram_ctrl_max_throughput.433684341
Directory	/workspace/31.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1127424869
Short name	T540
Test name
Test status
Simulation time	65512153 ps
CPU time	4.37 seconds
Started	Jun 23 06:27:12 PM PDT 24
Finished	Jun 23 06:27:17 PM PDT 24
Peak memory	211232 kb
Host	smart-f24598af-efa8-4a04-aa84-c8b257ee725c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127424869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.1127424869
Directory	/workspace/31.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_walk.43899291
Short name	T52
Test name
Test status
Simulation time	719083472 ps
CPU time	9.82 seconds
Started	Jun 23 06:27:10 PM PDT 24
Finished	Jun 23 06:27:21 PM PDT 24
Peak memory	211312 kb
Host	smart-f8161cda-ce6d-443b-8d5f-85436d56e273
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43899291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ mem_walk.43899291
Directory	/workspace/31.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/31.sram_ctrl_multiple_keys.2574524447
Short name	T910
Test name
Test status
Simulation time	14933800704 ps
CPU time	266.82 seconds
Started	Jun 23 06:27:06 PM PDT 24
Finished	Jun 23 06:31:33 PM PDT 24
Peak memory	369760 kb
Host	smart-c3da5086-7719-4aa5-89d2-735ec1089e91
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574524447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.2574524447
Directory	/workspace/31.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access.1655854942
Short name	T335
Test name
Test status
Simulation time	252133015 ps
CPU time	13.07 seconds
Started	Jun 23 06:27:06 PM PDT 24
Finished	Jun 23 06:27:20 PM PDT 24
Peak memory	203028 kb
Host	smart-16b9d841-482d-4b6a-844d-1325958aea6e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655854942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.1655854942
Directory	/workspace/31.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.4002594113
Short name	T762
Test name
Test status
Simulation time	15434845668 ps
CPU time	348.87 seconds
Started	Jun 23 06:27:05 PM PDT 24
Finished	Jun 23 06:32:54 PM PDT 24
Peak memory	203092 kb
Host	smart-67c55f81-b069-4f16-888a-3646a80eb7e9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002594113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.4002594113
Directory	/workspace/31.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/31.sram_ctrl_ram_cfg.1839692290
Short name	T586
Test name
Test status
Simulation time	30678489 ps
CPU time	0.78 seconds
Started	Jun 23 06:27:09 PM PDT 24
Finished	Jun 23 06:27:10 PM PDT 24
Peak memory	203120 kb
Host	smart-43bcce2e-bbc3-46ee-be48-3e98362b30bc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839692290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1839692290
Directory	/workspace/31.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/31.sram_ctrl_regwen.729290978
Short name	T21
Test name
Test status
Simulation time	635696529 ps
CPU time	129.64 seconds
Started	Jun 23 06:27:10 PM PDT 24
Finished	Jun 23 06:29:20 PM PDT 24
Peak memory	345544 kb
Host	smart-56da101e-29ea-4ec8-9b25-ade830503d8f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729290978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.729290978
Directory	/workspace/31.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/31.sram_ctrl_smoke.2395469243
Short name	T924
Test name
Test status
Simulation time	610641168 ps
CPU time	2.86 seconds
Started	Jun 23 06:27:05 PM PDT 24
Finished	Jun 23 06:27:08 PM PDT 24
Peak memory	203032 kb
Host	smart-d7c3f8f4-4692-4ecd-b299-e8d452260f70
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395469243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2395469243
Directory	/workspace/31.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all.4121081181
Short name	T813
Test name
Test status
Simulation time	15724448687 ps
CPU time	4428.77 seconds
Started	Jun 23 06:27:09 PM PDT 24
Finished	Jun 23 07:40:59 PM PDT 24
Peak memory	384120 kb
Host	smart-499a5680-8d8b-4a11-8839-c15606b7bb72
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121081181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.4121081181
Directory	/workspace/31.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3962519914
Short name	T732
Test name
Test status
Simulation time	2140646998 ps
CPU time	107.72 seconds
Started	Jun 23 06:27:10 PM PDT 24
Finished	Jun 23 06:28:58 PM PDT 24
Peak memory	331252 kb
Host	smart-652a00b9-58c9-4e16-9563-9463d006caa3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3962519914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3962519914
Directory	/workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1175695568
Short name	T547
Test name
Test status
Simulation time	18007349313 ps
CPU time	263.53 seconds
Started	Jun 23 06:27:07 PM PDT 24
Finished	Jun 23 06:31:31 PM PDT 24
Peak memory	203112 kb
Host	smart-62d5ddcf-af4c-420b-b588-b3609d0f71c7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175695568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.1175695568
Directory	/workspace/31.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2646940105
Short name	T142
Test name
Test status
Simulation time	1372588653 ps
CPU time	144.88 seconds
Started	Jun 23 06:27:05 PM PDT 24
Finished	Jun 23 06:29:31 PM PDT 24
Peak memory	369684 kb
Host	smart-e6aa456a-ecaf-4e7a-a93a-b56696e386cc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646940105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2646940105
Directory	/workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2727259289
Short name	T88
Test name
Test status
Simulation time	12539828341 ps
CPU time	1101.51 seconds
Started	Jun 23 06:27:08 PM PDT 24
Finished	Jun 23 06:45:30 PM PDT 24
Peak memory	369816 kb
Host	smart-e5d84475-8a81-4471-8333-1eb5a01303b3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727259289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.2727259289
Directory	/workspace/32.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/32.sram_ctrl_alert_test.1464251721
Short name	T15
Test name
Test status
Simulation time	19192444 ps
CPU time	0.64 seconds
Started	Jun 23 06:27:14 PM PDT 24
Finished	Jun 23 06:27:15 PM PDT 24
Peak memory	203168 kb
Host	smart-c568e448-981d-43c7-b33a-41bc85c18c8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464251721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1464251721
Directory	/workspace/32.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.sram_ctrl_bijection.3711699956
Short name	T219
Test name
Test status
Simulation time	4316744259 ps
CPU time	32.42 seconds
Started	Jun 23 06:27:13 PM PDT 24
Finished	Jun 23 06:27:45 PM PDT 24
Peak memory	203088 kb
Host	smart-a918e3d6-452e-480f-9b3e-c8674532f1f7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711699956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .3711699956
Directory	/workspace/32.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/32.sram_ctrl_executable.3688648270
Short name	T228
Test name
Test status
Simulation time	3102779607 ps
CPU time	125.32 seconds
Started	Jun 23 06:27:17 PM PDT 24
Finished	Jun 23 06:29:23 PM PDT 24
Peak memory	316464 kb
Host	smart-ad3357a5-0a93-4371-8a42-5257d175e835
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688648270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.3688648270
Directory	/workspace/32.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/32.sram_ctrl_lc_escalation.1989692220
Short name	T569
Test name
Test status
Simulation time	913409787 ps
CPU time	9.56 seconds
Started	Jun 23 06:27:10 PM PDT 24
Finished	Jun 23 06:27:20 PM PDT 24
Peak memory	203120 kb
Host	smart-b93b7af8-cdfb-4aab-8c90-7cc799857718
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989692220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.1989692220
Directory	/workspace/32.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/32.sram_ctrl_max_throughput.1728140444
Short name	T390
Test name
Test status
Simulation time	40352137 ps
CPU time	1.54 seconds
Started	Jun 23 06:27:11 PM PDT 24
Finished	Jun 23 06:27:13 PM PDT 24
Peak memory	211240 kb
Host	smart-d4e4532f-e757-4daf-b480-4b392b51c4f1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728140444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.1728140444
Directory	/workspace/32.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.4241121378
Short name	T51
Test name
Test status
Simulation time	394833181 ps
CPU time	3.41 seconds
Started	Jun 23 06:27:14 PM PDT 24
Finished	Jun 23 06:27:18 PM PDT 24
Peak memory	211308 kb
Host	smart-f3183247-cca1-4a69-a95a-f4316a0c7f69
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241121378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.4241121378
Directory	/workspace/32.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_walk.2740639941
Short name	T741
Test name
Test status
Simulation time	239811838 ps
CPU time	5.5 seconds
Started	Jun 23 06:27:14 PM PDT 24
Finished	Jun 23 06:27:20 PM PDT 24
Peak memory	211248 kb
Host	smart-466babb7-70f2-4403-85de-61fa627cf0f3
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740639941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.2740639941
Directory	/workspace/32.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/32.sram_ctrl_multiple_keys.3420897207
Short name	T341
Test name
Test status
Simulation time	2339926663 ps
CPU time	513.32 seconds
Started	Jun 23 06:27:08 PM PDT 24
Finished	Jun 23 06:35:42 PM PDT 24
Peak memory	372528 kb
Host	smart-cba62dd9-6a3b-4c94-9c2f-7afc4e338f5c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420897207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.3420897207
Directory	/workspace/32.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access.2075953160
Short name	T798
Test name
Test status
Simulation time	1660435754 ps
CPU time	15.92 seconds
Started	Jun 23 06:27:10 PM PDT 24
Finished	Jun 23 06:27:26 PM PDT 24
Peak memory	203156 kb
Host	smart-ee0452aa-f9f7-4832-bb81-6578acc2e31b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075953160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.2075953160
Directory	/workspace/32.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2231326066
Short name	T400
Test name
Test status
Simulation time	11990362477 ps
CPU time	385.02 seconds
Started	Jun 23 06:27:10 PM PDT 24
Finished	Jun 23 06:33:35 PM PDT 24
Peak memory	203168 kb
Host	smart-0dcf5c8d-a673-4426-b9ca-0fe07643a7b0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231326066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.2231326066
Directory	/workspace/32.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/32.sram_ctrl_ram_cfg.1526701646
Short name	T300
Test name
Test status
Simulation time	39088510 ps
CPU time	0.78 seconds
Started	Jun 23 06:27:15 PM PDT 24
Finished	Jun 23 06:27:16 PM PDT 24
Peak memory	203120 kb
Host	smart-6362d44e-5370-4d4a-a93b-7f29a57b867b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526701646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1526701646
Directory	/workspace/32.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/32.sram_ctrl_regwen.396725571
Short name	T179
Test name
Test status
Simulation time	36509615166 ps
CPU time	818.07 seconds
Started	Jun 23 06:27:17 PM PDT 24
Finished	Jun 23 06:40:55 PM PDT 24
Peak memory	374948 kb
Host	smart-19df916f-dedb-4b1d-8abc-e6125d1b74d1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396725571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.396725571
Directory	/workspace/32.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/32.sram_ctrl_smoke.1391129864
Short name	T710
Test name
Test status
Simulation time	436382799 ps
CPU time	45.31 seconds
Started	Jun 23 06:27:09 PM PDT 24
Finished	Jun 23 06:27:54 PM PDT 24
Peak memory	309108 kb
Host	smart-d967c6e1-e343-4f4b-96b7-057321e9c2cb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391129864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1391129864
Directory	/workspace/32.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all.1405900582
Short name	T751
Test name
Test status
Simulation time	16506573189 ps
CPU time	1138.96 seconds
Started	Jun 23 06:27:14 PM PDT 24
Finished	Jun 23 06:46:13 PM PDT 24
Peak memory	368084 kb
Host	smart-8db9be9f-e55b-4752-b832-d3e65e9ba8e1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405900582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.1405900582
Directory	/workspace/32.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1050258483
Short name	T759
Test name
Test status
Simulation time	2106031523 ps
CPU time	500.24 seconds
Started	Jun 23 06:27:15 PM PDT 24
Finished	Jun 23 06:35:36 PM PDT 24
Peak memory	364428 kb
Host	smart-6fd2f71c-e966-41f4-b9c8-6c0c3c1cba5d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1050258483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1050258483
Directory	/workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.4011014674
Short name	T291
Test name
Test status
Simulation time	2476020438 ps
CPU time	234.49 seconds
Started	Jun 23 06:27:11 PM PDT 24
Finished	Jun 23 06:31:05 PM PDT 24
Peak memory	203176 kb
Host	smart-f2d85764-9ce2-4805-9a67-8754ca1a6685
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011014674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.4011014674
Directory	/workspace/32.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1604864310
Short name	T385
Test name
Test status
Simulation time	579633971 ps
CPU time	123.95 seconds
Started	Jun 23 06:27:10 PM PDT 24
Finished	Jun 23 06:29:14 PM PDT 24
Peak memory	361520 kb
Host	smart-08274c2a-0b37-41bb-881a-94bfc2823c00
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604864310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1604864310
Directory	/workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3411698798
Short name	T509
Test name
Test status
Simulation time	1071916865 ps
CPU time	126.67 seconds
Started	Jun 23 06:27:21 PM PDT 24
Finished	Jun 23 06:29:28 PM PDT 24
Peak memory	362536 kb
Host	smart-3e8a9330-3780-4545-be7e-516c2ea516af
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411698798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.3411698798
Directory	/workspace/33.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/33.sram_ctrl_alert_test.2558804029
Short name	T841
Test name
Test status
Simulation time	15640181 ps
CPU time	0.7 seconds
Started	Jun 23 06:27:22 PM PDT 24
Finished	Jun 23 06:27:23 PM PDT 24
Peak memory	202940 kb
Host	smart-51281fe7-6478-47ee-9b4d-9a7ac55e2294
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558804029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.2558804029
Directory	/workspace/33.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.sram_ctrl_bijection.622188734
Short name	T806
Test name
Test status
Simulation time	2098304656 ps
CPU time	47.38 seconds
Started	Jun 23 06:27:15 PM PDT 24
Finished	Jun 23 06:28:03 PM PDT 24
Peak memory	203060 kb
Host	smart-1f9a8475-d60e-4127-9812-ddb1c9fb17bd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622188734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection. 622188734
Directory	/workspace/33.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/33.sram_ctrl_executable.681914206
Short name	T854
Test name
Test status
Simulation time	2572351139 ps
CPU time	941.83 seconds
Started	Jun 23 06:27:19 PM PDT 24
Finished	Jun 23 06:43:02 PM PDT 24
Peak memory	374628 kb
Host	smart-a040bd60-979c-465e-80b9-15ee0e29e5a9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681914206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executabl e.681914206
Directory	/workspace/33.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/33.sram_ctrl_lc_escalation.1127179696
Short name	T863
Test name
Test status
Simulation time	2289410563 ps
CPU time	6.95 seconds
Started	Jun 23 06:27:19 PM PDT 24
Finished	Jun 23 06:27:26 PM PDT 24
Peak memory	203132 kb
Host	smart-9a3daa9d-a17d-48d1-bd5d-3b3670891503
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127179696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.1127179696
Directory	/workspace/33.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/33.sram_ctrl_max_throughput.3775876699
Short name	T566
Test name
Test status
Simulation time	515360006 ps
CPU time	156.06 seconds
Started	Jun 23 06:27:21 PM PDT 24
Finished	Jun 23 06:29:58 PM PDT 24
Peak memory	370764 kb
Host	smart-b6592e8c-43bf-4a84-b01e-8766cea69fd3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775876699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.3775876699
Directory	/workspace/33.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3586267023
Short name	T638
Test name
Test status
Simulation time	206139892 ps
CPU time	3.36 seconds
Started	Jun 23 06:27:21 PM PDT 24
Finished	Jun 23 06:27:25 PM PDT 24
Peak memory	211272 kb
Host	smart-abde8b2b-56e5-4172-99e3-c353c27a5093
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586267023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.3586267023
Directory	/workspace/33.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_walk.3168261408
Short name	T491
Test name
Test status
Simulation time	2330995418 ps
CPU time	11.91 seconds
Started	Jun 23 06:27:19 PM PDT 24
Finished	Jun 23 06:27:32 PM PDT 24
Peak memory	211372 kb
Host	smart-a385f361-79b4-4caa-8554-31fcea10bf48
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168261408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.3168261408
Directory	/workspace/33.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/33.sram_ctrl_multiple_keys.753478868
Short name	T589
Test name
Test status
Simulation time	52287828668 ps
CPU time	551.65 seconds
Started	Jun 23 06:27:16 PM PDT 24
Finished	Jun 23 06:36:28 PM PDT 24
Peak memory	371972 kb
Host	smart-6c8e968f-1392-4e65-848b-9602f6ea18e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753478868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip le_keys.753478868
Directory	/workspace/33.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access.3462660549
Short name	T865
Test name
Test status
Simulation time	74073840 ps
CPU time	6.51 seconds
Started	Jun 23 06:27:22 PM PDT 24
Finished	Jun 23 06:27:29 PM PDT 24
Peak memory	229672 kb
Host	smart-ad7c76ba-c679-4682-9302-5501251a0962
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462660549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.3462660549
Directory	/workspace/33.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1010572723
Short name	T747
Test name
Test status
Simulation time	16347180221 ps
CPU time	302.24 seconds
Started	Jun 23 06:27:21 PM PDT 24
Finished	Jun 23 06:32:23 PM PDT 24
Peak memory	203080 kb
Host	smart-a35544f3-dd5d-4c1b-a27f-c255e553fc2e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010572723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.1010572723
Directory	/workspace/33.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/33.sram_ctrl_ram_cfg.2430580957
Short name	T816
Test name
Test status
Simulation time	27487670 ps
CPU time	0.79 seconds
Started	Jun 23 06:27:20 PM PDT 24
Finished	Jun 23 06:27:21 PM PDT 24
Peak memory	203104 kb
Host	smart-36c10c18-06b7-4c1c-a152-878938871c04
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430580957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2430580957
Directory	/workspace/33.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/33.sram_ctrl_regwen.2823055420
Short name	T479
Test name
Test status
Simulation time	8639618298 ps
CPU time	447.85 seconds
Started	Jun 23 06:27:19 PM PDT 24
Finished	Jun 23 06:34:47 PM PDT 24
Peak memory	362056 kb
Host	smart-af7c3c01-e32f-4ec0-a465-352c23569631
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823055420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2823055420
Directory	/workspace/33.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/33.sram_ctrl_smoke.2159718897
Short name	T234
Test name
Test status
Simulation time	189507697 ps
CPU time	8.81 seconds
Started	Jun 23 06:27:14 PM PDT 24
Finished	Jun 23 06:27:23 PM PDT 24
Peak memory	236260 kb
Host	smart-245599bc-a751-4fc3-ae78-0cd07f0f99fb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159718897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2159718897
Directory	/workspace/33.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all.791236186
Short name	T606
Test name
Test status
Simulation time	36527214743 ps
CPU time	3241.92 seconds
Started	Jun 23 06:27:21 PM PDT 24
Finished	Jun 23 07:21:24 PM PDT 24
Peak memory	375208 kb
Host	smart-ea35900e-7938-4ee7-9892-92a24ea4e2f2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791236186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_stress_all.791236186
Directory	/workspace/33.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3361652657
Short name	T53
Test name
Test status
Simulation time	1684435131 ps
CPU time	520.62 seconds
Started	Jun 23 06:27:21 PM PDT 24
Finished	Jun 23 06:36:02 PM PDT 24
Peak memory	379092 kb
Host	smart-4fcca51b-a7cc-411f-89e6-9c4db2bfad62
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3361652657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3361652657
Directory	/workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2111071874
Short name	T103
Test name
Test status
Simulation time	12403982444 ps
CPU time	292 seconds
Started	Jun 23 06:27:15 PM PDT 24
Finished	Jun 23 06:32:07 PM PDT 24
Peak memory	203056 kb
Host	smart-437d261f-d7b1-4142-a310-95a051513e3e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111071874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.2111071874
Directory	/workspace/33.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.227974798
Short name	T588
Test name
Test status
Simulation time	134676049 ps
CPU time	102.33 seconds
Started	Jun 23 06:27:19 PM PDT 24
Finished	Jun 23 06:29:01 PM PDT 24
Peak memory	341916 kb
Host	smart-ffdeb9ac-cb58-46d6-b048-711e4691471e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227974798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.227974798
Directory	/workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.781267054
Short name	T40
Test name
Test status
Simulation time	6852127933 ps
CPU time	706.64 seconds
Started	Jun 23 06:27:25 PM PDT 24
Finished	Jun 23 06:39:12 PM PDT 24
Peak memory	371556 kb
Host	smart-d4d0545d-348d-48a8-8d83-7cf0496e8c32
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781267054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 34.sram_ctrl_access_during_key_req.781267054
Directory	/workspace/34.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/34.sram_ctrl_alert_test.750793511
Short name	T753
Test name
Test status
Simulation time	24708861 ps
CPU time	0.66 seconds
Started	Jun 23 06:27:23 PM PDT 24
Finished	Jun 23 06:27:24 PM PDT 24
Peak memory	202940 kb
Host	smart-dba0597c-60c4-4507-a574-9be7271434c7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750793511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.750793511
Directory	/workspace/34.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.sram_ctrl_bijection.2919364283
Short name	T330
Test name
Test status
Simulation time	3530181661 ps
CPU time	74.32 seconds
Started	Jun 23 06:27:20 PM PDT 24
Finished	Jun 23 06:28:35 PM PDT 24
Peak memory	203148 kb
Host	smart-4ab7f5ae-6951-49d9-ae7a-57a3311ead8a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919364283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .2919364283
Directory	/workspace/34.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/34.sram_ctrl_executable.1567453097
Short name	T625
Test name
Test status
Simulation time	12897152986 ps
CPU time	939.58 seconds
Started	Jun 23 06:27:23 PM PDT 24
Finished	Jun 23 06:43:03 PM PDT 24
Peak memory	374744 kb
Host	smart-4e272fcc-f6b1-424a-9b9a-47d30e8c4d5a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567453097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.1567453097
Directory	/workspace/34.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/34.sram_ctrl_lc_escalation.3550382934
Short name	T325
Test name
Test status
Simulation time	554139485 ps
CPU time	7.16 seconds
Started	Jun 23 06:27:23 PM PDT 24
Finished	Jun 23 06:27:31 PM PDT 24
Peak memory	203044 kb
Host	smart-4af24072-6ad8-4663-bc0b-fd4d1cb9421c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550382934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.3550382934
Directory	/workspace/34.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/34.sram_ctrl_max_throughput.2336727378
Short name	T299
Test name
Test status
Simulation time	86613541 ps
CPU time	2.51 seconds
Started	Jun 23 06:27:24 PM PDT 24
Finished	Jun 23 06:27:28 PM PDT 24
Peak memory	219104 kb
Host	smart-7121e881-63d3-4e48-9d2b-de77d7f35cd7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336727378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.2336727378
Directory	/workspace/34.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2596321844
Short name	T59
Test name
Test status
Simulation time	309192288 ps
CPU time	3.01 seconds
Started	Jun 23 06:27:24 PM PDT 24
Finished	Jun 23 06:27:27 PM PDT 24
Peak memory	211308 kb
Host	smart-5cd548fe-bdae-4c8b-b27c-8157e7775897
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596321844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.2596321844
Directory	/workspace/34.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_walk.487032265
Short name	T322
Test name
Test status
Simulation time	1276980944 ps
CPU time	11.4 seconds
Started	Jun 23 06:27:27 PM PDT 24
Finished	Jun 23 06:27:38 PM PDT 24
Peak memory	211308 kb
Host	smart-743c9e33-c5d0-4cea-bbe5-a6d9d47b5975
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487032265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl _mem_walk.487032265
Directory	/workspace/34.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/34.sram_ctrl_multiple_keys.3414838099
Short name	T449
Test name
Test status
Simulation time	21038639021 ps
CPU time	1757.42 seconds
Started	Jun 23 06:27:20 PM PDT 24
Finished	Jun 23 06:56:38 PM PDT 24
Peak memory	376004 kb
Host	smart-430de1d4-6102-4c47-9a6e-b53d2616c365
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414838099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.3414838099
Directory	/workspace/34.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access.1250383261
Short name	T324
Test name
Test status
Simulation time	1234309625 ps
CPU time	23.38 seconds
Started	Jun 23 06:27:20 PM PDT 24
Finished	Jun 23 06:27:44 PM PDT 24
Peak memory	271060 kb
Host	smart-f2cbdea8-217e-4ec3-89b0-0089eed7d5fe
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250383261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.1250383261
Directory	/workspace/34.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2615091951
Short name	T703
Test name
Test status
Simulation time	73933890414 ps
CPU time	472.53 seconds
Started	Jun 23 06:27:23 PM PDT 24
Finished	Jun 23 06:35:16 PM PDT 24
Peak memory	203160 kb
Host	smart-1d81ad22-774d-42c4-937b-8fc4c22d019b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615091951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.2615091951
Directory	/workspace/34.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/34.sram_ctrl_ram_cfg.3078015007
Short name	T352
Test name
Test status
Simulation time	80663707 ps
CPU time	0.76 seconds
Started	Jun 23 06:27:25 PM PDT 24
Finished	Jun 23 06:27:26 PM PDT 24
Peak memory	203124 kb
Host	smart-8d5819c7-a13e-4790-aba7-8adb35676726
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078015007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3078015007
Directory	/workspace/34.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/34.sram_ctrl_regwen.1232590605
Short name	T577
Test name
Test status
Simulation time	1542955123 ps
CPU time	557.65 seconds
Started	Jun 23 06:27:25 PM PDT 24
Finished	Jun 23 06:36:43 PM PDT 24
Peak memory	375264 kb
Host	smart-93f997f9-c017-4859-b47a-d2b7912d3b9d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232590605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1232590605
Directory	/workspace/34.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/34.sram_ctrl_smoke.2388107454
Short name	T473
Test name
Test status
Simulation time	883008617 ps
CPU time	2.29 seconds
Started	Jun 23 06:27:21 PM PDT 24
Finished	Jun 23 06:27:23 PM PDT 24
Peak memory	203088 kb
Host	smart-ab302f13-9273-499b-8ec9-e246974a7b6c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388107454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2388107454
Directory	/workspace/34.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all.2227660085
Short name	T121
Test name
Test status
Simulation time	16490946394 ps
CPU time	1808.49 seconds
Started	Jun 23 06:27:26 PM PDT 24
Finished	Jun 23 06:57:35 PM PDT 24
Peak memory	376148 kb
Host	smart-62e887a3-212d-4eb5-9078-dd18efddb0b7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227660085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.2227660085
Directory	/workspace/34.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1478499331
Short name	T536
Test name
Test status
Simulation time	621652975 ps
CPU time	438.86 seconds
Started	Jun 23 06:27:26 PM PDT 24
Finished	Jun 23 06:34:46 PM PDT 24
Peak memory	383144 kb
Host	smart-8043a848-4e32-4920-8f2f-78a5690f8cf1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1478499331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1478499331
Directory	/workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3098388157
Short name	T474
Test name
Test status
Simulation time	12825854746 ps
CPU time	353.26 seconds
Started	Jun 23 06:27:20 PM PDT 24
Finished	Jun 23 06:33:13 PM PDT 24
Peak memory	203112 kb
Host	smart-8aba1f7a-6427-45d5-b80d-42635f6ccf1b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098388157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.3098388157
Directory	/workspace/34.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1909252190
Short name	T145
Test name
Test status
Simulation time	243052674 ps
CPU time	76.11 seconds
Started	Jun 23 06:27:24 PM PDT 24
Finished	Jun 23 06:28:40 PM PDT 24
Peak memory	325752 kb
Host	smart-09d2e009-f464-438a-9142-d4ab0eb2cab4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909252190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1909252190
Directory	/workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.114228794
Short name	T768
Test name
Test status
Simulation time	3712133578 ps
CPU time	540.15 seconds
Started	Jun 23 06:27:28 PM PDT 24
Finished	Jun 23 06:36:29 PM PDT 24
Peak memory	355712 kb
Host	smart-9a7f0900-bd1b-4cdd-a347-a0e6a77c05dc
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114228794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 35.sram_ctrl_access_during_key_req.114228794
Directory	/workspace/35.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/35.sram_ctrl_alert_test.235629870
Short name	T744
Test name
Test status
Simulation time	40262229 ps
CPU time	0.66 seconds
Started	Jun 23 06:27:33 PM PDT 24
Finished	Jun 23 06:27:34 PM PDT 24
Peak memory	202908 kb
Host	smart-584b671e-b8ac-48ef-a9d4-de314741b979
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235629870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.235629870
Directory	/workspace/35.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.sram_ctrl_bijection.4128778430
Short name	T784
Test name
Test status
Simulation time	4701136356 ps
CPU time	87.06 seconds
Started	Jun 23 06:27:30 PM PDT 24
Finished	Jun 23 06:28:58 PM PDT 24
Peak memory	203136 kb
Host	smart-130db2a1-a198-4480-bcfb-ac3fdf6b489d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128778430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .4128778430
Directory	/workspace/35.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/35.sram_ctrl_executable.749769898
Short name	T296
Test name
Test status
Simulation time	23424699824 ps
CPU time	1502 seconds
Started	Jun 23 06:27:30 PM PDT 24
Finished	Jun 23 06:52:33 PM PDT 24
Peak memory	375540 kb
Host	smart-ed043e5e-3fdd-486d-816f-66962041ac20
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749769898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executabl e.749769898
Directory	/workspace/35.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/35.sram_ctrl_lc_escalation.3207369169
Short name	T769
Test name
Test status
Simulation time	630174019 ps
CPU time	7.13 seconds
Started	Jun 23 06:27:29 PM PDT 24
Finished	Jun 23 06:27:37 PM PDT 24
Peak memory	203048 kb
Host	smart-7b898ead-4977-4e2d-91bf-ee0fd4663a16
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207369169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.3207369169
Directory	/workspace/35.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/35.sram_ctrl_max_throughput.2341804780
Short name	T311
Test name
Test status
Simulation time	1498344875 ps
CPU time	113.23 seconds
Started	Jun 23 06:27:30 PM PDT 24
Finished	Jun 23 06:29:24 PM PDT 24
Peak memory	355480 kb
Host	smart-f48486d2-4e81-4639-97f5-e9dc0fed94fa
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341804780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.2341804780
Directory	/workspace/35.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3149637071
Short name	T263
Test name
Test status
Simulation time	212346091 ps
CPU time	3.4 seconds
Started	Jun 23 06:27:32 PM PDT 24
Finished	Jun 23 06:27:36 PM PDT 24
Peak memory	211264 kb
Host	smart-80a1da49-8cff-4c27-a7bc-1478a173da8d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149637071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.3149637071
Directory	/workspace/35.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_walk.726197967
Short name	T360
Test name
Test status
Simulation time	187995497 ps
CPU time	5.16 seconds
Started	Jun 23 06:27:34 PM PDT 24
Finished	Jun 23 06:27:39 PM PDT 24
Peak memory	211300 kb
Host	smart-69fb4510-ac24-4fc3-84d5-c610b03aedc2
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726197967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _mem_walk.726197967
Directory	/workspace/35.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/35.sram_ctrl_multiple_keys.442819580
Short name	T800
Test name
Test status
Simulation time	43185171649 ps
CPU time	1750.7 seconds
Started	Jun 23 06:27:31 PM PDT 24
Finished	Jun 23 06:56:42 PM PDT 24
Peak memory	375168 kb
Host	smart-6f6e1084-58c6-4e66-86b4-0871ff50f927
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442819580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip le_keys.442819580
Directory	/workspace/35.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access.2128041769
Short name	T721
Test name
Test status
Simulation time	1126447868 ps
CPU time	10.72 seconds
Started	Jun 23 06:27:30 PM PDT 24
Finished	Jun 23 06:27:41 PM PDT 24
Peak memory	203092 kb
Host	smart-21fc0dd2-3e01-4098-bc02-e309e1c610dc
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128041769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.2128041769
Directory	/workspace/35.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_ram_cfg.3949122462
Short name	T760
Test name
Test status
Simulation time	99190565 ps
CPU time	0.74 seconds
Started	Jun 23 06:27:33 PM PDT 24
Finished	Jun 23 06:27:34 PM PDT 24
Peak memory	203116 kb
Host	smart-04c5cf13-082a-4612-a680-1dd3c6ee84ad
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949122462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.3949122462
Directory	/workspace/35.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/35.sram_ctrl_regwen.1171941178
Short name	T71
Test name
Test status
Simulation time	22659842332 ps
CPU time	649.26 seconds
Started	Jun 23 06:27:34 PM PDT 24
Finished	Jun 23 06:38:23 PM PDT 24
Peak memory	368712 kb
Host	smart-df44656e-e945-423d-83ac-f18ce9c26098
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171941178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1171941178
Directory	/workspace/35.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/35.sram_ctrl_smoke.1088838662
Short name	T57
Test name
Test status
Simulation time	233740677 ps
CPU time	4.08 seconds
Started	Jun 23 06:27:30 PM PDT 24
Finished	Jun 23 06:27:35 PM PDT 24
Peak memory	203028 kb
Host	smart-abdd3401-37ac-4e75-8b6f-d01558dca939
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088838662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1088838662
Directory	/workspace/35.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all.1599937750
Short name	T438
Test name
Test status
Simulation time	36386996269 ps
CPU time	2313.15 seconds
Started	Jun 23 06:27:34 PM PDT 24
Finished	Jun 23 07:06:08 PM PDT 24
Peak memory	376000 kb
Host	smart-542c9705-2d16-4709-a347-f5941a5be204
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599937750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.1599937750
Directory	/workspace/35.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1167949295
Short name	T481
Test name
Test status
Simulation time	11613262147 ps
CPU time	283.84 seconds
Started	Jun 23 06:27:31 PM PDT 24
Finished	Jun 23 06:32:15 PM PDT 24
Peak memory	203164 kb
Host	smart-f47573a6-ccd1-473f-bc3b-47303d507f09
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167949295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1167949295
Directory	/workspace/35.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4288065269
Short name	T362
Test name
Test status
Simulation time	1222456808 ps
CPU time	66.56 seconds
Started	Jun 23 06:27:30 PM PDT 24
Finished	Jun 23 06:28:37 PM PDT 24
Peak memory	333628 kb
Host	smart-53df4609-a9eb-43bc-bb6d-6e987b65f9bd
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288065269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.4288065269
Directory	/workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/36.sram_ctrl_alert_test.2276725018
Short name	T867
Test name
Test status
Simulation time	13511030 ps
CPU time	0.67 seconds
Started	Jun 23 06:27:43 PM PDT 24
Finished	Jun 23 06:27:45 PM PDT 24
Peak memory	202884 kb
Host	smart-f9b42cf9-3d5e-4f9c-bf49-fabcdc652bde
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276725018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.2276725018
Directory	/workspace/36.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.sram_ctrl_bijection.2883210900
Short name	T855
Test name
Test status
Simulation time	2494868923 ps
CPU time	39.99 seconds
Started	Jun 23 06:27:33 PM PDT 24
Finished	Jun 23 06:28:14 PM PDT 24
Peak memory	203128 kb
Host	smart-3125290e-35e0-421d-8d8a-ce0315f7c4aa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883210900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .2883210900
Directory	/workspace/36.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/36.sram_ctrl_executable.623463104
Short name	T654
Test name
Test status
Simulation time	73294658887 ps
CPU time	2104.77 seconds
Started	Jun 23 06:27:38 PM PDT 24
Finished	Jun 23 07:02:43 PM PDT 24
Peak memory	375520 kb
Host	smart-34851462-5e94-4839-8895-ecc9d5b3b894
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623463104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executabl e.623463104
Directory	/workspace/36.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/36.sram_ctrl_lc_escalation.2669092199
Short name	T901
Test name
Test status
Simulation time	1289116926 ps
CPU time	4.79 seconds
Started	Jun 23 06:27:36 PM PDT 24
Finished	Jun 23 06:27:41 PM PDT 24
Peak memory	203072 kb
Host	smart-dec51b5d-7061-4bdf-bc3c-b484b4da5c7e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669092199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.2669092199
Directory	/workspace/36.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/36.sram_ctrl_max_throughput.4160959623
Short name	T158
Test name
Test status
Simulation time	97159040 ps
CPU time	4.19 seconds
Started	Jun 23 06:27:34 PM PDT 24
Finished	Jun 23 06:27:38 PM PDT 24
Peak memory	224560 kb
Host	smart-f8dd1af6-7ce0-49eb-a400-c978b323ae68
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160959623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.4160959623
Directory	/workspace/36.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3694834417
Short name	T283
Test name
Test status
Simulation time	350880627 ps
CPU time	2.96 seconds
Started	Jun 23 06:27:37 PM PDT 24
Finished	Jun 23 06:27:40 PM PDT 24
Peak memory	211248 kb
Host	smart-9dfb848c-0f9b-4823-9a95-a9143ed85d30
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694834417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.3694834417
Directory	/workspace/36.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_walk.1663439657
Short name	T698
Test name
Test status
Simulation time	4426333603 ps
CPU time	11.57 seconds
Started	Jun 23 06:27:40 PM PDT 24
Finished	Jun 23 06:27:52 PM PDT 24
Peak memory	203132 kb
Host	smart-99c7d82f-3174-4f33-93b9-9dcc5b48e9aa
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663439657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.1663439657
Directory	/workspace/36.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/36.sram_ctrl_multiple_keys.1378885599
Short name	T405
Test name
Test status
Simulation time	20751573033 ps
CPU time	882.21 seconds
Started	Jun 23 06:27:33 PM PDT 24
Finished	Jun 23 06:42:15 PM PDT 24
Peak memory	367104 kb
Host	smart-a7cf73fb-437f-48d7-b7ab-93d7c895cc37
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378885599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.1378885599
Directory	/workspace/36.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access.469137792
Short name	T497
Test name
Test status
Simulation time	588890106 ps
CPU time	10.72 seconds
Started	Jun 23 06:27:33 PM PDT 24
Finished	Jun 23 06:27:44 PM PDT 24
Peak memory	203064 kb
Host	smart-ed672c2f-77a8-41b2-ae5f-e40048cb37b5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469137792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s ram_ctrl_partial_access.469137792
Directory	/workspace/36.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2840355126
Short name	T724
Test name
Test status
Simulation time	6413846168 ps
CPU time	459.02 seconds
Started	Jun 23 06:27:34 PM PDT 24
Finished	Jun 23 06:35:14 PM PDT 24
Peak memory	203164 kb
Host	smart-4b48faa6-3761-4b45-930c-c0fa78eeb5a4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840355126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.2840355126
Directory	/workspace/36.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/36.sram_ctrl_ram_cfg.595720938
Short name	T817
Test name
Test status
Simulation time	42585714 ps
CPU time	0.74 seconds
Started	Jun 23 06:27:37 PM PDT 24
Finished	Jun 23 06:27:38 PM PDT 24
Peak memory	203072 kb
Host	smart-2daf4e3a-8af6-4ead-b195-3d6fa7b678ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595720938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.595720938
Directory	/workspace/36.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/36.sram_ctrl_regwen.1835418096
Short name	T458
Test name
Test status
Simulation time	22284419800 ps
CPU time	701.39 seconds
Started	Jun 23 06:27:40 PM PDT 24
Finished	Jun 23 06:39:21 PM PDT 24
Peak memory	354480 kb
Host	smart-b045ea40-0efa-4ff5-8a1b-3f297293186e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835418096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1835418096
Directory	/workspace/36.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/36.sram_ctrl_smoke.1921607939
Short name	T750
Test name
Test status
Simulation time	2597368251 ps
CPU time	158.2 seconds
Started	Jun 23 06:27:34 PM PDT 24
Finished	Jun 23 06:30:13 PM PDT 24
Peak memory	368648 kb
Host	smart-aa09fbd8-f239-47cc-a99c-6c5e4cd17292
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921607939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1921607939
Directory	/workspace/36.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all.679052118
Short name	T372
Test name
Test status
Simulation time	57490576280 ps
CPU time	4049.97 seconds
Started	Jun 23 06:27:39 PM PDT 24
Finished	Jun 23 07:35:09 PM PDT 24
Peak memory	374824 kb
Host	smart-1f0cd413-5f2e-4a7a-9c39-21220a14d0bf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679052118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_stress_all.679052118
Directory	/workspace/36.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1088111701
Short name	T440
Test name
Test status
Simulation time	6058150690 ps
CPU time	55.29 seconds
Started	Jun 23 06:27:38 PM PDT 24
Finished	Jun 23 06:28:34 PM PDT 24
Peak memory	298820 kb
Host	smart-22c19017-3e99-4c54-bb57-a99778080a2b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1088111701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1088111701
Directory	/workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2608411604
Short name	T876
Test name
Test status
Simulation time	25221882312 ps
CPU time	383.74 seconds
Started	Jun 23 06:27:34 PM PDT 24
Finished	Jun 23 06:33:58 PM PDT 24
Peak memory	203144 kb
Host	smart-171cee17-26c8-4c05-96de-ee72a3b38907
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608411604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.2608411604
Directory	/workspace/36.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.216437229
Short name	T454
Test name
Test status
Simulation time	622414250 ps
CPU time	145.66 seconds
Started	Jun 23 06:27:35 PM PDT 24
Finished	Jun 23 06:30:01 PM PDT 24
Peak memory	371588 kb
Host	smart-8fdfdebf-e663-4e44-9a25-48fadd7d30b3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216437229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.216437229
Directory	/workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3325444313
Short name	T596
Test name
Test status
Simulation time	5736472597 ps
CPU time	370.37 seconds
Started	Jun 23 06:27:44 PM PDT 24
Finished	Jun 23 06:33:54 PM PDT 24
Peak memory	372868 kb
Host	smart-3fb5bae6-5c68-41c2-b372-dad72c6ee8f3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325444313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.3325444313
Directory	/workspace/37.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/37.sram_ctrl_alert_test.3628333355
Short name	T274
Test name
Test status
Simulation time	22687377 ps
CPU time	0.66 seconds
Started	Jun 23 06:27:45 PM PDT 24
Finished	Jun 23 06:27:46 PM PDT 24
Peak memory	202920 kb
Host	smart-bd914af2-334a-431f-a4d3-4e1ff6b2afa8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628333355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3628333355
Directory	/workspace/37.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.sram_ctrl_bijection.993921597
Short name	T420
Test name
Test status
Simulation time	2773644523 ps
CPU time	39.57 seconds
Started	Jun 23 06:27:40 PM PDT 24
Finished	Jun 23 06:28:20 PM PDT 24
Peak memory	203112 kb
Host	smart-f012088b-7aa0-40b1-809c-0102ab5ab102
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993921597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection. 993921597
Directory	/workspace/37.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/37.sram_ctrl_executable.1259080733
Short name	T900
Test name
Test status
Simulation time	79676974500 ps
CPU time	941.89 seconds
Started	Jun 23 06:27:46 PM PDT 24
Finished	Jun 23 06:43:28 PM PDT 24
Peak memory	365756 kb
Host	smart-eb44b47b-2467-415a-a8ea-ebb3fc495fb9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259080733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.1259080733
Directory	/workspace/37.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/37.sram_ctrl_lc_escalation.3271296868
Short name	T109
Test name
Test status
Simulation time	1081625383 ps
CPU time	3.44 seconds
Started	Jun 23 06:27:47 PM PDT 24
Finished	Jun 23 06:27:51 PM PDT 24
Peak memory	211280 kb
Host	smart-0fa026ae-2aea-4198-9f83-324b1336e79b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271296868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.3271296868
Directory	/workspace/37.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/37.sram_ctrl_max_throughput.4209653767
Short name	T677
Test name
Test status
Simulation time	246484654 ps
CPU time	101.52 seconds
Started	Jun 23 06:27:46 PM PDT 24
Finished	Jun 23 06:29:28 PM PDT 24
Peak memory	354104 kb
Host	smart-a57c30a0-deee-4fe1-a947-aadba21f1daf
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209653767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.4209653767
Directory	/workspace/37.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3500828709
Short name	T382
Test name
Test status
Simulation time	182023522 ps
CPU time	2.69 seconds
Started	Jun 23 06:27:45 PM PDT 24
Finished	Jun 23 06:27:48 PM PDT 24
Peak memory	211496 kb
Host	smart-ccfe4a0c-2cad-4d55-9787-3bdc79c74bf6
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500828709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.3500828709
Directory	/workspace/37.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_walk.261122993
Short name	T378
Test name
Test status
Simulation time	443296831 ps
CPU time	10.45 seconds
Started	Jun 23 06:27:46 PM PDT 24
Finished	Jun 23 06:27:57 PM PDT 24
Peak memory	211140 kb
Host	smart-a3e9ba73-b5e2-4c5c-b344-ee3ea8948a7d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261122993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _mem_walk.261122993
Directory	/workspace/37.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/37.sram_ctrl_multiple_keys.4083045402
Short name	T623
Test name
Test status
Simulation time	24295385846 ps
CPU time	1171.97 seconds
Started	Jun 23 06:27:39 PM PDT 24
Finished	Jun 23 06:47:11 PM PDT 24
Peak memory	373908 kb
Host	smart-7bb18de3-faba-4c07-b1fa-d52fcd7a4d7c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083045402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.4083045402
Directory	/workspace/37.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access.2898090002
Short name	T177
Test name
Test status
Simulation time	1535347777 ps
CPU time	12.39 seconds
Started	Jun 23 06:27:47 PM PDT 24
Finished	Jun 23 06:28:00 PM PDT 24
Peak memory	241228 kb
Host	smart-ffa77e34-c621-49e6-a522-81858e034f40
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898090002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.2898090002
Directory	/workspace/37.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1868050359
Short name	T278
Test name
Test status
Simulation time	7155325323 ps
CPU time	556.81 seconds
Started	Jun 23 06:27:46 PM PDT 24
Finished	Jun 23 06:37:03 PM PDT 24
Peak memory	203136 kb
Host	smart-99e16a79-37e1-4b58-be42-a68ae3064996
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868050359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.1868050359
Directory	/workspace/37.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/37.sram_ctrl_ram_cfg.1694884659
Short name	T512
Test name
Test status
Simulation time	86108261 ps
CPU time	0.78 seconds
Started	Jun 23 06:27:45 PM PDT 24
Finished	Jun 23 06:27:47 PM PDT 24
Peak memory	203112 kb
Host	smart-7807d550-0e7f-4809-9e31-8920dcfacd20
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694884659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1694884659
Directory	/workspace/37.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/37.sram_ctrl_regwen.1484260128
Short name	T503
Test name
Test status
Simulation time	4471560682 ps
CPU time	1089.09 seconds
Started	Jun 23 06:27:45 PM PDT 24
Finished	Jun 23 06:45:54 PM PDT 24
Peak memory	372888 kb
Host	smart-475f583b-4fe5-49e6-b36d-59cfec1b9551
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484260128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1484260128
Directory	/workspace/37.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/37.sram_ctrl_smoke.2863234317
Short name	T404
Test name
Test status
Simulation time	3406721897 ps
CPU time	15.22 seconds
Started	Jun 23 06:27:41 PM PDT 24
Finished	Jun 23 06:27:56 PM PDT 24
Peak memory	203136 kb
Host	smart-dd31c5cd-671a-4348-abf3-a6fe17ca3bf6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863234317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2863234317
Directory	/workspace/37.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all.4123771314
Short name	T244
Test name
Test status
Simulation time	12789903517 ps
CPU time	1647.3 seconds
Started	Jun 23 06:27:47 PM PDT 24
Finished	Jun 23 06:55:15 PM PDT 24
Peak memory	375956 kb
Host	smart-4bef5b00-93e6-4324-84ff-aa73e56eb79c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123771314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.4123771314
Directory	/workspace/37.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.221167631
Short name	T47
Test name
Test status
Simulation time	1654449629 ps
CPU time	13.24 seconds
Started	Jun 23 06:27:46 PM PDT 24
Finished	Jun 23 06:28:00 PM PDT 24
Peak memory	211356 kb
Host	smart-26a64140-7ddb-48f8-a2a4-1561d1b26331
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=221167631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.221167631
Directory	/workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.42020180
Short name	T790
Test name
Test status
Simulation time	6366379891 ps
CPU time	157.18 seconds
Started	Jun 23 06:27:41 PM PDT 24
Finished	Jun 23 06:30:18 PM PDT 24
Peak memory	203196 kb
Host	smart-cb0047ba-4191-4c27-9373-9b11df9145f2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_stress_pipeline.42020180
Directory	/workspace/37.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1309051962
Short name	T903
Test name
Test status
Simulation time	316613225 ps
CPU time	73.37 seconds
Started	Jun 23 06:27:46 PM PDT 24
Finished	Jun 23 06:28:59 PM PDT 24
Peak memory	325764 kb
Host	smart-81a11e5d-5e6b-48fc-8d8a-163943b5934b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309051962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1309051962
Directory	/workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/38.sram_ctrl_access_during_key_req.3260066411
Short name	T598
Test name
Test status
Simulation time	23557039496 ps
CPU time	1667.07 seconds
Started	Jun 23 06:27:49 PM PDT 24
Finished	Jun 23 06:55:36 PM PDT 24
Peak memory	374564 kb
Host	smart-fcc8abf0-4c40-48db-aafb-fdb5e91ea760
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260066411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.3260066411
Directory	/workspace/38.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/38.sram_ctrl_alert_test.1436653518
Short name	T288
Test name
Test status
Simulation time	35503012 ps
CPU time	0.68 seconds
Started	Jun 23 06:27:47 PM PDT 24
Finished	Jun 23 06:27:48 PM PDT 24
Peak memory	202944 kb
Host	smart-b6398624-606d-4a21-a9ff-aacb6fea88fa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436653518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.1436653518
Directory	/workspace/38.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.sram_ctrl_bijection.3397477745
Short name	T466
Test name
Test status
Simulation time	3035084873 ps
CPU time	52.54 seconds
Started	Jun 23 06:27:45 PM PDT 24
Finished	Jun 23 06:28:38 PM PDT 24
Peak memory	203388 kb
Host	smart-66ff88be-0fdd-4335-98f8-5dc151dc7571
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397477745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .3397477745
Directory	/workspace/38.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/38.sram_ctrl_executable.1885080868
Short name	T293
Test name
Test status
Simulation time	36150527326 ps
CPU time	908.32 seconds
Started	Jun 23 06:27:47 PM PDT 24
Finished	Jun 23 06:42:56 PM PDT 24
Peak memory	354464 kb
Host	smart-836ec997-560b-44ea-9ff8-d8d298a8ef57
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885080868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.1885080868
Directory	/workspace/38.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/38.sram_ctrl_lc_escalation.373997063
Short name	T478
Test name
Test status
Simulation time	490923178 ps
CPU time	6.01 seconds
Started	Jun 23 06:27:48 PM PDT 24
Finished	Jun 23 06:27:54 PM PDT 24
Peak memory	203088 kb
Host	smart-51c9a9fd-4008-4e96-b55a-5a95df49ce81
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373997063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_esc alation.373997063
Directory	/workspace/38.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/38.sram_ctrl_max_throughput.230986180
Short name	T617
Test name
Test status
Simulation time	124657886 ps
CPU time	107.56 seconds
Started	Jun 23 06:27:51 PM PDT 24
Finished	Jun 23 06:29:38 PM PDT 24
Peak memory	357760 kb
Host	smart-55bf40cb-a349-4f42-a38b-a1d1c8fde69c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230986180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.sram_ctrl_max_throughput.230986180
Directory	/workspace/38.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2959673842
Short name	T48
Test name
Test status
Simulation time	103103350 ps
CPU time	5.08 seconds
Started	Jun 23 06:27:46 PM PDT 24
Finished	Jun 23 06:27:52 PM PDT 24
Peak memory	211276 kb
Host	smart-9f1fa873-4516-4a8c-8cee-550eb2980b3b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959673842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.2959673842
Directory	/workspace/38.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_walk.398567016
Short name	T268
Test name
Test status
Simulation time	139175594 ps
CPU time	8.48 seconds
Started	Jun 23 06:27:46 PM PDT 24
Finished	Jun 23 06:27:55 PM PDT 24
Peak memory	211300 kb
Host	smart-5530a26c-f66e-4ced-8043-9ccf1046b037
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398567016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _mem_walk.398567016
Directory	/workspace/38.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/38.sram_ctrl_multiple_keys.1978236050
Short name	T381
Test name
Test status
Simulation time	11181098801 ps
CPU time	641.71 seconds
Started	Jun 23 06:27:47 PM PDT 24
Finished	Jun 23 06:38:29 PM PDT 24
Peak memory	373688 kb
Host	smart-93928f4a-67aa-4787-bbb6-89749aa1c8f4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978236050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.1978236050
Directory	/workspace/38.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access.1239011056
Short name	T364
Test name
Test status
Simulation time	237352678 ps
CPU time	13.42 seconds
Started	Jun 23 06:27:48 PM PDT 24
Finished	Jun 23 06:28:02 PM PDT 24
Peak memory	203032 kb
Host	smart-9927ea60-0ca1-4628-9dae-277aff599dcb
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239011056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.1239011056
Directory	/workspace/38.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.560743453
Short name	T523
Test name
Test status
Simulation time	21162467494 ps
CPU time	329.79 seconds
Started	Jun 23 06:27:50 PM PDT 24
Finished	Jun 23 06:33:20 PM PDT 24
Peak memory	203212 kb
Host	smart-9be489a6-9d78-4089-be27-e438c08be836
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560743453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.sram_ctrl_partial_access_b2b.560743453
Directory	/workspace/38.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/38.sram_ctrl_ram_cfg.3987816303
Short name	T561
Test name
Test status
Simulation time	76380793 ps
CPU time	0.76 seconds
Started	Jun 23 06:27:48 PM PDT 24
Finished	Jun 23 06:27:49 PM PDT 24
Peak memory	203124 kb
Host	smart-4bd335b7-53c0-4387-9e56-93534f7e7c2d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987816303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3987816303
Directory	/workspace/38.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/38.sram_ctrl_regwen.2846811026
Short name	T171
Test name
Test status
Simulation time	53270097534 ps
CPU time	897.62 seconds
Started	Jun 23 06:27:51 PM PDT 24
Finished	Jun 23 06:42:49 PM PDT 24
Peak memory	376012 kb
Host	smart-c4c73fd2-fedb-4611-981e-73031d834bca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846811026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2846811026
Directory	/workspace/38.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/38.sram_ctrl_smoke.871041405
Short name	T873
Test name
Test status
Simulation time	55397037 ps
CPU time	5.24 seconds
Started	Jun 23 06:27:48 PM PDT 24
Finished	Jun 23 06:27:53 PM PDT 24
Peak memory	225180 kb
Host	smart-b0c64656-74bc-446d-8ad3-48d70b2f4ea1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871041405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.871041405
Directory	/workspace/38.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all.2244010439
Short name	T135
Test name
Test status
Simulation time	25470157257 ps
CPU time	2520.04 seconds
Started	Jun 23 06:27:49 PM PDT 24
Finished	Jun 23 07:09:50 PM PDT 24
Peak memory	377256 kb
Host	smart-21276c17-b6e7-4773-af6e-e64fd5e0bbd5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244010439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.2244010439
Directory	/workspace/38.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2157500190
Short name	T792
Test name
Test status
Simulation time	4203420927 ps
CPU time	274.64 seconds
Started	Jun 23 06:27:49 PM PDT 24
Finished	Jun 23 06:32:24 PM PDT 24
Peak memory	384208 kb
Host	smart-59f5a38c-0fd9-44c9-9a59-25abb5ba4d73
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2157500190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2157500190
Directory	/workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.573364821
Short name	T429
Test name
Test status
Simulation time	10009338140 ps
CPU time	237.41 seconds
Started	Jun 23 06:27:46 PM PDT 24
Finished	Jun 23 06:31:44 PM PDT 24
Peak memory	203056 kb
Host	smart-6c7ca3c8-9465-4411-860a-333b1d3dc443
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573364821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .sram_ctrl_stress_pipeline.573364821
Directory	/workspace/38.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1423926249
Short name	T775
Test name
Test status
Simulation time	74114208 ps
CPU time	7.42 seconds
Started	Jun 23 06:27:49 PM PDT 24
Finished	Jun 23 06:27:57 PM PDT 24
Peak memory	238992 kb
Host	smart-776b1d63-5e4f-4e00-8ea9-f21f3d5d0653
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423926249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1423926249
Directory	/workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1771720681
Short name	T180
Test name
Test status
Simulation time	1383291631 ps
CPU time	32.53 seconds
Started	Jun 23 06:27:53 PM PDT 24
Finished	Jun 23 06:28:26 PM PDT 24
Peak memory	257916 kb
Host	smart-b8511636-ec27-4fff-a9dc-33d45b06e91f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771720681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.1771720681
Directory	/workspace/39.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/39.sram_ctrl_alert_test.2076420986
Short name	T433
Test name
Test status
Simulation time	49310347 ps
CPU time	0.66 seconds
Started	Jun 23 06:27:57 PM PDT 24
Finished	Jun 23 06:27:58 PM PDT 24
Peak memory	202916 kb
Host	smart-6d9e32de-8733-4bc2-93db-f76dba4f2518
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076420986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2076420986
Directory	/workspace/39.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.sram_ctrl_bijection.2146274180
Short name	T537
Test name
Test status
Simulation time	10777144606 ps
CPU time	84.24 seconds
Started	Jun 23 06:27:56 PM PDT 24
Finished	Jun 23 06:29:20 PM PDT 24
Peak memory	203120 kb
Host	smart-ee6296fe-ad93-4e08-8829-08d84e29084f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146274180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .2146274180
Directory	/workspace/39.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/39.sram_ctrl_executable.3152663328
Short name	T500
Test name
Test status
Simulation time	44679017152 ps
CPU time	806.42 seconds
Started	Jun 23 06:27:56 PM PDT 24
Finished	Jun 23 06:41:22 PM PDT 24
Peak memory	368784 kb
Host	smart-4cb2553a-cf34-4377-92d3-0969bb4715a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152663328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.3152663328
Directory	/workspace/39.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/39.sram_ctrl_lc_escalation.345648154
Short name	T321
Test name
Test status
Simulation time	700919937 ps
CPU time	4.51 seconds
Started	Jun 23 06:27:50 PM PDT 24
Finished	Jun 23 06:27:55 PM PDT 24
Peak memory	203108 kb
Host	smart-f7f4ed00-f8da-4930-8adf-07f3e8ffec47
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345648154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_esc alation.345648154
Directory	/workspace/39.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/39.sram_ctrl_max_throughput.634420919
Short name	T581
Test name
Test status
Simulation time	748703139 ps
CPU time	168.4 seconds
Started	Jun 23 06:27:53 PM PDT 24
Finished	Jun 23 06:30:41 PM PDT 24
Peak memory	369980 kb
Host	smart-a0016582-7454-49c9-a919-34ca74ac8039
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634420919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.sram_ctrl_max_throughput.634420919
Directory	/workspace/39.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.4152900612
Short name	T756
Test name
Test status
Simulation time	106447345 ps
CPU time	5.23 seconds
Started	Jun 23 06:27:56 PM PDT 24
Finished	Jun 23 06:28:02 PM PDT 24
Peak memory	211344 kb
Host	smart-7e5eea26-be3c-4eca-b033-2563efab0fbb
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152900612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.4152900612
Directory	/workspace/39.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_walk.3320692822
Short name	T860
Test name
Test status
Simulation time	361986350 ps
CPU time	9.65 seconds
Started	Jun 23 06:27:52 PM PDT 24
Finished	Jun 23 06:28:02 PM PDT 24
Peak memory	211248 kb
Host	smart-7d068d2f-bccd-417f-af6c-6604e9d942f9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320692822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.3320692822
Directory	/workspace/39.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/39.sram_ctrl_multiple_keys.592432945
Short name	T2
Test name
Test status
Simulation time	2440337814 ps
CPU time	670.78 seconds
Started	Jun 23 06:27:51 PM PDT 24
Finished	Jun 23 06:39:02 PM PDT 24
Peak memory	358004 kb
Host	smart-4d9bb0f9-8b8e-42ff-9de3-9541dbdd6cf0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592432945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multip le_keys.592432945
Directory	/workspace/39.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access.3344703007
Short name	T642
Test name
Test status
Simulation time	5133922416 ps
CPU time	12.81 seconds
Started	Jun 23 06:27:51 PM PDT 24
Finished	Jun 23 06:28:04 PM PDT 24
Peak memory	203124 kb
Host	smart-4eaad955-e852-4a27-a1d2-c2e222af6ce3
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344703007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.3344703007
Directory	/workspace/39.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1156947563
Short name	T659
Test name
Test status
Simulation time	16071376059 ps
CPU time	443.37 seconds
Started	Jun 23 06:27:52 PM PDT 24
Finished	Jun 23 06:35:16 PM PDT 24
Peak memory	203188 kb
Host	smart-a4f37335-0867-463b-988e-00c185642297
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156947563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.1156947563
Directory	/workspace/39.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/39.sram_ctrl_ram_cfg.3300644574
Short name	T731
Test name
Test status
Simulation time	48513335 ps
CPU time	0.73 seconds
Started	Jun 23 06:27:51 PM PDT 24
Finished	Jun 23 06:27:52 PM PDT 24
Peak memory	203100 kb
Host	smart-7f891685-ef5a-4a07-bf33-66ab9c7d78fd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300644574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3300644574
Directory	/workspace/39.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/39.sram_ctrl_regwen.2442369014
Short name	T32
Test name
Test status
Simulation time	4023816570 ps
CPU time	1814.86 seconds
Started	Jun 23 06:27:52 PM PDT 24
Finished	Jun 23 06:58:07 PM PDT 24
Peak memory	375168 kb
Host	smart-7f5aeea6-e32a-4bb8-9e8d-97ad5b29578a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442369014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2442369014
Directory	/workspace/39.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/39.sram_ctrl_smoke.701089981
Short name	T499
Test name
Test status
Simulation time	2361665932 ps
CPU time	14.49 seconds
Started	Jun 23 06:27:47 PM PDT 24
Finished	Jun 23 06:28:02 PM PDT 24
Peak memory	203120 kb
Host	smart-b7d89f59-65ba-4340-933d-3d6b0c8972db
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701089981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.701089981
Directory	/workspace/39.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all.2993129546
Short name	T716
Test name
Test status
Simulation time	4167326411 ps
CPU time	2060.87 seconds
Started	Jun 23 06:27:57 PM PDT 24
Finished	Jun 23 07:02:19 PM PDT 24
Peak memory	375948 kb
Host	smart-8bc44cc3-2357-4a3a-8f6f-6ab919f03d93
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993129546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.2993129546
Directory	/workspace/39.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1013814203
Short name	T914
Test name
Test status
Simulation time	12334405466 ps
CPU time	63.6 seconds
Started	Jun 23 06:28:00 PM PDT 24
Finished	Jun 23 06:29:03 PM PDT 24
Peak memory	292108 kb
Host	smart-e444b88a-730a-4d21-aeb0-56dcc5f05741
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1013814203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1013814203
Directory	/workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1655798004
Short name	T193
Test name
Test status
Simulation time	29430958240 ps
CPU time	184.84 seconds
Started	Jun 23 06:27:56 PM PDT 24
Finished	Jun 23 06:31:01 PM PDT 24
Peak memory	203128 kb
Host	smart-dc9d8447-b996-4c9e-a3f9-bf248d076b43
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655798004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1655798004
Directory	/workspace/39.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1297688122
Short name	T386
Test name
Test status
Simulation time	42722115 ps
CPU time	2.35 seconds
Started	Jun 23 06:27:54 PM PDT 24
Finished	Jun 23 06:27:56 PM PDT 24
Peak memory	217308 kb
Host	smart-cbf64add-2a84-4f5e-a80a-68612345cf64
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297688122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1297688122
Directory	/workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/4.sram_ctrl_access_during_key_req.131083031
Short name	T447
Test name
Test status
Simulation time	9217941755 ps
CPU time	482.51 seconds
Started	Jun 23 06:24:42 PM PDT 24
Finished	Jun 23 06:32:44 PM PDT 24
Peak memory	341008 kb
Host	smart-f69b8519-2b3d-4a41-9da9-92e1de7541a5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131083031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.sram_ctrl_access_during_key_req.131083031
Directory	/workspace/4.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/4.sram_ctrl_alert_test.4052233119
Short name	T13
Test name
Test status
Simulation time	13513903 ps
CPU time	0.67 seconds
Started	Jun 23 06:24:43 PM PDT 24
Finished	Jun 23 06:24:44 PM PDT 24
Peak memory	202940 kb
Host	smart-72eee81d-3c64-428b-890a-191cfdd57a33
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052233119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.4052233119
Directory	/workspace/4.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.sram_ctrl_bijection.3321212722
Short name	T805
Test name
Test status
Simulation time	8971502935 ps
CPU time	26.89 seconds
Started	Jun 23 06:24:45 PM PDT 24
Finished	Jun 23 06:25:12 PM PDT 24
Peak memory	203084 kb
Host	smart-416c9cb5-2dc9-4507-a2f8-d76a9aadc393
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321212722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 3321212722
Directory	/workspace/4.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/4.sram_ctrl_executable.991932566
Short name	T599
Test name
Test status
Simulation time	2130230834 ps
CPU time	736.79 seconds
Started	Jun 23 06:24:39 PM PDT 24
Finished	Jun 23 06:36:57 PM PDT 24
Peak memory	374984 kb
Host	smart-312c3231-4e48-4722-b602-12612def8138
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991932566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable .991932566
Directory	/workspace/4.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/4.sram_ctrl_lc_escalation.4068731377
Short name	T758
Test name
Test status
Simulation time	578048611 ps
CPU time	6.04 seconds
Started	Jun 23 06:24:40 PM PDT 24
Finished	Jun 23 06:24:46 PM PDT 24
Peak memory	203084 kb
Host	smart-96417469-5e01-44d9-a581-9d213457a960
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068731377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.4068731377
Directory	/workspace/4.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/4.sram_ctrl_max_throughput.281524164
Short name	T297
Test name
Test status
Simulation time	44574802 ps
CPU time	1.39 seconds
Started	Jun 23 06:24:42 PM PDT 24
Finished	Jun 23 06:24:43 PM PDT 24
Peak memory	211212 kb
Host	smart-50e7c5fe-fde0-40d3-beda-a3978193ab3c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281524164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.sram_ctrl_max_throughput.281524164
Directory	/workspace/4.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.906184935
Short name	T592
Test name
Test status
Simulation time	370489393 ps
CPU time	3.18 seconds
Started	Jun 23 06:24:46 PM PDT 24
Finished	Jun 23 06:24:50 PM PDT 24
Peak memory	211292 kb
Host	smart-ce028989-b7ff-476b-8b02-0a5db4190d46
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906184935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. sram_ctrl_mem_partial_access.906184935
Directory	/workspace/4.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_walk.3356498749
Short name	T615
Test name
Test status
Simulation time	136788392 ps
CPU time	8.22 seconds
Started	Jun 23 06:24:44 PM PDT 24
Finished	Jun 23 06:24:53 PM PDT 24
Peak memory	211256 kb
Host	smart-2cef350f-a17a-4848-a838-43a9f2554269
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356498749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.3356498749
Directory	/workspace/4.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/4.sram_ctrl_multiple_keys.1875284264
Short name	T508
Test name
Test status
Simulation time	66202104846 ps
CPU time	779.02 seconds
Started	Jun 23 06:24:40 PM PDT 24
Finished	Jun 23 06:37:39 PM PDT 24
Peak memory	353416 kb
Host	smart-d0fe3159-ada9-4d7e-b6c1-acb25e388b27
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875284264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.1875284264
Directory	/workspace/4.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access.788082977
Short name	T265
Test name
Test status
Simulation time	569233017 ps
CPU time	82.26 seconds
Started	Jun 23 06:24:45 PM PDT 24
Finished	Jun 23 06:26:08 PM PDT 24
Peak memory	332864 kb
Host	smart-999a8aba-dec9-4e60-a643-fa85fd12d2a5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788082977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr am_ctrl_partial_access.788082977
Directory	/workspace/4.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1318265583
Short name	T636
Test name
Test status
Simulation time	11651257815 ps
CPU time	418.54 seconds
Started	Jun 23 06:24:41 PM PDT 24
Finished	Jun 23 06:31:40 PM PDT 24
Peak memory	203176 kb
Host	smart-9cdbc5ec-08c5-4aec-8bf0-c4fefa47b8c8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318265583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.1318265583
Directory	/workspace/4.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/4.sram_ctrl_ram_cfg.671644756
Short name	T801
Test name
Test status
Simulation time	28355412 ps
CPU time	0.75 seconds
Started	Jun 23 06:24:46 PM PDT 24
Finished	Jun 23 06:24:47 PM PDT 24
Peak memory	203052 kb
Host	smart-445eb33b-22a2-42f4-85c0-b5e86cf93743
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671644756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.671644756
Directory	/workspace/4.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/4.sram_ctrl_regwen.2738715917
Short name	T904
Test name
Test status
Simulation time	28354133449 ps
CPU time	1072.38 seconds
Started	Jun 23 06:24:39 PM PDT 24
Finished	Jun 23 06:42:32 PM PDT 24
Peak memory	375948 kb
Host	smart-211db1c5-96a8-4ac6-90cd-4983b19650b8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738715917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.2738715917
Directory	/workspace/4.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/4.sram_ctrl_sec_cm.1112676132
Short name	T28
Test name
Test status
Simulation time	389327065 ps
CPU time	2.03 seconds
Started	Jun 23 06:24:45 PM PDT 24
Finished	Jun 23 06:24:47 PM PDT 24
Peak memory	222040 kb
Host	smart-8b98f23c-663e-4b7f-9e58-e167500ca2a3
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112676132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1112676132
Directory	/workspace/4.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.sram_ctrl_smoke.1503450983
Short name	T252
Test name
Test status
Simulation time	2356058152 ps
CPU time	162.36 seconds
Started	Jun 23 06:24:42 PM PDT 24
Finished	Jun 23 06:27:24 PM PDT 24
Peak memory	367312 kb
Host	smart-2f978a71-1396-4b97-8d65-015a5e28e9f8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503450983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1503450983
Directory	/workspace/4.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_all.1987010571
Short name	T785
Test name
Test status
Simulation time	122162602922 ps
CPU time	2578.49 seconds
Started	Jun 23 06:24:45 PM PDT 24
Finished	Jun 23 07:07:45 PM PDT 24
Peak memory	383996 kb
Host	smart-dfca351b-1d38-418b-acb9-86a62ed77eb8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987010571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.1987010571
Directory	/workspace/4.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3834579209
Short name	T197
Test name
Test status
Simulation time	12873691629 ps
CPU time	244.69 seconds
Started	Jun 23 06:24:40 PM PDT 24
Finished	Jun 23 06:28:45 PM PDT 24
Peak memory	203172 kb
Host	smart-f46b6d33-2dee-40f4-987d-22ddae076cf2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834579209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.3834579209
Directory	/workspace/4.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1387935040
Short name	T175
Test name
Test status
Simulation time	518577956 ps
CPU time	57.6 seconds
Started	Jun 23 06:24:41 PM PDT 24
Finished	Jun 23 06:25:39 PM PDT 24
Peak memory	332864 kb
Host	smart-5f48a02a-7251-4826-90be-45e45b63de96
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387935040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1387935040
Directory	/workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2953694948
Short name	T534
Test name
Test status
Simulation time	6487083882 ps
CPU time	664.25 seconds
Started	Jun 23 06:27:58 PM PDT 24
Finished	Jun 23 06:39:02 PM PDT 24
Peak memory	370664 kb
Host	smart-3bddc7ad-887a-4ac6-a634-9a0e67db5b2f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953694948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.2953694948
Directory	/workspace/40.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/40.sram_ctrl_alert_test.3077741456
Short name	T14
Test name
Test status
Simulation time	37267165 ps
CPU time	0.59 seconds
Started	Jun 23 06:28:03 PM PDT 24
Finished	Jun 23 06:28:04 PM PDT 24
Peak memory	202892 kb
Host	smart-2a1d0721-5ec4-4532-b7b5-a32671d9a4d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077741456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.3077741456
Directory	/workspace/40.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.sram_ctrl_bijection.3752615892
Short name	T917
Test name
Test status
Simulation time	1414526475 ps
CPU time	41.62 seconds
Started	Jun 23 06:27:56 PM PDT 24
Finished	Jun 23 06:28:38 PM PDT 24
Peak memory	202992 kb
Host	smart-98cde356-817b-4a89-b774-9a8cbba7acff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752615892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .3752615892
Directory	/workspace/40.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/40.sram_ctrl_executable.2524070792
Short name	T720
Test name
Test status
Simulation time	3756337073 ps
CPU time	931.71 seconds
Started	Jun 23 06:28:02 PM PDT 24
Finished	Jun 23 06:43:34 PM PDT 24
Peak memory	375012 kb
Host	smart-f39350f9-cb50-4d27-b143-51aa6f4a9ff3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524070792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.2524070792
Directory	/workspace/40.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/40.sram_ctrl_lc_escalation.1380632561
Short name	T494
Test name
Test status
Simulation time	954852953 ps
CPU time	8.91 seconds
Started	Jun 23 06:27:58 PM PDT 24
Finished	Jun 23 06:28:07 PM PDT 24
Peak memory	211496 kb
Host	smart-3aac9261-3080-43eb-91ce-6194b1cd1b86
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380632561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.1380632561
Directory	/workspace/40.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/40.sram_ctrl_max_throughput.4052776819
Short name	T191
Test name
Test status
Simulation time	745810996 ps
CPU time	17.96 seconds
Started	Jun 23 06:27:57 PM PDT 24
Finished	Jun 23 06:28:15 PM PDT 24
Peak memory	265264 kb
Host	smart-a75c0a19-17d7-416d-8e8f-cae175968463
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052776819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.4052776819
Directory	/workspace/40.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.370159606
Short name	T450
Test name
Test status
Simulation time	580534745 ps
CPU time	5.66 seconds
Started	Jun 23 06:28:00 PM PDT 24
Finished	Jun 23 06:28:06 PM PDT 24
Peak memory	211212 kb
Host	smart-eb30f3e5-d09e-4134-ae05-3c206f3af31c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370159606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sram_ctrl_mem_partial_access.370159606
Directory	/workspace/40.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_walk.877012178
Short name	T56
Test name
Test status
Simulation time	72718398 ps
CPU time	4.73 seconds
Started	Jun 23 06:28:02 PM PDT 24
Finished	Jun 23 06:28:07 PM PDT 24
Peak memory	211228 kb
Host	smart-a92c7c64-56a8-4410-81c2-1ff656860716
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877012178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl _mem_walk.877012178
Directory	/workspace/40.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access.2410593078
Short name	T176
Test name
Test status
Simulation time	104416847 ps
CPU time	4.47 seconds
Started	Jun 23 06:27:57 PM PDT 24
Finished	Jun 23 06:28:02 PM PDT 24
Peak memory	203140 kb
Host	smart-6848c9ab-d887-486a-b66f-8fde6dff4296
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410593078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.2410593078
Directory	/workspace/40.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4112833870
Short name	T680
Test name
Test status
Simulation time	6212835395 ps
CPU time	160.6 seconds
Started	Jun 23 06:27:56 PM PDT 24
Finished	Jun 23 06:30:37 PM PDT 24
Peak memory	203124 kb
Host	smart-ed667c70-4397-42cb-8bfb-593106c4af28
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112833870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.4112833870
Directory	/workspace/40.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/40.sram_ctrl_ram_cfg.2956060699
Short name	T558
Test name
Test status
Simulation time	72074349 ps
CPU time	0.79 seconds
Started	Jun 23 06:28:01 PM PDT 24
Finished	Jun 23 06:28:02 PM PDT 24
Peak memory	203124 kb
Host	smart-c12ec0f0-1960-452d-a79e-7fbc56fdaeca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956060699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2956060699
Directory	/workspace/40.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/40.sram_ctrl_regwen.3129530296
Short name	T452
Test name
Test status
Simulation time	11431464819 ps
CPU time	100.88 seconds
Started	Jun 23 06:28:04 PM PDT 24
Finished	Jun 23 06:29:45 PM PDT 24
Peak memory	322712 kb
Host	smart-df5398ba-479d-4ccc-b36b-dc15074602df
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129530296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3129530296
Directory	/workspace/40.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/40.sram_ctrl_smoke.842525876
Short name	T229
Test name
Test status
Simulation time	374492780 ps
CPU time	33.8 seconds
Started	Jun 23 06:27:55 PM PDT 24
Finished	Jun 23 06:28:29 PM PDT 24
Peak memory	287888 kb
Host	smart-209324b0-31c9-4480-a6c0-95cdec81ccec
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842525876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.842525876
Directory	/workspace/40.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_all.522737058
Short name	T628
Test name
Test status
Simulation time	130923553184 ps
CPU time	2801.64 seconds
Started	Jun 23 06:28:01 PM PDT 24
Finished	Jun 23 07:14:43 PM PDT 24
Peak memory	383176 kb
Host	smart-0c4fc711-15f4-43eb-9dd4-f6571db3efdd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522737058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_stress_all.522737058
Directory	/workspace/40.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2320017285
Short name	T384
Test name
Test status
Simulation time	227698488 ps
CPU time	46.35 seconds
Started	Jun 23 06:28:03 PM PDT 24
Finished	Jun 23 06:28:49 PM PDT 24
Peak memory	301260 kb
Host	smart-e964e3da-a973-49e5-8c5c-bdc97a52d196
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2320017285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2320017285
Directory	/workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2814646892
Short name	T373
Test name
Test status
Simulation time	3411169539 ps
CPU time	323.77 seconds
Started	Jun 23 06:27:56 PM PDT 24
Finished	Jun 23 06:33:21 PM PDT 24
Peak memory	203164 kb
Host	smart-aa74c8e4-102a-433a-8e01-80908c77fcb8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814646892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.2814646892
Directory	/workspace/40.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.553243341
Short name	T168
Test name
Test status
Simulation time	140051005 ps
CPU time	102.85 seconds
Started	Jun 23 06:27:57 PM PDT 24
Finished	Jun 23 06:29:40 PM PDT 24
Peak memory	350148 kb
Host	smart-5b3d37cc-ea8f-47ed-8f8b-bfd7dc7f5600
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553243341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_throughput_w_partial_write.553243341
Directory	/workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3086532364
Short name	T562
Test name
Test status
Simulation time	24663165573 ps
CPU time	1136.52 seconds
Started	Jun 23 06:28:03 PM PDT 24
Finished	Jun 23 06:47:00 PM PDT 24
Peak memory	369308 kb
Host	smart-f1db2e63-4b99-462e-b8f0-679b91d00544
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086532364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.3086532364
Directory	/workspace/41.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/41.sram_ctrl_alert_test.2241301690
Short name	T389
Test name
Test status
Simulation time	35511448 ps
CPU time	0.67 seconds
Started	Jun 23 06:28:07 PM PDT 24
Finished	Jun 23 06:28:08 PM PDT 24
Peak memory	202984 kb
Host	smart-daaeb0c3-4469-4eff-9f46-4cab55d77045
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241301690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2241301690
Directory	/workspace/41.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.sram_ctrl_bijection.801351552
Short name	T493
Test name
Test status
Simulation time	1490745468 ps
CPU time	33.8 seconds
Started	Jun 23 06:28:01 PM PDT 24
Finished	Jun 23 06:28:35 PM PDT 24
Peak memory	203140 kb
Host	smart-4cd2de81-6b16-4283-aad1-363c7941f93f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801351552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection. 801351552
Directory	/workspace/41.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/41.sram_ctrl_executable.3906208313
Short name	T671
Test name
Test status
Simulation time	2688742042 ps
CPU time	866.01 seconds
Started	Jun 23 06:28:02 PM PDT 24
Finished	Jun 23 06:42:28 PM PDT 24
Peak memory	374848 kb
Host	smart-279beb14-5f67-4c07-b124-aed048611a44
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906208313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.3906208313
Directory	/workspace/41.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/41.sram_ctrl_lc_escalation.1097908975
Short name	T310
Test name
Test status
Simulation time	725314281 ps
CPU time	6.88 seconds
Started	Jun 23 06:28:04 PM PDT 24
Finished	Jun 23 06:28:11 PM PDT 24
Peak memory	211228 kb
Host	smart-fbfd7c42-bbd4-4e5a-a694-fbf4a770d109
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097908975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.1097908975
Directory	/workspace/41.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/41.sram_ctrl_max_throughput.3885846301
Short name	T858
Test name
Test status
Simulation time	133568731 ps
CPU time	59.41 seconds
Started	Jun 23 06:28:01 PM PDT 24
Finished	Jun 23 06:29:01 PM PDT 24
Peak memory	309720 kb
Host	smart-2183efc6-968b-4b07-a77f-cec26b11e895
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885846301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.3885846301
Directory	/workspace/41.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2578214504
Short name	T905
Test name
Test status
Simulation time	202673458 ps
CPU time	5.77 seconds
Started	Jun 23 06:28:06 PM PDT 24
Finished	Jun 23 06:28:12 PM PDT 24
Peak memory	211140 kb
Host	smart-a820eb73-6701-4d80-9e1f-f066c36aedc1
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578214504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.2578214504
Directory	/workspace/41.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_walk.2696107244
Short name	T875
Test name
Test status
Simulation time	685105986 ps
CPU time	9.41 seconds
Started	Jun 23 06:28:01 PM PDT 24
Finished	Jun 23 06:28:11 PM PDT 24
Peak memory	211248 kb
Host	smart-6e0f7cd4-1d56-48c0-8d9c-e1d424af0d21
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696107244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.2696107244
Directory	/workspace/41.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/41.sram_ctrl_multiple_keys.2053995840
Short name	T292
Test name
Test status
Simulation time	2074964781 ps
CPU time	539.04 seconds
Started	Jun 23 06:28:02 PM PDT 24
Finished	Jun 23 06:37:02 PM PDT 24
Peak memory	373840 kb
Host	smart-adf84452-6a96-46d7-8eef-c20c3803f394
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053995840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.2053995840
Directory	/workspace/41.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access.1304211691
Short name	T3
Test name
Test status
Simulation time	49680077 ps
CPU time	3.31 seconds
Started	Jun 23 06:28:03 PM PDT 24
Finished	Jun 23 06:28:07 PM PDT 24
Peak memory	215060 kb
Host	smart-57423356-bf9f-4551-ab6f-ecc8d5a7de3c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304211691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.1304211691
Directory	/workspace/41.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1393179293
Short name	T927
Test name
Test status
Simulation time	18859911331 ps
CPU time	501.37 seconds
Started	Jun 23 06:28:01 PM PDT 24
Finished	Jun 23 06:36:23 PM PDT 24
Peak memory	203188 kb
Host	smart-a46b6ec9-1ea8-40f8-afe2-4ad19928447b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393179293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.1393179293
Directory	/workspace/41.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/41.sram_ctrl_ram_cfg.2075196984
Short name	T410
Test name
Test status
Simulation time	74000557 ps
CPU time	0.74 seconds
Started	Jun 23 06:28:00 PM PDT 24
Finished	Jun 23 06:28:01 PM PDT 24
Peak memory	203124 kb
Host	smart-5638cb84-48c5-4090-8388-72fb4f6a8fc8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075196984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2075196984
Directory	/workspace/41.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/41.sram_ctrl_regwen.1094123686
Short name	T735
Test name
Test status
Simulation time	13618720371 ps
CPU time	1730.2 seconds
Started	Jun 23 06:28:02 PM PDT 24
Finished	Jun 23 06:56:53 PM PDT 24
Peak memory	374904 kb
Host	smart-2f2d6879-ad53-46c0-ad09-c0901204dbf1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094123686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1094123686
Directory	/workspace/41.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/41.sram_ctrl_smoke.3351396922
Short name	T289
Test name
Test status
Simulation time	8433153683 ps
CPU time	17.55 seconds
Started	Jun 23 06:28:02 PM PDT 24
Finished	Jun 23 06:28:20 PM PDT 24
Peak memory	203160 kb
Host	smart-789b9b48-0f64-4b0f-8e64-0e2133c16d38
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351396922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3351396922
Directory	/workspace/41.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all.3088132612
Short name	T545
Test name
Test status
Simulation time	13048132625 ps
CPU time	713.97 seconds
Started	Jun 23 06:28:06 PM PDT 24
Finished	Jun 23 06:40:00 PM PDT 24
Peak memory	375992 kb
Host	smart-97fb8c16-3438-4db9-b081-bf6cef6c51fa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088132612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.3088132612
Directory	/workspace/41.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.389163949
Short name	T574
Test name
Test status
Simulation time	2252688872 ps
CPU time	255.26 seconds
Started	Jun 23 06:28:05 PM PDT 24
Finished	Jun 23 06:32:21 PM PDT 24
Peak memory	360404 kb
Host	smart-01206e3b-76f8-4bd8-aa33-37300282228b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=389163949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.389163949
Directory	/workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1857303211
Short name	T791
Test name
Test status
Simulation time	42409676142 ps
CPU time	262.13 seconds
Started	Jun 23 06:28:01 PM PDT 24
Finished	Jun 23 06:32:24 PM PDT 24
Peak memory	203204 kb
Host	smart-321ed639-9222-46c5-9ac4-60d9e2097661
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857303211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.1857303211
Directory	/workspace/41.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1948657794
Short name	T326
Test name
Test status
Simulation time	334315452 ps
CPU time	34.97 seconds
Started	Jun 23 06:28:01 PM PDT 24
Finished	Jun 23 06:28:37 PM PDT 24
Peak memory	287944 kb
Host	smart-2c42aa9d-4a08-4f5f-ab8c-2ee2c80ba51b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948657794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1948657794
Directory	/workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/42.sram_ctrl_access_during_key_req.4114378430
Short name	T462
Test name
Test status
Simulation time	3272522332 ps
CPU time	1470.77 seconds
Started	Jun 23 06:28:10 PM PDT 24
Finished	Jun 23 06:52:42 PM PDT 24
Peak memory	374956 kb
Host	smart-0506e9da-1d49-484e-9045-8505a82f4cea
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114378430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.4114378430
Directory	/workspace/42.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/42.sram_ctrl_alert_test.2201083693
Short name	T570
Test name
Test status
Simulation time	32447177 ps
CPU time	0.68 seconds
Started	Jun 23 06:28:17 PM PDT 24
Finished	Jun 23 06:28:18 PM PDT 24
Peak memory	202920 kb
Host	smart-efb1ea73-5cc9-475e-9e41-215df5210c5c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201083693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2201083693
Directory	/workspace/42.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.sram_ctrl_bijection.1408110251
Short name	T852
Test name
Test status
Simulation time	802680987 ps
CPU time	26.18 seconds
Started	Jun 23 06:28:06 PM PDT 24
Finished	Jun 23 06:28:32 PM PDT 24
Peak memory	203060 kb
Host	smart-e1532b3f-a221-4a87-b791-b202009bdb8e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408110251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .1408110251
Directory	/workspace/42.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/42.sram_ctrl_executable.2878205481
Short name	T222
Test name
Test status
Simulation time	2300546220 ps
CPU time	1102.41 seconds
Started	Jun 23 06:28:11 PM PDT 24
Finished	Jun 23 06:46:33 PM PDT 24
Peak memory	374832 kb
Host	smart-5c89228d-3d52-442e-a5b5-627edde66e43
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878205481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.2878205481
Directory	/workspace/42.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/42.sram_ctrl_lc_escalation.1218818825
Short name	T111
Test name
Test status
Simulation time	597922230 ps
CPU time	2.21 seconds
Started	Jun 23 06:28:11 PM PDT 24
Finished	Jun 23 06:28:14 PM PDT 24
Peak memory	211276 kb
Host	smart-30df1a0a-8850-4490-87d4-945f559ae4ad
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218818825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.1218818825
Directory	/workspace/42.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/42.sram_ctrl_max_throughput.1298496850
Short name	T205
Test name
Test status
Simulation time	119028602 ps
CPU time	46.89 seconds
Started	Jun 23 06:28:11 PM PDT 24
Finished	Jun 23 06:28:59 PM PDT 24
Peak memory	301132 kb
Host	smart-2eda51f4-14d1-4540-a03a-fd685345f978
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298496850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.1298496850
Directory	/workspace/42.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1882776855
Short name	T730
Test name
Test status
Simulation time	182724661 ps
CPU time	3.03 seconds
Started	Jun 23 06:28:11 PM PDT 24
Finished	Jun 23 06:28:14 PM PDT 24
Peak memory	211312 kb
Host	smart-a58f1436-2551-4f46-8928-a1c5a5887feb
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882776855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.1882776855
Directory	/workspace/42.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_walk.136775524
Short name	T334
Test name
Test status
Simulation time	1510605572 ps
CPU time	10.7 seconds
Started	Jun 23 06:28:10 PM PDT 24
Finished	Jun 23 06:28:22 PM PDT 24
Peak memory	211260 kb
Host	smart-61330925-2269-466e-b1c8-2ddca8c7f60b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136775524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl _mem_walk.136775524
Directory	/workspace/42.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/42.sram_ctrl_multiple_keys.1458820635
Short name	T397
Test name
Test status
Simulation time	182304378 ps
CPU time	36.13 seconds
Started	Jun 23 06:28:06 PM PDT 24
Finished	Jun 23 06:28:43 PM PDT 24
Peak memory	276920 kb
Host	smart-3405e69e-9b22-427c-9168-34dbfa23449f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458820635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.1458820635
Directory	/workspace/42.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access.2913164366
Short name	T624
Test name
Test status
Simulation time	1912874539 ps
CPU time	10.02 seconds
Started	Jun 23 06:28:10 PM PDT 24
Finished	Jun 23 06:28:20 PM PDT 24
Peak memory	203100 kb
Host	smart-a7a81353-8e72-4c59-85b5-968d0193d160
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913164366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.2913164366
Directory	/workspace/42.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.634065692
Short name	T303
Test name
Test status
Simulation time	3836086462 ps
CPU time	297.57 seconds
Started	Jun 23 06:28:11 PM PDT 24
Finished	Jun 23 06:33:09 PM PDT 24
Peak memory	203188 kb
Host	smart-f0be4c80-d84b-4df7-a39e-5e22533eb525
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634065692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.sram_ctrl_partial_access_b2b.634065692
Directory	/workspace/42.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/42.sram_ctrl_ram_cfg.2581972107
Short name	T546
Test name
Test status
Simulation time	65621998 ps
CPU time	0.75 seconds
Started	Jun 23 06:28:11 PM PDT 24
Finished	Jun 23 06:28:12 PM PDT 24
Peak memory	203124 kb
Host	smart-e62af1fc-ad75-4bf8-a18a-619d1b777b8e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581972107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2581972107
Directory	/workspace/42.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/42.sram_ctrl_regwen.499054681
Short name	T513
Test name
Test status
Simulation time	37784037966 ps
CPU time	663.18 seconds
Started	Jun 23 06:28:10 PM PDT 24
Finished	Jun 23 06:39:14 PM PDT 24
Peak memory	366772 kb
Host	smart-6cceedcf-9d97-42a0-b017-6e75908d1b2b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499054681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.499054681
Directory	/workspace/42.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/42.sram_ctrl_smoke.2200783607
Short name	T621
Test name
Test status
Simulation time	1183775340 ps
CPU time	3.95 seconds
Started	Jun 23 06:28:07 PM PDT 24
Finished	Jun 23 06:28:12 PM PDT 24
Peak memory	203112 kb
Host	smart-d4ece340-83d0-48f1-beac-184a66633141
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200783607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2200783607
Directory	/workspace/42.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all.1955821067
Short name	T428
Test name
Test status
Simulation time	56033120768 ps
CPU time	2043.64 seconds
Started	Jun 23 06:28:10 PM PDT 24
Finished	Jun 23 07:02:15 PM PDT 24
Peak memory	373988 kb
Host	smart-cc969317-33ff-496c-92e9-bf646b9c6fe6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955821067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1955821067
Directory	/workspace/42.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.872217954
Short name	T519
Test name
Test status
Simulation time	8106987897 ps
CPU time	401.62 seconds
Started	Jun 23 06:28:12 PM PDT 24
Finished	Jun 23 06:34:54 PM PDT 24
Peak memory	203412 kb
Host	smart-b195de15-a2ee-406c-8bb4-a9118541034c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872217954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_stress_pipeline.872217954
Directory	/workspace/42.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.364573989
Short name	T401
Test name
Test status
Simulation time	295928142 ps
CPU time	92.46 seconds
Started	Jun 23 06:28:11 PM PDT 24
Finished	Jun 23 06:29:44 PM PDT 24
Peak memory	361268 kb
Host	smart-8b3e97ed-d134-4c3f-9bcd-6a2e90303908
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364573989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.364573989
Directory	/workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.95222567
Short name	T346
Test name
Test status
Simulation time	12772201519 ps
CPU time	1089.6 seconds
Started	Jun 23 06:28:20 PM PDT 24
Finished	Jun 23 06:46:30 PM PDT 24
Peak memory	376000 kb
Host	smart-d55e3291-bcd4-4ed7-9575-f852ebf5b5d1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95222567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.sram_ctrl_access_during_key_req.95222567
Directory	/workspace/43.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/43.sram_ctrl_alert_test.2225930230
Short name	T357
Test name
Test status
Simulation time	114237958 ps
CPU time	0.68 seconds
Started	Jun 23 06:28:20 PM PDT 24
Finished	Jun 23 06:28:21 PM PDT 24
Peak memory	202892 kb
Host	smart-a55a55ea-d733-4d26-9597-077b852b533d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225930230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2225930230
Directory	/workspace/43.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.sram_ctrl_bijection.4057288049
Short name	T434
Test name
Test status
Simulation time	1193858092 ps
CPU time	41.23 seconds
Started	Jun 23 06:28:15 PM PDT 24
Finished	Jun 23 06:28:56 PM PDT 24
Peak memory	203056 kb
Host	smart-85106603-ae48-4080-bc27-e8142d4c83c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057288049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .4057288049
Directory	/workspace/43.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/43.sram_ctrl_executable.3294211938
Short name	T885
Test name
Test status
Simulation time	6105697476 ps
CPU time	251.16 seconds
Started	Jun 23 06:28:20 PM PDT 24
Finished	Jun 23 06:32:31 PM PDT 24
Peak memory	375616 kb
Host	smart-519dcc06-4d6d-4390-bcf5-67d54718903e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294211938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.3294211938
Directory	/workspace/43.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/43.sram_ctrl_lc_escalation.3590246263
Short name	T748
Test name
Test status
Simulation time	81010128 ps
CPU time	1.31 seconds
Started	Jun 23 06:28:15 PM PDT 24
Finished	Jun 23 06:28:17 PM PDT 24
Peak memory	202880 kb
Host	smart-eb8cab31-d826-4b77-a158-9818b73911b7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590246263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.3590246263
Directory	/workspace/43.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/43.sram_ctrl_max_throughput.3741532538
Short name	T226
Test name
Test status
Simulation time	311751236 ps
CPU time	77.49 seconds
Started	Jun 23 06:28:16 PM PDT 24
Finished	Jun 23 06:29:33 PM PDT 24
Peak memory	325760 kb
Host	smart-9a877040-36f9-4122-8206-07d2d26cdb07
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741532538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.3741532538
Directory	/workspace/43.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2561366688
Short name	T764
Test name
Test status
Simulation time	1247902340 ps
CPU time	5.93 seconds
Started	Jun 23 06:28:22 PM PDT 24
Finished	Jun 23 06:28:28 PM PDT 24
Peak memory	211284 kb
Host	smart-b34b799e-73a9-46c4-bfc5-bdbbab0126c0
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561366688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.2561366688
Directory	/workspace/43.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_walk.456858582
Short name	T250
Test name
Test status
Simulation time	348370453 ps
CPU time	5.25 seconds
Started	Jun 23 06:28:21 PM PDT 24
Finished	Jun 23 06:28:26 PM PDT 24
Peak memory	211260 kb
Host	smart-ac85db2e-6d5c-430b-8f5f-a332f9a98f40
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456858582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _mem_walk.456858582
Directory	/workspace/43.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/43.sram_ctrl_multiple_keys.350759281
Short name	T441
Test name
Test status
Simulation time	10186006609 ps
CPU time	155.34 seconds
Started	Jun 23 06:28:15 PM PDT 24
Finished	Jun 23 06:30:51 PM PDT 24
Peak memory	303300 kb
Host	smart-4377b7a1-082b-451d-8073-473a9c9deda6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350759281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip le_keys.350759281
Directory	/workspace/43.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access.2577175856
Short name	T745
Test name
Test status
Simulation time	2184340826 ps
CPU time	37.39 seconds
Started	Jun 23 06:28:15 PM PDT 24
Finished	Jun 23 06:28:53 PM PDT 24
Peak memory	282824 kb
Host	smart-d034c37f-ecc9-45a1-b729-1415f9a78d01
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577175856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.2577175856
Directory	/workspace/43.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2387223920
Short name	T612
Test name
Test status
Simulation time	5080364879 ps
CPU time	363.66 seconds
Started	Jun 23 06:28:16 PM PDT 24
Finished	Jun 23 06:34:20 PM PDT 24
Peak memory	203200 kb
Host	smart-fba8c58b-2218-42e6-ae1c-c9f751ada9bf
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387223920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.2387223920
Directory	/workspace/43.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/43.sram_ctrl_ram_cfg.3850218060
Short name	T208
Test name
Test status
Simulation time	30688464 ps
CPU time	0.8 seconds
Started	Jun 23 06:28:21 PM PDT 24
Finished	Jun 23 06:28:23 PM PDT 24
Peak memory	203080 kb
Host	smart-05089521-5367-4544-8041-31dbb555737a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850218060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3850218060
Directory	/workspace/43.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/43.sram_ctrl_smoke.2254949563
Short name	T211
Test name
Test status
Simulation time	407170024 ps
CPU time	13.23 seconds
Started	Jun 23 06:28:17 PM PDT 24
Finished	Jun 23 06:28:30 PM PDT 24
Peak memory	203124 kb
Host	smart-a3d82d70-c34e-4ba8-9cda-832fef3c8fcc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254949563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2254949563
Directory	/workspace/43.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all.997470770
Short name	T5
Test name
Test status
Simulation time	37796261832 ps
CPU time	2774.5 seconds
Started	Jun 23 06:28:21 PM PDT 24
Finished	Jun 23 07:14:37 PM PDT 24
Peak memory	374960 kb
Host	smart-5da4ab02-e1ca-4313-ad78-83a40bb6f4bb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997470770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_stress_all.997470770
Directory	/workspace/43.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1541179595
Short name	T58
Test name
Test status
Simulation time	1599615692 ps
CPU time	101.55 seconds
Started	Jun 23 06:28:20 PM PDT 24
Finished	Jun 23 06:30:02 PM PDT 24
Peak memory	344436 kb
Host	smart-a547725f-da73-40dd-af14-97b1669d91b3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1541179595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1541179595
Directory	/workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2101611939
Short name	T101
Test name
Test status
Simulation time	5910093247 ps
CPU time	284.21 seconds
Started	Jun 23 06:28:15 PM PDT 24
Finished	Jun 23 06:33:00 PM PDT 24
Peak memory	203068 kb
Host	smart-ef74ef3f-a140-46f9-8a1e-6c762c112111
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101611939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.2101611939
Directory	/workspace/43.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1512163005
Short name	T273
Test name
Test status
Simulation time	1533585439 ps
CPU time	73.73 seconds
Started	Jun 23 06:28:15 PM PDT 24
Finished	Jun 23 06:29:29 PM PDT 24
Peak memory	337520 kb
Host	smart-b369a336-8a1d-4009-b216-593258801a52
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512163005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1512163005
Directory	/workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1044339278
Short name	T887
Test name
Test status
Simulation time	5829297105 ps
CPU time	215.94 seconds
Started	Jun 23 06:28:29 PM PDT 24
Finished	Jun 23 06:32:06 PM PDT 24
Peak memory	347304 kb
Host	smart-ca116775-21de-4bd8-b1e5-a4c50fb387d9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044339278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.1044339278
Directory	/workspace/44.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/44.sram_ctrl_alert_test.1801567078
Short name	T788
Test name
Test status
Simulation time	38116623 ps
CPU time	0.67 seconds
Started	Jun 23 06:28:30 PM PDT 24
Finished	Jun 23 06:28:31 PM PDT 24
Peak memory	203168 kb
Host	smart-6f98df6e-d93c-46b8-af04-4df1715e2f58
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801567078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1801567078
Directory	/workspace/44.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.sram_ctrl_bijection.2498465729
Short name	T391
Test name
Test status
Simulation time	971034383 ps
CPU time	31.92 seconds
Started	Jun 23 06:28:21 PM PDT 24
Finished	Jun 23 06:28:54 PM PDT 24
Peak memory	203068 kb
Host	smart-0a525c04-1f31-46d8-b1ee-e9ddf4f830a0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498465729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .2498465729
Directory	/workspace/44.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/44.sram_ctrl_executable.304918834
Short name	T370
Test name
Test status
Simulation time	1667994188 ps
CPU time	497.94 seconds
Started	Jun 23 06:28:24 PM PDT 24
Finished	Jun 23 06:36:43 PM PDT 24
Peak memory	375244 kb
Host	smart-2dcd54e6-d4de-446d-a0a2-641280a2fb4d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304918834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl e.304918834
Directory	/workspace/44.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/44.sram_ctrl_lc_escalation.572122308
Short name	T451
Test name
Test status
Simulation time	3573560364 ps
CPU time	11.05 seconds
Started	Jun 23 06:28:26 PM PDT 24
Finished	Jun 23 06:28:38 PM PDT 24
Peak memory	215440 kb
Host	smart-f1f90e3e-615f-4dc5-8ffa-69c1f7c4b305
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572122308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_esc alation.572122308
Directory	/workspace/44.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/44.sram_ctrl_max_throughput.1088763762
Short name	T728
Test name
Test status
Simulation time	183203386 ps
CPU time	138.5 seconds
Started	Jun 23 06:28:24 PM PDT 24
Finished	Jun 23 06:30:43 PM PDT 24
Peak memory	366332 kb
Host	smart-1d6ddb2c-d38c-4768-a869-469a7dd84403
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088763762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.1088763762
Directory	/workspace/44.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.4039302956
Short name	T501
Test name
Test status
Simulation time	386318725 ps
CPU time	3.4 seconds
Started	Jun 23 06:28:26 PM PDT 24
Finished	Jun 23 06:28:30 PM PDT 24
Peak memory	211224 kb
Host	smart-2d8ae8b8-cf05-49ee-95dc-88119fa723c8
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039302956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.4039302956
Directory	/workspace/44.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_walk.652047381
Short name	T780
Test name
Test status
Simulation time	4152250974 ps
CPU time	6.23 seconds
Started	Jun 23 06:28:24 PM PDT 24
Finished	Jun 23 06:28:31 PM PDT 24
Peak memory	211396 kb
Host	smart-d9e4dacc-7612-41a2-b757-488dc812ec69
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652047381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl _mem_walk.652047381
Directory	/workspace/44.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/44.sram_ctrl_multiple_keys.1712290837
Short name	T649
Test name
Test status
Simulation time	6774925686 ps
CPU time	725.3 seconds
Started	Jun 23 06:28:19 PM PDT 24
Finished	Jun 23 06:40:25 PM PDT 24
Peak memory	374824 kb
Host	smart-b7c8dcd7-f731-4574-942c-85b724c64408
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712290837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.1712290837
Directory	/workspace/44.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access.4281208329
Short name	T564
Test name
Test status
Simulation time	1698112048 ps
CPU time	8.76 seconds
Started	Jun 23 06:28:20 PM PDT 24
Finished	Jun 23 06:28:29 PM PDT 24
Peak memory	203088 kb
Host	smart-fb3c7915-f2df-4c82-a797-74057965b20e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281208329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.4281208329
Directory	/workspace/44.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1594975639
Short name	T771
Test name
Test status
Simulation time	17211908162 ps
CPU time	379.94 seconds
Started	Jun 23 06:28:25 PM PDT 24
Finished	Jun 23 06:34:45 PM PDT 24
Peak memory	203108 kb
Host	smart-8535232a-3f49-4d39-8db4-dfdae3074e62
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594975639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.1594975639
Directory	/workspace/44.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/44.sram_ctrl_ram_cfg.2933460329
Short name	T843
Test name
Test status
Simulation time	84379640 ps
CPU time	0.78 seconds
Started	Jun 23 06:28:25 PM PDT 24
Finished	Jun 23 06:28:26 PM PDT 24
Peak memory	203096 kb
Host	smart-c7847134-9b02-4e6b-9e0c-55f937c2dbed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933460329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2933460329
Directory	/workspace/44.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/44.sram_ctrl_regwen.139056487
Short name	T461
Test name
Test status
Simulation time	1264303794 ps
CPU time	163.16 seconds
Started	Jun 23 06:28:26 PM PDT 24
Finished	Jun 23 06:31:09 PM PDT 24
Peak memory	367644 kb
Host	smart-69959882-89fa-4f28-973b-108f7e3ed6f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139056487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.139056487
Directory	/workspace/44.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/44.sram_ctrl_smoke.169649522
Short name	T206
Test name
Test status
Simulation time	714547222 ps
CPU time	15.26 seconds
Started	Jun 23 06:28:22 PM PDT 24
Finished	Jun 23 06:28:37 PM PDT 24
Peak memory	203092 kb
Host	smart-ac23ebd7-2918-4719-adba-ad8e8fd7de04
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169649522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.169649522
Directory	/workspace/44.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all.3756298004
Short name	T668
Test name
Test status
Simulation time	62858799200 ps
CPU time	4753.56 seconds
Started	Jun 23 06:28:29 PM PDT 24
Finished	Jun 23 07:47:44 PM PDT 24
Peak memory	377472 kb
Host	smart-9aa76971-2a14-46b6-b0a9-4d2593f25682
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756298004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.3756298004
Directory	/workspace/44.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3916232573
Short name	T199
Test name
Test status
Simulation time	1436546298 ps
CPU time	129.06 seconds
Started	Jun 23 06:28:20 PM PDT 24
Finished	Jun 23 06:30:30 PM PDT 24
Peak memory	203320 kb
Host	smart-b16619b7-22f4-44b8-9145-6899e2b7e732
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916232573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.3916232573
Directory	/workspace/44.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1929760153
Short name	T631
Test name
Test status
Simulation time	158508938 ps
CPU time	142.22 seconds
Started	Jun 23 06:28:27 PM PDT 24
Finished	Jun 23 06:30:49 PM PDT 24
Peak memory	369668 kb
Host	smart-4b240916-2e13-451f-933b-7c35a0720118
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929760153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1929760153
Directory	/workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3692399605
Short name	T847
Test name
Test status
Simulation time	1261906808 ps
CPU time	570.9 seconds
Started	Jun 23 06:28:30 PM PDT 24
Finished	Jun 23 06:38:01 PM PDT 24
Peak memory	369732 kb
Host	smart-e5b9ffaf-4f92-417f-830e-bb9d50c0d22e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692399605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.3692399605
Directory	/workspace/45.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/45.sram_ctrl_alert_test.4274488240
Short name	T37
Test name
Test status
Simulation time	11382403 ps
CPU time	0.64 seconds
Started	Jun 23 06:28:34 PM PDT 24
Finished	Jun 23 06:28:35 PM PDT 24
Peak memory	202868 kb
Host	smart-41864368-ab90-47c2-94ac-45590745ac3b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274488240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.4274488240
Directory	/workspace/45.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.sram_ctrl_bijection.2782976145
Short name	T258
Test name
Test status
Simulation time	2851045316 ps
CPU time	30.01 seconds
Started	Jun 23 06:28:31 PM PDT 24
Finished	Jun 23 06:29:01 PM PDT 24
Peak memory	203168 kb
Host	smart-d4be2f7d-9943-4482-bdcf-63b8253adf81
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782976145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .2782976145
Directory	/workspace/45.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/45.sram_ctrl_executable.2503043712
Short name	T35
Test name
Test status
Simulation time	12099691564 ps
CPU time	491.57 seconds
Started	Jun 23 06:28:29 PM PDT 24
Finished	Jun 23 06:36:41 PM PDT 24
Peak memory	369332 kb
Host	smart-c5d25468-12eb-47a4-a512-18a4e45ad739
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503043712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.2503043712
Directory	/workspace/45.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/45.sram_ctrl_lc_escalation.647172849
Short name	T573
Test name
Test status
Simulation time	987435690 ps
CPU time	6.71 seconds
Started	Jun 23 06:28:30 PM PDT 24
Finished	Jun 23 06:28:37 PM PDT 24
Peak memory	202980 kb
Host	smart-4bd6dd2d-8ecf-4656-9684-b6729e9e9239
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647172849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esc alation.647172849
Directory	/workspace/45.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/45.sram_ctrl_max_throughput.665635961
Short name	T406
Test name
Test status
Simulation time	108449508 ps
CPU time	39.49 seconds
Started	Jun 23 06:28:31 PM PDT 24
Finished	Jun 23 06:29:11 PM PDT 24
Peak memory	293700 kb
Host	smart-c5082b1e-19e5-45a1-8ea2-800fa933fc97
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665635961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.sram_ctrl_max_throughput.665635961
Directory	/workspace/45.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3602791267
Short name	T60
Test name
Test status
Simulation time	239013663 ps
CPU time	3.05 seconds
Started	Jun 23 06:28:34 PM PDT 24
Finished	Jun 23 06:28:38 PM PDT 24
Peak memory	211272 kb
Host	smart-ba87c443-73b0-4bf7-9e20-e376dfef31dc
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602791267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.3602791267
Directory	/workspace/45.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_walk.2802563316
Short name	T926
Test name
Test status
Simulation time	140457898 ps
CPU time	8.79 seconds
Started	Jun 23 06:28:33 PM PDT 24
Finished	Jun 23 06:28:42 PM PDT 24
Peak memory	211312 kb
Host	smart-340ca708-58c2-4041-9b04-eb57bab1bb12
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802563316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.2802563316
Directory	/workspace/45.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/45.sram_ctrl_multiple_keys.917435005
Short name	T888
Test name
Test status
Simulation time	18634333394 ps
CPU time	1332.7 seconds
Started	Jun 23 06:28:30 PM PDT 24
Finished	Jun 23 06:50:43 PM PDT 24
Peak memory	376020 kb
Host	smart-da2b2e73-fba9-42ee-a19f-1de8938e5aa8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917435005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip le_keys.917435005
Directory	/workspace/45.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access.1326418051
Short name	T795
Test name
Test status
Simulation time	257836420 ps
CPU time	14.01 seconds
Started	Jun 23 06:28:30 PM PDT 24
Finished	Jun 23 06:28:44 PM PDT 24
Peak memory	203076 kb
Host	smart-8bfb350f-4ff3-40be-842b-addc7a6ecf01
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326418051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.1326418051
Directory	/workspace/45.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1702176271
Short name	T468
Test name
Test status
Simulation time	38952692545 ps
CPU time	273.26 seconds
Started	Jun 23 06:28:32 PM PDT 24
Finished	Jun 23 06:33:05 PM PDT 24
Peak memory	203132 kb
Host	smart-4f3f3cfc-5be6-4f57-a96a-49ec293cbd6e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702176271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.1702176271
Directory	/workspace/45.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/45.sram_ctrl_ram_cfg.135241330
Short name	T531
Test name
Test status
Simulation time	35270964 ps
CPU time	0.79 seconds
Started	Jun 23 06:28:29 PM PDT 24
Finished	Jun 23 06:28:30 PM PDT 24
Peak memory	203132 kb
Host	smart-cc74a0e4-59fd-4e57-ba2b-a86081b7ee74
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135241330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.135241330
Directory	/workspace/45.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/45.sram_ctrl_regwen.4257421665
Short name	T467
Test name
Test status
Simulation time	41544303265 ps
CPU time	626.78 seconds
Started	Jun 23 06:28:30 PM PDT 24
Finished	Jun 23 06:38:57 PM PDT 24
Peak memory	357576 kb
Host	smart-bde36b1b-fe23-49d5-ad83-3f7f3d819976
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257421665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.4257421665
Directory	/workspace/45.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/45.sram_ctrl_smoke.4090352017
Short name	T149
Test name
Test status
Simulation time	182261356 ps
CPU time	10.12 seconds
Started	Jun 23 06:28:30 PM PDT 24
Finished	Jun 23 06:28:41 PM PDT 24
Peak memory	203104 kb
Host	smart-aa6207f1-2673-428e-95dc-273e84a2cbda
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090352017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.4090352017
Directory	/workspace/45.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all.57285945
Short name	T733
Test name
Test status
Simulation time	14099457506 ps
CPU time	1200.29 seconds
Started	Jun 23 06:28:34 PM PDT 24
Finished	Jun 23 06:48:35 PM PDT 24
Peak memory	372904 kb
Host	smart-453621e2-ddfe-4d97-b640-1c5a11ae3a79
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57285945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.sram_ctrl_stress_all.57285945
Directory	/workspace/45.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.194168116
Short name	T282
Test name
Test status
Simulation time	1194422143 ps
CPU time	10.28 seconds
Started	Jun 23 06:28:34 PM PDT 24
Finished	Jun 23 06:28:44 PM PDT 24
Peak memory	211416 kb
Host	smart-bf4fd07f-d3fe-47bb-9fa9-f92444f6a4ab
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=194168116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.194168116
Directory	/workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3152164297
Short name	T464
Test name
Test status
Simulation time	10104309090 ps
CPU time	240.74 seconds
Started	Jun 23 06:28:32 PM PDT 24
Finished	Jun 23 06:32:33 PM PDT 24
Peak memory	203196 kb
Host	smart-58fc7df6-a0ee-4e69-b73f-866c3b2fb32e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152164297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.3152164297
Directory	/workspace/45.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.822471202
Short name	T711
Test name
Test status
Simulation time	130350626 ps
CPU time	75.38 seconds
Started	Jun 23 06:28:29 PM PDT 24
Finished	Jun 23 06:29:44 PM PDT 24
Peak memory	341032 kb
Host	smart-29cb3563-b5e8-48a1-95c2-e94af9180467
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822471202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_throughput_w_partial_write.822471202
Directory	/workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.4028464131
Short name	T350
Test name
Test status
Simulation time	1974711141 ps
CPU time	749.46 seconds
Started	Jun 23 06:28:39 PM PDT 24
Finished	Jun 23 06:41:09 PM PDT 24
Peak memory	369764 kb
Host	smart-791ad1e8-9b62-4f83-a6ba-df3b5839810a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028464131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.4028464131
Directory	/workspace/46.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/46.sram_ctrl_alert_test.2717951677
Short name	T567
Test name
Test status
Simulation time	30331158 ps
CPU time	0.63 seconds
Started	Jun 23 06:28:44 PM PDT 24
Finished	Jun 23 06:28:45 PM PDT 24
Peak memory	202960 kb
Host	smart-8d8127bb-85a4-40b6-9610-11d8da97f12e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717951677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2717951677
Directory	/workspace/46.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.sram_ctrl_bijection.3500669806
Short name	T36
Test name
Test status
Simulation time	14460984138 ps
CPU time	69.12 seconds
Started	Jun 23 06:28:34 PM PDT 24
Finished	Jun 23 06:29:44 PM PDT 24
Peak memory	203204 kb
Host	smart-4cad79fd-56be-47e3-b901-cfa191746b15
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500669806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .3500669806
Directory	/workspace/46.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/46.sram_ctrl_executable.1533592838
Short name	T882
Test name
Test status
Simulation time	14121699034 ps
CPU time	713.93 seconds
Started	Jun 23 06:28:38 PM PDT 24
Finished	Jun 23 06:40:32 PM PDT 24
Peak memory	374860 kb
Host	smart-b208ae44-bed4-4be1-8f97-8d93e3c3f685
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533592838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.1533592838
Directory	/workspace/46.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/46.sram_ctrl_lc_escalation.3525856009
Short name	T603
Test name
Test status
Simulation time	769957543 ps
CPU time	2.8 seconds
Started	Jun 23 06:28:39 PM PDT 24
Finished	Jun 23 06:28:42 PM PDT 24
Peak memory	214432 kb
Host	smart-e76806af-2fe2-4286-b488-9ab2139c0e05
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525856009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.3525856009
Directory	/workspace/46.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/46.sram_ctrl_max_throughput.4162420273
Short name	T622
Test name
Test status
Simulation time	348583092 ps
CPU time	153.71 seconds
Started	Jun 23 06:28:41 PM PDT 24
Finished	Jun 23 06:31:15 PM PDT 24
Peak memory	371564 kb
Host	smart-f3894d31-aac2-4479-9bcf-82323fb5aa34
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162420273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.4162420273
Directory	/workspace/46.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1108996438
Short name	T239
Test name
Test status
Simulation time	744072056 ps
CPU time	6.15 seconds
Started	Jun 23 06:28:43 PM PDT 24
Finished	Jun 23 06:28:50 PM PDT 24
Peak memory	211312 kb
Host	smart-c6a134ca-a4b2-4157-be35-286b90fc5a74
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108996438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.1108996438
Directory	/workspace/46.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_walk.2651011405
Short name	T260
Test name
Test status
Simulation time	908887832 ps
CPU time	5.96 seconds
Started	Jun 23 06:28:43 PM PDT 24
Finished	Jun 23 06:28:50 PM PDT 24
Peak memory	211488 kb
Host	smart-7b40aca1-1f8b-473f-aceb-140762af4b08
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651011405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.2651011405
Directory	/workspace/46.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/46.sram_ctrl_multiple_keys.1351192146
Short name	T172
Test name
Test status
Simulation time	11483847045 ps
CPU time	819.6 seconds
Started	Jun 23 06:28:33 PM PDT 24
Finished	Jun 23 06:42:13 PM PDT 24
Peak memory	358584 kb
Host	smart-85d7a192-4160-4ffa-90d1-2b69d756ebff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351192146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.1351192146
Directory	/workspace/46.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access.2740004204
Short name	T22
Test name
Test status
Simulation time	1274864104 ps
CPU time	116.25 seconds
Started	Jun 23 06:28:35 PM PDT 24
Finished	Jun 23 06:30:32 PM PDT 24
Peak memory	362088 kb
Host	smart-61ca3de7-8889-4dbc-b127-727ba9526b69
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740004204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.2740004204
Directory	/workspace/46.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2230055932
Short name	T415
Test name
Test status
Simulation time	71554118472 ps
CPU time	412.91 seconds
Started	Jun 23 06:28:34 PM PDT 24
Finished	Jun 23 06:35:27 PM PDT 24
Peak memory	203092 kb
Host	smart-d7faec76-5e5b-40c9-a8ba-dcbd6d07a5c6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230055932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.2230055932
Directory	/workspace/46.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/46.sram_ctrl_ram_cfg.976942424
Short name	T25
Test name
Test status
Simulation time	70445519 ps
CPU time	0.75 seconds
Started	Jun 23 06:28:39 PM PDT 24
Finished	Jun 23 06:28:40 PM PDT 24
Peak memory	203004 kb
Host	smart-a9cdf409-42c5-496e-a7c2-1b0bfd76c872
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976942424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.976942424
Directory	/workspace/46.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/46.sram_ctrl_regwen.1579604172
Short name	T644
Test name
Test status
Simulation time	18067231203 ps
CPU time	915.3 seconds
Started	Jun 23 06:28:39 PM PDT 24
Finished	Jun 23 06:43:55 PM PDT 24
Peak memory	371424 kb
Host	smart-a543e8b8-604b-452f-98b2-58b897d3e57f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579604172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1579604172
Directory	/workspace/46.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/46.sram_ctrl_smoke.1925306550
Short name	T201
Test name
Test status
Simulation time	617215809 ps
CPU time	9.54 seconds
Started	Jun 23 06:28:33 PM PDT 24
Finished	Jun 23 06:28:42 PM PDT 24
Peak memory	203092 kb
Host	smart-0c3abdea-8e06-4974-a1f0-474f59324613
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925306550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1925306550
Directory	/workspace/46.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4136505827
Short name	T403
Test name
Test status
Simulation time	2010390531 ps
CPU time	286.74 seconds
Started	Jun 23 06:28:45 PM PDT 24
Finished	Jun 23 06:33:32 PM PDT 24
Peak memory	350372 kb
Host	smart-298c3426-3095-4ed6-b819-8ec57ac91787
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4136505827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.4136505827
Directory	/workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.631472015
Short name	T336
Test name
Test status
Simulation time	804771746 ps
CPU time	69.58 seconds
Started	Jun 23 06:28:33 PM PDT 24
Finished	Jun 23 06:29:43 PM PDT 24
Peak memory	203084 kb
Host	smart-44d73c2e-f1f2-4588-82c6-938f8e6477c6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631472015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sram_ctrl_stress_pipeline.631472015
Directory	/workspace/46.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2195857052
Short name	T388
Test name
Test status
Simulation time	301084208 ps
CPU time	17.05 seconds
Started	Jun 23 06:28:39 PM PDT 24
Finished	Jun 23 06:28:56 PM PDT 24
Peak memory	261832 kb
Host	smart-4cee716b-4bce-49c3-b19c-6ec9f04621b7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195857052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2195857052
Directory	/workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1808276646
Short name	T480
Test name
Test status
Simulation time	4433753839 ps
CPU time	723.23 seconds
Started	Jun 23 06:28:44 PM PDT 24
Finished	Jun 23 06:40:47 PM PDT 24
Peak memory	373672 kb
Host	smart-2c72e019-992f-4c9f-93ee-f5a6bbb67d52
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808276646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.1808276646
Directory	/workspace/47.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/47.sram_ctrl_alert_test.3253417406
Short name	T807
Test name
Test status
Simulation time	20133410 ps
CPU time	0.66 seconds
Started	Jun 23 06:28:50 PM PDT 24
Finished	Jun 23 06:28:52 PM PDT 24
Peak memory	202832 kb
Host	smart-3ce88a84-6f59-4ba0-b682-976b2543dce7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253417406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3253417406
Directory	/workspace/47.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.sram_ctrl_bijection.2114439372
Short name	T737
Test name
Test status
Simulation time	5488641159 ps
CPU time	50 seconds
Started	Jun 23 06:28:46 PM PDT 24
Finished	Jun 23 06:29:36 PM PDT 24
Peak memory	203096 kb
Host	smart-60e42928-9785-4272-8d17-ecdb218b4bf0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114439372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .2114439372
Directory	/workspace/47.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/47.sram_ctrl_executable.588934496
Short name	T752
Test name
Test status
Simulation time	4885114594 ps
CPU time	1038.46 seconds
Started	Jun 23 06:28:45 PM PDT 24
Finished	Jun 23 06:46:04 PM PDT 24
Peak memory	372856 kb
Host	smart-839b499d-a09f-4f30-8237-20a792091cdd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588934496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executabl e.588934496
Directory	/workspace/47.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/47.sram_ctrl_lc_escalation.3448059781
Short name	T823
Test name
Test status
Simulation time	1455076600 ps
CPU time	6.54 seconds
Started	Jun 23 06:28:44 PM PDT 24
Finished	Jun 23 06:28:50 PM PDT 24
Peak memory	203048 kb
Host	smart-3cecdd9f-553a-4b44-a487-df8cca7518b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448059781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.3448059781
Directory	/workspace/47.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/47.sram_ctrl_max_throughput.1123036561
Short name	T245
Test name
Test status
Simulation time	138045182 ps
CPU time	130.14 seconds
Started	Jun 23 06:28:46 PM PDT 24
Finished	Jun 23 06:30:56 PM PDT 24
Peak memory	369676 kb
Host	smart-995d9fb0-1562-455c-bdca-540848146adc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123036561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.1123036561
Directory	/workspace/47.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2229924227
Short name	T203
Test name
Test status
Simulation time	174617040 ps
CPU time	5.89 seconds
Started	Jun 23 06:28:52 PM PDT 24
Finished	Jun 23 06:28:58 PM PDT 24
Peak memory	211308 kb
Host	smart-c6ab11b7-cc56-4c29-89a6-212c66e41379
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229924227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.2229924227
Directory	/workspace/47.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_walk.1991039421
Short name	T593
Test name
Test status
Simulation time	543676393 ps
CPU time	8.58 seconds
Started	Jun 23 06:28:50 PM PDT 24
Finished	Jun 23 06:29:00 PM PDT 24
Peak memory	211192 kb
Host	smart-29c4baa0-ab6c-4654-9552-433aa3a73179
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991039421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.1991039421
Directory	/workspace/47.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/47.sram_ctrl_multiple_keys.2157345897
Short name	T717
Test name
Test status
Simulation time	17623212742 ps
CPU time	997.49 seconds
Started	Jun 23 06:28:46 PM PDT 24
Finished	Jun 23 06:45:23 PM PDT 24
Peak memory	368096 kb
Host	smart-c9431340-5a05-4cd5-95d8-764c66f3e319
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157345897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.2157345897
Directory	/workspace/47.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access.1514169601
Short name	T38
Test name
Test status
Simulation time	986087701 ps
CPU time	19.11 seconds
Started	Jun 23 06:28:44 PM PDT 24
Finished	Jun 23 06:29:04 PM PDT 24
Peak memory	203076 kb
Host	smart-6f2b18ce-7e8f-45de-a67e-edc7e86018d1
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514169601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.1514169601
Directory	/workspace/47.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.721927048
Short name	T249
Test name
Test status
Simulation time	45367917955 ps
CPU time	579.21 seconds
Started	Jun 23 06:28:43 PM PDT 24
Finished	Jun 23 06:38:23 PM PDT 24
Peak memory	203152 kb
Host	smart-fee4ba43-8e80-4da4-947b-d0a09d02b9e5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721927048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 47.sram_ctrl_partial_access_b2b.721927048
Directory	/workspace/47.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/47.sram_ctrl_ram_cfg.3715542166
Short name	T256
Test name
Test status
Simulation time	53726683 ps
CPU time	0.76 seconds
Started	Jun 23 06:28:50 PM PDT 24
Finished	Jun 23 06:28:51 PM PDT 24
Peak memory	203124 kb
Host	smart-60cfd74d-4bdc-490b-8946-d4c0750dcc40
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715542166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3715542166
Directory	/workspace/47.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/47.sram_ctrl_regwen.2646533071
Short name	T470
Test name
Test status
Simulation time	9851323632 ps
CPU time	760.53 seconds
Started	Jun 23 06:28:53 PM PDT 24
Finished	Jun 23 06:41:35 PM PDT 24
Peak memory	373920 kb
Host	smart-ce360663-9c51-42f3-95e3-f59bfa9b224d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646533071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2646533071
Directory	/workspace/47.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/47.sram_ctrl_smoke.2138432826
Short name	T853
Test name
Test status
Simulation time	230151057 ps
CPU time	1.53 seconds
Started	Jun 23 06:28:43 PM PDT 24
Finished	Jun 23 06:28:45 PM PDT 24
Peak memory	203088 kb
Host	smart-368bc5a2-e053-4ae2-aaf3-d56b0643e5eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138432826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2138432826
Directory	/workspace/47.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all.1036427012
Short name	T676
Test name
Test status
Simulation time	19200273723 ps
CPU time	3004.53 seconds
Started	Jun 23 06:28:48 PM PDT 24
Finished	Jun 23 07:18:53 PM PDT 24
Peak memory	372884 kb
Host	smart-0dac58df-0549-4b83-a132-53e4d1d35f1d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036427012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.1036427012
Directory	/workspace/47.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4271069486
Short name	T607
Test name
Test status
Simulation time	2007998935 ps
CPU time	93.68 seconds
Started	Jun 23 06:28:48 PM PDT 24
Finished	Jun 23 06:30:22 PM PDT 24
Peak memory	326240 kb
Host	smart-3dbf706b-238a-4171-9459-a6a9cb8ca266
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4271069486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.4271069486
Directory	/workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3650416780
Short name	T809
Test name
Test status
Simulation time	3580139085 ps
CPU time	323.93 seconds
Started	Jun 23 06:28:45 PM PDT 24
Finished	Jun 23 06:34:09 PM PDT 24
Peak memory	203116 kb
Host	smart-2ecbbf10-ceda-4358-af75-c863809714f6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650416780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.3650416780
Directory	/workspace/47.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.363056702
Short name	T551
Test name
Test status
Simulation time	730509713 ps
CPU time	53.1 seconds
Started	Jun 23 06:28:44 PM PDT 24
Finished	Jun 23 06:29:37 PM PDT 24
Peak memory	303228 kb
Host	smart-dc363004-811d-4f78-977a-88474d666927
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363056702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.363056702
Directory	/workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/48.sram_ctrl_access_during_key_req.206090807
Short name	T225
Test name
Test status
Simulation time	5171742294 ps
CPU time	363.48 seconds
Started	Jun 23 06:28:53 PM PDT 24
Finished	Jun 23 06:34:57 PM PDT 24
Peak memory	371820 kb
Host	smart-e2dc6816-357e-463d-b5e5-4a3b31f3043c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206090807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 48.sram_ctrl_access_during_key_req.206090807
Directory	/workspace/48.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/48.sram_ctrl_alert_test.1034990988
Short name	T182
Test name
Test status
Simulation time	17314875 ps
CPU time	0.68 seconds
Started	Jun 23 06:28:53 PM PDT 24
Finished	Jun 23 06:28:55 PM PDT 24
Peak memory	202932 kb
Host	smart-f8fc84b5-f1c0-434a-a8fe-364cc8f53f3d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034990988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1034990988
Directory	/workspace/48.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.sram_ctrl_bijection.3460187232
Short name	T661
Test name
Test status
Simulation time	5238753443 ps
CPU time	31.84 seconds
Started	Jun 23 06:28:47 PM PDT 24
Finished	Jun 23 06:29:19 PM PDT 24
Peak memory	203188 kb
Host	smart-372c6b58-c240-4521-a55f-e3d1fcb53fe8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460187232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .3460187232
Directory	/workspace/48.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/48.sram_ctrl_executable.3208976101
Short name	T667
Test name
Test status
Simulation time	47588548786 ps
CPU time	637.76 seconds
Started	Jun 23 06:28:54 PM PDT 24
Finished	Jun 23 06:39:32 PM PDT 24
Peak memory	372228 kb
Host	smart-58a322c2-269e-4751-8a4f-b2a3286793c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208976101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.3208976101
Directory	/workspace/48.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/48.sram_ctrl_lc_escalation.2839848199
Short name	T224
Test name
Test status
Simulation time	230046054 ps
CPU time	2.77 seconds
Started	Jun 23 06:28:53 PM PDT 24
Finished	Jun 23 06:28:56 PM PDT 24
Peak memory	214252 kb
Host	smart-49c9dafc-4f18-4fe6-be4f-98a0ad1e533e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839848199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.2839848199
Directory	/workspace/48.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/48.sram_ctrl_max_throughput.2924111105
Short name	T524
Test name
Test status
Simulation time	82620097 ps
CPU time	22.4 seconds
Started	Jun 23 06:28:54 PM PDT 24
Finished	Jun 23 06:29:17 PM PDT 24
Peak memory	273608 kb
Host	smart-66080c7c-0cc4-4814-b68b-a3b8fc958904
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924111105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.2924111105
Directory	/workspace/48.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3438528609
Short name	T722
Test name
Test status
Simulation time	193441208 ps
CPU time	3.1 seconds
Started	Jun 23 06:28:53 PM PDT 24
Finished	Jun 23 06:28:57 PM PDT 24
Peak memory	211256 kb
Host	smart-6383dca8-187c-4861-805c-ef5464c3d4a9
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438528609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.3438528609
Directory	/workspace/48.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_walk.3564671482
Short name	T890
Test name
Test status
Simulation time	151319480 ps
CPU time	4.47 seconds
Started	Jun 23 06:28:53 PM PDT 24
Finished	Jun 23 06:28:58 PM PDT 24
Peak memory	203072 kb
Host	smart-415205f5-f4a5-4f3c-8bdd-dc585df24e98
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564671482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.3564671482
Directory	/workspace/48.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/48.sram_ctrl_multiple_keys.615080213
Short name	T911
Test name
Test status
Simulation time	11292763840 ps
CPU time	48.59 seconds
Started	Jun 23 06:28:48 PM PDT 24
Finished	Jun 23 06:29:37 PM PDT 24
Peak memory	203112 kb
Host	smart-2792f21c-364d-4d41-bf62-ab37af29793a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615080213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip le_keys.615080213
Directory	/workspace/48.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access.527162409
Short name	T507
Test name
Test status
Simulation time	679759861 ps
CPU time	9.92 seconds
Started	Jun 23 06:28:48 PM PDT 24
Finished	Jun 23 06:28:59 PM PDT 24
Peak memory	203112 kb
Host	smart-7e44efd3-f9d0-42db-9b64-7952581c3037
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527162409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.s ram_ctrl_partial_access.527162409
Directory	/workspace/48.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2839879143
Short name	T301
Test name
Test status
Simulation time	11116491878 ps
CPU time	405.34 seconds
Started	Jun 23 06:28:53 PM PDT 24
Finished	Jun 23 06:35:39 PM PDT 24
Peak memory	203196 kb
Host	smart-280da795-8e9e-4252-8746-579d099f29f3
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839879143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.2839879143
Directory	/workspace/48.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/48.sram_ctrl_ram_cfg.2724860191
Short name	T683
Test name
Test status
Simulation time	27155638 ps
CPU time	0.74 seconds
Started	Jun 23 06:28:52 PM PDT 24
Finished	Jun 23 06:28:54 PM PDT 24
Peak memory	203124 kb
Host	smart-77b5e3b9-e64d-46f7-b8a1-61a486bdcf68
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724860191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2724860191
Directory	/workspace/48.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/48.sram_ctrl_regwen.307760069
Short name	T861
Test name
Test status
Simulation time	50186203682 ps
CPU time	501.42 seconds
Started	Jun 23 06:28:52 PM PDT 24
Finished	Jun 23 06:37:15 PM PDT 24
Peak memory	366504 kb
Host	smart-0a95a81d-3d81-4c76-8798-4427abee2a7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307760069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.307760069
Directory	/workspace/48.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/48.sram_ctrl_smoke.949373545
Short name	T10
Test name
Test status
Simulation time	589529962 ps
CPU time	88.65 seconds
Started	Jun 23 06:28:49 PM PDT 24
Finished	Jun 23 06:30:18 PM PDT 24
Peak memory	348900 kb
Host	smart-825fabdc-2f1d-4d3c-aeac-e48603de6489
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949373545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.949373545
Directory	/workspace/48.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all.2561840527
Short name	T932
Test name
Test status
Simulation time	217199000670 ps
CPU time	2240.14 seconds
Started	Jun 23 06:28:52 PM PDT 24
Finished	Jun 23 07:06:13 PM PDT 24
Peak memory	375008 kb
Host	smart-5a62f8de-e000-468e-b207-bd5c1510094d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561840527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.2561840527
Directory	/workspace/48.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4008598207
Short name	T619
Test name
Test status
Simulation time	2290699141 ps
CPU time	186.71 seconds
Started	Jun 23 06:28:52 PM PDT 24
Finished	Jun 23 06:31:59 PM PDT 24
Peak memory	350504 kb
Host	smart-c36e1bac-a891-49c7-b04e-8e8aab3cdcf2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4008598207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.4008598207
Directory	/workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1920705383
Short name	T881
Test name
Test status
Simulation time	9818524128 ps
CPU time	246.58 seconds
Started	Jun 23 06:28:47 PM PDT 24
Finished	Jun 23 06:32:54 PM PDT 24
Peak memory	203204 kb
Host	smart-3a158afa-76ec-4075-a32b-3c981203e9c9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920705383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1920705383
Directory	/workspace/48.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3773799015
Short name	T515
Test name
Test status
Simulation time	44442889 ps
CPU time	2.37 seconds
Started	Jun 23 06:28:52 PM PDT 24
Finished	Jun 23 06:28:55 PM PDT 24
Peak memory	217268 kb
Host	smart-86adb5b6-51b2-4ac9-b091-1210a51de5c3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773799015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3773799015
Directory	/workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/49.sram_ctrl_access_during_key_req.688692375
Short name	T327
Test name
Test status
Simulation time	1762078537 ps
CPU time	587.47 seconds
Started	Jun 23 06:29:04 PM PDT 24
Finished	Jun 23 06:38:52 PM PDT 24
Peak memory	373568 kb
Host	smart-1b5046f1-c8a8-476e-b5cf-7fd56729b5eb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688692375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 49.sram_ctrl_access_during_key_req.688692375
Directory	/workspace/49.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/49.sram_ctrl_alert_test.4009040648
Short name	T630
Test name
Test status
Simulation time	38117510 ps
CPU time	0.7 seconds
Started	Jun 23 06:29:06 PM PDT 24
Finished	Jun 23 06:29:07 PM PDT 24
Peak memory	202316 kb
Host	smart-d6c835f3-c36d-42b0-804c-8ec8818a426f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009040648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.4009040648
Directory	/workspace/49.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.sram_ctrl_bijection.1678309328
Short name	T688
Test name
Test status
Simulation time	3554448306 ps
CPU time	33.31 seconds
Started	Jun 23 06:28:57 PM PDT 24
Finished	Jun 23 06:29:31 PM PDT 24
Peak memory	203100 kb
Host	smart-73d31ffe-b765-4250-9311-7fa4774b920f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678309328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .1678309328
Directory	/workspace/49.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/49.sram_ctrl_executable.3971312557
Short name	T367
Test name
Test status
Simulation time	19208012808 ps
CPU time	850.07 seconds
Started	Jun 23 06:29:03 PM PDT 24
Finished	Jun 23 06:43:13 PM PDT 24
Peak memory	359576 kb
Host	smart-03114d98-9ca9-46a0-bf4a-2f529614d2c1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971312557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.3971312557
Directory	/workspace/49.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/49.sram_ctrl_lc_escalation.1351029873
Short name	T559
Test name
Test status
Simulation time	996482093 ps
CPU time	7.33 seconds
Started	Jun 23 06:29:04 PM PDT 24
Finished	Jun 23 06:29:11 PM PDT 24
Peak memory	203132 kb
Host	smart-bec7ea6d-cfde-4048-a543-3a63a849369d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351029873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.1351029873
Directory	/workspace/49.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/49.sram_ctrl_max_throughput.559665305
Short name	T541
Test name
Test status
Simulation time	167773689 ps
CPU time	26.48 seconds
Started	Jun 23 06:29:04 PM PDT 24
Finished	Jun 23 06:29:30 PM PDT 24
Peak memory	287936 kb
Host	smart-afa92fa5-7215-46ea-992e-54463def659d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559665305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.sram_ctrl_max_throughput.559665305
Directory	/workspace/49.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2703989880
Short name	T354
Test name
Test status
Simulation time	62977760 ps
CPU time	2.96 seconds
Started	Jun 23 06:29:04 PM PDT 24
Finished	Jun 23 06:29:07 PM PDT 24
Peak memory	211308 kb
Host	smart-71455dc9-994f-41e5-800e-1fa81a212cdc
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703989880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.2703989880
Directory	/workspace/49.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_walk.2361659628
Short name	T331
Test name
Test status
Simulation time	205635628 ps
CPU time	8.94 seconds
Started	Jun 23 06:29:05 PM PDT 24
Finished	Jun 23 06:29:14 PM PDT 24
Peak memory	211256 kb
Host	smart-f5ec5b83-4bfc-488b-9d51-b92310b7999e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361659628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.2361659628
Directory	/workspace/49.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/49.sram_ctrl_multiple_keys.3676332473
Short name	T812
Test name
Test status
Simulation time	1036436062 ps
CPU time	40.51 seconds
Started	Jun 23 06:28:57 PM PDT 24
Finished	Jun 23 06:29:38 PM PDT 24
Peak memory	275272 kb
Host	smart-b62846f8-838a-4d9e-b6ae-3076fdc138cc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676332473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.3676332473
Directory	/workspace/49.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access.1883333365
Short name	T779
Test name
Test status
Simulation time	902413140 ps
CPU time	12.45 seconds
Started	Jun 23 06:28:58 PM PDT 24
Finished	Jun 23 06:29:11 PM PDT 24
Peak memory	203140 kb
Host	smart-f263d97c-5edf-4fbf-a7bc-65db1cdee6d6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883333365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.1883333365
Directory	/workspace/49.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.551214394
Short name	T740
Test name
Test status
Simulation time	4335228154 ps
CPU time	305.17 seconds
Started	Jun 23 06:29:05 PM PDT 24
Finished	Jun 23 06:34:11 PM PDT 24
Peak memory	203200 kb
Host	smart-e822b023-c250-4b10-98d3-ddb12190cf30
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551214394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.sram_ctrl_partial_access_b2b.551214394
Directory	/workspace/49.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/49.sram_ctrl_ram_cfg.4255225205
Short name	T883
Test name
Test status
Simulation time	71618624 ps
CPU time	0.74 seconds
Started	Jun 23 06:29:01 PM PDT 24
Finished	Jun 23 06:29:02 PM PDT 24
Peak memory	203072 kb
Host	smart-77f644cf-c2bc-4b5f-a88b-c64d71ba8b32
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255225205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.4255225205
Directory	/workspace/49.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/49.sram_ctrl_regwen.746004254
Short name	T262
Test name
Test status
Simulation time	9521898707 ps
CPU time	973.95 seconds
Started	Jun 23 06:29:01 PM PDT 24
Finished	Jun 23 06:45:15 PM PDT 24
Peak memory	367372 kb
Host	smart-0d62a1d1-70ee-4be1-9507-8037dc4d407f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746004254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.746004254
Directory	/workspace/49.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/49.sram_ctrl_smoke.3184186296
Short name	T351
Test name
Test status
Simulation time	72770184 ps
CPU time	19.31 seconds
Started	Jun 23 06:28:57 PM PDT 24
Finished	Jun 23 06:29:17 PM PDT 24
Peak memory	266504 kb
Host	smart-980e80b6-5d43-4969-9fb5-6f575f544168
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184186296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3184186296
Directory	/workspace/49.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1286232507
Short name	T696
Test name
Test status
Simulation time	4018201250 ps
CPU time	187.48 seconds
Started	Jun 23 06:28:58 PM PDT 24
Finished	Jun 23 06:32:06 PM PDT 24
Peak memory	203176 kb
Host	smart-f7bd7b9e-ebc9-42e6-9bb3-9877da3b9440
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286232507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.1286232507
Directory	/workspace/49.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3113281358
Short name	T475
Test name
Test status
Simulation time	437021566 ps
CPU time	60.79 seconds
Started	Jun 23 06:29:06 PM PDT 24
Finished	Jun 23 06:30:07 PM PDT 24
Peak memory	313912 kb
Host	smart-a3c74456-2bf2-4546-a88b-07afd1bed55e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113281358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.3113281358
Directory	/workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2418860303
Short name	T272
Test name
Test status
Simulation time	1099794773 ps
CPU time	186.62 seconds
Started	Jun 23 06:24:49 PM PDT 24
Finished	Jun 23 06:27:56 PM PDT 24
Peak memory	327364 kb
Host	smart-2716da7e-6f4e-4bb4-b24c-a6b4f1e4bd9d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418860303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.2418860303
Directory	/workspace/5.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/5.sram_ctrl_alert_test.3714064313
Short name	T742
Test name
Test status
Simulation time	21339311 ps
CPU time	0.68 seconds
Started	Jun 23 06:24:51 PM PDT 24
Finished	Jun 23 06:24:53 PM PDT 24
Peak memory	202936 kb
Host	smart-24932278-b817-448b-9c94-0722f194d573
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714064313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3714064313
Directory	/workspace/5.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.sram_ctrl_bijection.2532851444
Short name	T757
Test name
Test status
Simulation time	4403784898 ps
CPU time	74.83 seconds
Started	Jun 23 06:24:46 PM PDT 24
Finished	Jun 23 06:26:02 PM PDT 24
Peak memory	203016 kb
Host	smart-ec7e2af9-c44a-477e-8892-55971da704c5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532851444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 2532851444
Directory	/workspace/5.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/5.sram_ctrl_executable.1234016585
Short name	T568
Test name
Test status
Simulation time	129789811997 ps
CPU time	1307.01 seconds
Started	Jun 23 06:24:49 PM PDT 24
Finished	Jun 23 06:46:37 PM PDT 24
Peak memory	373816 kb
Host	smart-7ac1d73d-23da-4cbe-907a-7617b38c5902
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234016585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.1234016585
Directory	/workspace/5.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/5.sram_ctrl_lc_escalation.1266466500
Short name	T842
Test name
Test status
Simulation time	1687948664 ps
CPU time	6.02 seconds
Started	Jun 23 06:24:48 PM PDT 24
Finished	Jun 23 06:24:54 PM PDT 24
Peak memory	214204 kb
Host	smart-3dabc65e-0a4e-4e61-80ba-25f991af46ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266466500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.1266466500
Directory	/workspace/5.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/5.sram_ctrl_max_throughput.3549220676
Short name	T706
Test name
Test status
Simulation time	117096620 ps
CPU time	57.75 seconds
Started	Jun 23 06:24:43 PM PDT 24
Finished	Jun 23 06:25:42 PM PDT 24
Peak memory	311172 kb
Host	smart-90df8776-970c-4ad1-b846-1afb6f328966
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549220676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.3549220676
Directory	/workspace/5.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.4169947146
Short name	T463
Test name
Test status
Simulation time	387119570 ps
CPU time	3.55 seconds
Started	Jun 23 06:24:50 PM PDT 24
Finished	Jun 23 06:24:55 PM PDT 24
Peak memory	211256 kb
Host	smart-5cb54573-e39c-47d3-8da3-be8b02df8a0a
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169947146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.4169947146
Directory	/workspace/5.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_walk.385803041
Short name	T496
Test name
Test status
Simulation time	724864237 ps
CPU time	5.87 seconds
Started	Jun 23 06:24:49 PM PDT 24
Finished	Jun 23 06:24:55 PM PDT 24
Peak memory	211256 kb
Host	smart-55bd9c28-a507-4ae9-83a7-7e88dce63d17
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385803041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ mem_walk.385803041
Directory	/workspace/5.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/5.sram_ctrl_multiple_keys.1895108206
Short name	T31
Test name
Test status
Simulation time	7822956770 ps
CPU time	218.91 seconds
Started	Jun 23 06:24:46 PM PDT 24
Finished	Jun 23 06:28:26 PM PDT 24
Peak memory	372956 kb
Host	smart-f58bdcf2-de50-4dab-aec3-c5851bf87433
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895108206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.1895108206
Directory	/workspace/5.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access.1712752143
Short name	T656
Test name
Test status
Simulation time	1298908719 ps
CPU time	159.82 seconds
Started	Jun 23 06:24:44 PM PDT 24
Finished	Jun 23 06:27:24 PM PDT 24
Peak memory	367272 kb
Host	smart-29968378-f301-4757-b02c-fbc7b585b310
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712752143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.1712752143
Directory	/workspace/5.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2446258900
Short name	T529
Test name
Test status
Simulation time	8332347851 ps
CPU time	319.68 seconds
Started	Jun 23 06:24:44 PM PDT 24
Finished	Jun 23 06:30:05 PM PDT 24
Peak memory	203168 kb
Host	smart-bd4dc4f5-6234-4a6f-8ab8-b0c2e896e943
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446258900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.2446258900
Directory	/workspace/5.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/5.sram_ctrl_ram_cfg.1368562934
Short name	T264
Test name
Test status
Simulation time	80229052 ps
CPU time	0.77 seconds
Started	Jun 23 06:24:50 PM PDT 24
Finished	Jun 23 06:24:52 PM PDT 24
Peak memory	202880 kb
Host	smart-0267460d-c49b-4b4d-b6b5-ef4c41175c17
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368562934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1368562934
Directory	/workspace/5.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/5.sram_ctrl_regwen.3204337460
Short name	T522
Test name
Test status
Simulation time	6771149504 ps
CPU time	649.95 seconds
Started	Jun 23 06:24:50 PM PDT 24
Finished	Jun 23 06:35:42 PM PDT 24
Peak memory	372908 kb
Host	smart-a949dc39-4801-403a-8c3b-8972a98ad691
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204337460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3204337460
Directory	/workspace/5.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/5.sram_ctrl_smoke.3638741407
Short name	T643
Test name
Test status
Simulation time	2163342447 ps
CPU time	70.39 seconds
Started	Jun 23 06:24:47 PM PDT 24
Finished	Jun 23 06:25:58 PM PDT 24
Peak memory	343904 kb
Host	smart-f276218d-28e6-403a-bab9-bd938dcf27f8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638741407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3638741407
Directory	/workspace/5.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all.2858784074
Short name	T908
Test name
Test status
Simulation time	93015627560 ps
CPU time	4235.81 seconds
Started	Jun 23 06:24:48 PM PDT 24
Finished	Jun 23 07:35:25 PM PDT 24
Peak memory	384220 kb
Host	smart-a93771a9-00ed-44b1-bae7-95d189ddd410
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858784074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.2858784074
Directory	/workspace/5.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1034819404
Short name	T23
Test name
Test status
Simulation time	1167123663 ps
CPU time	60.75 seconds
Started	Jun 23 06:24:49 PM PDT 24
Finished	Jun 23 06:25:50 PM PDT 24
Peak memory	309136 kb
Host	smart-d4973247-3c01-44e7-8743-91dc0b64342d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1034819404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1034819404
Directory	/workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.468513346
Short name	T693
Test name
Test status
Simulation time	2520443434 ps
CPU time	216.72 seconds
Started	Jun 23 06:24:46 PM PDT 24
Finished	Jun 23 06:28:23 PM PDT 24
Peak memory	203160 kb
Host	smart-d56c67c0-7ec0-4424-a972-92bf958d1cd7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468513346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. sram_ctrl_stress_pipeline.468513346
Directory	/workspace/5.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2264480957
Short name	T825
Test name
Test status
Simulation time	542222948 ps
CPU time	89.6 seconds
Started	Jun 23 06:24:43 PM PDT 24
Finished	Jun 23 06:26:13 PM PDT 24
Peak memory	338736 kb
Host	smart-6cd1d99c-7a72-4260-986a-8c66480e098f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264480957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2264480957
Directory	/workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2323240086
Short name	T459
Test name
Test status
Simulation time	1845528642 ps
CPU time	471.86 seconds
Started	Jun 23 06:24:56 PM PDT 24
Finished	Jun 23 06:32:48 PM PDT 24
Peak memory	372340 kb
Host	smart-620b22ed-83b2-46f2-8c67-7fe8a3598589
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323240086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.2323240086
Directory	/workspace/6.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/6.sram_ctrl_alert_test.1442893783
Short name	T215
Test name
Test status
Simulation time	42817914 ps
CPU time	0.65 seconds
Started	Jun 23 06:24:55 PM PDT 24
Finished	Jun 23 06:24:56 PM PDT 24
Peak memory	202936 kb
Host	smart-5515764f-f1f3-4d5f-86bf-ad64eb022212
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442893783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1442893783
Directory	/workspace/6.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.sram_ctrl_bijection.277951786
Short name	T520
Test name
Test status
Simulation time	1079480749 ps
CPU time	72.17 seconds
Started	Jun 23 06:24:51 PM PDT 24
Finished	Jun 23 06:26:04 PM PDT 24
Peak memory	203080 kb
Host	smart-19053261-78d4-4d56-8e4a-c3c8fab3c1f3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277951786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.277951786
Directory	/workspace/6.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/6.sram_ctrl_executable.4270678340
Short name	T460
Test name
Test status
Simulation time	43327601844 ps
CPU time	839.09 seconds
Started	Jun 23 06:24:56 PM PDT 24
Finished	Jun 23 06:38:55 PM PDT 24
Peak memory	368124 kb
Host	smart-49d582c0-6142-407b-a30c-1357c51ab191
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270678340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.4270678340
Directory	/workspace/6.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/6.sram_ctrl_lc_escalation.3379751364
Short name	T307
Test name
Test status
Simulation time	2231001901 ps
CPU time	6.49 seconds
Started	Jun 23 06:24:57 PM PDT 24
Finished	Jun 23 06:25:04 PM PDT 24
Peak memory	203204 kb
Host	smart-dafff1d8-5791-4cdc-a18b-db791347abd0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379751364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.3379751364
Directory	/workspace/6.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/6.sram_ctrl_max_throughput.2706599701
Short name	T235
Test name
Test status
Simulation time	120718434 ps
CPU time	88.48 seconds
Started	Jun 23 06:24:48 PM PDT 24
Finished	Jun 23 06:26:17 PM PDT 24
Peak memory	341816 kb
Host	smart-67aa3483-8a30-4817-be4f-9acedcf4c870
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706599701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.2706599701
Directory	/workspace/6.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.446907679
Short name	T783
Test name
Test status
Simulation time	190826296 ps
CPU time	3.24 seconds
Started	Jun 23 06:24:53 PM PDT 24
Finished	Jun 23 06:24:57 PM PDT 24
Peak memory	211276 kb
Host	smart-e6768a23-4d21-400c-b3c4-270d5c8a6f9a
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446907679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_mem_partial_access.446907679
Directory	/workspace/6.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_walk.1104333591
Short name	T705
Test name
Test status
Simulation time	137339993 ps
CPU time	8.34 seconds
Started	Jun 23 06:24:56 PM PDT 24
Finished	Jun 23 06:25:05 PM PDT 24
Peak memory	211204 kb
Host	smart-271a14ab-803c-41e4-b49e-5ce8d1966210
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104333591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.1104333591
Directory	/workspace/6.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/6.sram_ctrl_multiple_keys.2544914087
Short name	T317
Test name
Test status
Simulation time	10285131837 ps
CPU time	989.37 seconds
Started	Jun 23 06:24:50 PM PDT 24
Finished	Jun 23 06:41:21 PM PDT 24
Peak memory	375760 kb
Host	smart-e3807843-907a-4b21-a9cc-a31089088083
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544914087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.2544914087
Directory	/workspace/6.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access.1606454358
Short name	T584
Test name
Test status
Simulation time	990432354 ps
CPU time	72.61 seconds
Started	Jun 23 06:24:50 PM PDT 24
Finished	Jun 23 06:26:04 PM PDT 24
Peak memory	319232 kb
Host	smart-fabaadb2-8ce4-4eba-98b2-cd5d34f3f88c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606454358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.1606454358
Directory	/workspace/6.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1546223280
Short name	T136
Test name
Test status
Simulation time	24866909272 ps
CPU time	285.74 seconds
Started	Jun 23 06:24:50 PM PDT 24
Finished	Jun 23 06:29:37 PM PDT 24
Peak memory	203096 kb
Host	smart-49d3558d-52f8-451b-a014-5b1697f683ac
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546223280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.1546223280
Directory	/workspace/6.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/6.sram_ctrl_ram_cfg.540535801
Short name	T909
Test name
Test status
Simulation time	93918591 ps
CPU time	0.74 seconds
Started	Jun 23 06:24:56 PM PDT 24
Finished	Jun 23 06:24:57 PM PDT 24
Peak memory	203128 kb
Host	smart-89c565d9-cc50-4b83-8458-1799bb6402a9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540535801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.540535801
Directory	/workspace/6.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/6.sram_ctrl_regwen.1701684011
Short name	T68
Test name
Test status
Simulation time	925351098 ps
CPU time	105.77 seconds
Started	Jun 23 06:24:56 PM PDT 24
Finished	Jun 23 06:26:42 PM PDT 24
Peak memory	344660 kb
Host	smart-7dd160cd-c82c-4d28-abfa-79270558f2f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701684011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1701684011
Directory	/workspace/6.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/6.sram_ctrl_smoke.330544856
Short name	T896
Test name
Test status
Simulation time	697528470 ps
CPU time	124.77 seconds
Started	Jun 23 06:24:49 PM PDT 24
Finished	Jun 23 06:26:54 PM PDT 24
Peak memory	359448 kb
Host	smart-a4f4c6e3-00f2-45f1-aa70-59dbda92c5b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330544856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.330544856
Directory	/workspace/6.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all.240855151
Short name	T653
Test name
Test status
Simulation time	445038653954 ps
CPU time	6093.15 seconds
Started	Jun 23 06:24:55 PM PDT 24
Finished	Jun 23 08:06:29 PM PDT 24
Peak memory	377928 kb
Host	smart-d29626b0-86fb-4e6c-b353-a8bcf0698424
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240855151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_stress_all.240855151
Directory	/workspace/6.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2902852828
Short name	T839
Test name
Test status
Simulation time	1766140880 ps
CPU time	171.52 seconds
Started	Jun 23 06:24:49 PM PDT 24
Finished	Jun 23 06:27:41 PM PDT 24
Peak memory	203276 kb
Host	smart-793e95de-d68e-4c4e-b458-aa5006979ef1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902852828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.2902852828
Directory	/workspace/6.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1687436183
Short name	T159
Test name
Test status
Simulation time	285392139 ps
CPU time	1.27 seconds
Started	Jun 23 06:24:56 PM PDT 24
Finished	Jun 23 06:24:58 PM PDT 24
Peak memory	211112 kb
Host	smart-67765db4-253d-4fbf-8f72-52dc80e41de8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687436183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.1687436183
Directory	/workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1178257084
Short name	T662
Test name
Test status
Simulation time	5740762912 ps
CPU time	975.43 seconds
Started	Jun 23 06:25:01 PM PDT 24
Finished	Jun 23 06:41:17 PM PDT 24
Peak memory	375608 kb
Host	smart-ea6f59f2-e96c-48b2-b884-ccbf35a669ab
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178257084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.1178257084
Directory	/workspace/7.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/7.sram_ctrl_alert_test.1366898595
Short name	T266
Test name
Test status
Simulation time	10584367 ps
CPU time	0.66 seconds
Started	Jun 23 06:25:03 PM PDT 24
Finished	Jun 23 06:25:04 PM PDT 24
Peak memory	202956 kb
Host	smart-49e8c58f-1bd1-4886-8007-0db17af46ac4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366898595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.1366898595
Directory	/workspace/7.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.sram_ctrl_bijection.2201358528
Short name	T165
Test name
Test status
Simulation time	1523436593 ps
CPU time	33.77 seconds
Started	Jun 23 06:24:55 PM PDT 24
Finished	Jun 23 06:25:29 PM PDT 24
Peak memory	203124 kb
Host	smart-f2b4f93c-77e2-4d2b-b644-39e9212e28bc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201358528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 2201358528
Directory	/workspace/7.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/7.sram_ctrl_executable.2049896406
Short name	T789
Test name
Test status
Simulation time	57611995935 ps
CPU time	1259.92 seconds
Started	Jun 23 06:25:01 PM PDT 24
Finished	Jun 23 06:46:02 PM PDT 24
Peak memory	371892 kb
Host	smart-6eeedafa-51a9-4563-9ef9-a0377283c730
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049896406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.2049896406
Directory	/workspace/7.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/7.sram_ctrl_lc_escalation.1072220399
Short name	T579
Test name
Test status
Simulation time	1470340864 ps
CPU time	8.02 seconds
Started	Jun 23 06:25:00 PM PDT 24
Finished	Jun 23 06:25:09 PM PDT 24
Peak memory	211208 kb
Host	smart-52c9fec3-1fd9-43cb-84f4-d8c86fb364ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072220399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.1072220399
Directory	/workspace/7.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/7.sram_ctrl_max_throughput.1338222566
Short name	T349
Test name
Test status
Simulation time	104735984 ps
CPU time	52.26 seconds
Started	Jun 23 06:25:00 PM PDT 24
Finished	Jun 23 06:25:52 PM PDT 24
Peak memory	312584 kb
Host	smart-f4697b1c-56cc-425d-90b7-608af2bfb496
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338222566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.1338222566
Directory	/workspace/7.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3359839261
Short name	T419
Test name
Test status
Simulation time	84103480 ps
CPU time	4.56 seconds
Started	Jun 23 06:24:59 PM PDT 24
Finished	Jun 23 06:25:04 PM PDT 24
Peak memory	211224 kb
Host	smart-f0bd395f-3a4f-4df9-b2de-b3a7387f6810
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359839261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.3359839261
Directory	/workspace/7.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_walk.2843489404
Short name	T482
Test name
Test status
Simulation time	263022439 ps
CPU time	10.4 seconds
Started	Jun 23 06:24:59 PM PDT 24
Finished	Jun 23 06:25:10 PM PDT 24
Peak memory	211284 kb
Host	smart-663b83fc-2c55-4bcb-9eb9-e6e9a114c0ed
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843489404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2843489404
Directory	/workspace/7.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/7.sram_ctrl_multiple_keys.238193148
Short name	T609
Test name
Test status
Simulation time	4451910757 ps
CPU time	571.98 seconds
Started	Jun 23 06:24:54 PM PDT 24
Finished	Jun 23 06:34:27 PM PDT 24
Peak memory	344256 kb
Host	smart-9e9126a9-8d36-411e-8bfd-af043d531a32
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238193148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multipl e_keys.238193148
Directory	/workspace/7.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access.76536944
Short name	T314
Test name
Test status
Simulation time	1716494466 ps
CPU time	45.66 seconds
Started	Jun 23 06:24:56 PM PDT 24
Finished	Jun 23 06:25:42 PM PDT 24
Peak memory	306000 kb
Host	smart-e92dcb45-d5ca-4307-ad5e-5178d15ace91
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76536944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sra m_ctrl_partial_access.76536944
Directory	/workspace/7.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.236038510
Short name	T328
Test name
Test status
Simulation time	5705638590 ps
CPU time	404.75 seconds
Started	Jun 23 06:24:57 PM PDT 24
Finished	Jun 23 06:31:43 PM PDT 24
Peak memory	203104 kb
Host	smart-62e55671-2ad5-4023-8710-c9831ccdaa32
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236038510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.sram_ctrl_partial_access_b2b.236038510
Directory	/workspace/7.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/7.sram_ctrl_ram_cfg.2381881027
Short name	T538
Test name
Test status
Simulation time	52303731 ps
CPU time	0.76 seconds
Started	Jun 23 06:25:00 PM PDT 24
Finished	Jun 23 06:25:01 PM PDT 24
Peak memory	203060 kb
Host	smart-79ca6bfb-4e40-4be6-82b7-048645f1ed9b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381881027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2381881027
Directory	/workspace/7.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/7.sram_ctrl_regwen.3221978763
Short name	T587
Test name
Test status
Simulation time	2166359714 ps
CPU time	1211.74 seconds
Started	Jun 23 06:24:58 PM PDT 24
Finished	Jun 23 06:45:11 PM PDT 24
Peak memory	374960 kb
Host	smart-ca91ebf2-1e2f-4470-9fcc-7fe351aa7c1e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221978763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3221978763
Directory	/workspace/7.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/7.sram_ctrl_smoke.838156295
Short name	T383
Test name
Test status
Simulation time	173940617 ps
CPU time	4.63 seconds
Started	Jun 23 06:24:55 PM PDT 24
Finished	Jun 23 06:25:00 PM PDT 24
Peak memory	203088 kb
Host	smart-4a2af00b-b926-4e63-b00f-fde2314341be
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838156295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.838156295
Directory	/workspace/7.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all.440642202
Short name	T131
Test name
Test status
Simulation time	79797347343 ps
CPU time	8159.17 seconds
Started	Jun 23 06:25:01 PM PDT 24
Finished	Jun 23 08:41:02 PM PDT 24
Peak memory	376048 kb
Host	smart-729d0f03-9ee0-4f8c-9e1a-afdf2da9d166
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440642202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_stress_all.440642202
Directory	/workspace/7.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2552318833
Short name	T316
Test name
Test status
Simulation time	743271597 ps
CPU time	165.72 seconds
Started	Jun 23 06:25:01 PM PDT 24
Finished	Jun 23 06:27:47 PM PDT 24
Peak memory	367104 kb
Host	smart-2c2e0265-17e6-4301-8127-253b3112dc78
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2552318833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2552318833
Directory	/workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.582805073
Short name	T284
Test name
Test status
Simulation time	22201548636 ps
CPU time	296.99 seconds
Started	Jun 23 06:24:52 PM PDT 24
Finished	Jun 23 06:29:49 PM PDT 24
Peak memory	203172 kb
Host	smart-6b0573db-ada8-4cf4-a09d-a5fbb1d8f393
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582805073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. sram_ctrl_stress_pipeline.582805073
Directory	/workspace/7.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2777154501
Short name	T739
Test name
Test status
Simulation time	160423547 ps
CPU time	2.94 seconds
Started	Jun 23 06:25:00 PM PDT 24
Finished	Jun 23 06:25:04 PM PDT 24
Peak memory	219412 kb
Host	smart-05d53a84-cc4f-47be-a9bb-4b3da6e2a1f6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777154501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2777154501
Directory	/workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2394746672
Short name	T379
Test name
Test status
Simulation time	938170767 ps
CPU time	223.61 seconds
Started	Jun 23 06:25:05 PM PDT 24
Finished	Jun 23 06:28:49 PM PDT 24
Peak memory	307840 kb
Host	smart-3d22e2c9-d9da-4f33-a134-efaf9032cb90
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394746672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.2394746672
Directory	/workspace/8.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/8.sram_ctrl_bijection.2350182523
Short name	T692
Test name
Test status
Simulation time	2111107066 ps
CPU time	44.39 seconds
Started	Jun 23 06:24:57 PM PDT 24
Finished	Jun 23 06:25:42 PM PDT 24
Peak memory	203120 kb
Host	smart-5ddffec6-4dd9-4d73-bf29-b68e553199a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350182523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 2350182523
Directory	/workspace/8.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/8.sram_ctrl_executable.3588767541
Short name	T629
Test name
Test status
Simulation time	13936261484 ps
CPU time	922.14 seconds
Started	Jun 23 06:25:03 PM PDT 24
Finished	Jun 23 06:40:26 PM PDT 24
Peak memory	374488 kb
Host	smart-3a7e3194-eec7-4ad3-aabe-a6f59aec257c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588767541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.3588767541
Directory	/workspace/8.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/8.sram_ctrl_lc_escalation.3325092997
Short name	T778
Test name
Test status
Simulation time	492344095 ps
CPU time	5.25 seconds
Started	Jun 23 06:25:03 PM PDT 24
Finished	Jun 23 06:25:09 PM PDT 24
Peak memory	211264 kb
Host	smart-7d1fa631-d981-4d4a-9b95-fa7c155c2a23
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325092997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.3325092997
Directory	/workspace/8.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/8.sram_ctrl_max_throughput.3420300732
Short name	T162
Test name
Test status
Simulation time	2057961420 ps
CPU time	113.78 seconds
Started	Jun 23 06:25:02 PM PDT 24
Finished	Jun 23 06:26:56 PM PDT 24
Peak memory	361296 kb
Host	smart-f3cf0b56-7808-44c2-b333-2514dbf4f4f2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420300732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.3420300732
Directory	/workspace/8.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3635406748
Short name	T810
Test name
Test status
Simulation time	1279423910 ps
CPU time	6.39 seconds
Started	Jun 23 06:25:03 PM PDT 24
Finished	Jun 23 06:25:10 PM PDT 24
Peak memory	211272 kb
Host	smart-125e9e11-1f18-4821-9ea7-85023f12029b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635406748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.3635406748
Directory	/workspace/8.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_walk.3419734132
Short name	T694
Test name
Test status
Simulation time	1404268675 ps
CPU time	11.32 seconds
Started	Jun 23 06:25:05 PM PDT 24
Finished	Jun 23 06:25:16 PM PDT 24
Peak memory	211236 kb
Host	smart-c98c15df-b345-4547-bcec-30b17a9d52d7
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419734132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.3419734132
Directory	/workspace/8.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/8.sram_ctrl_multiple_keys.4275735617
Short name	T448
Test name
Test status
Simulation time	22336347661 ps
CPU time	1511.31 seconds
Started	Jun 23 06:24:59 PM PDT 24
Finished	Jun 23 06:50:11 PM PDT 24
Peak memory	374180 kb
Host	smart-5eb275f8-b1f5-49fd-97fc-ab5b49bb1a6c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275735617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.4275735617
Directory	/workspace/8.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access.427605631
Short name	T12
Test name
Test status
Simulation time	526465348 ps
CPU time	34.06 seconds
Started	Jun 23 06:24:59 PM PDT 24
Finished	Jun 23 06:25:33 PM PDT 24
Peak memory	289172 kb
Host	smart-a7d3422d-0d24-4ba8-a7be-7ef2dc3bbe9d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427605631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr am_ctrl_partial_access.427605631
Directory	/workspace/8.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.151008845
Short name	T749
Test name
Test status
Simulation time	109767126873 ps
CPU time	468.36 seconds
Started	Jun 23 06:25:00 PM PDT 24
Finished	Jun 23 06:32:49 PM PDT 24
Peak memory	203180 kb
Host	smart-b59ef3fc-0bf7-4e06-9d70-eb9af32288a9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151008845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.sram_ctrl_partial_access_b2b.151008845
Directory	/workspace/8.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/8.sram_ctrl_ram_cfg.822293126
Short name	T871
Test name
Test status
Simulation time	134162046 ps
CPU time	0.76 seconds
Started	Jun 23 06:25:05 PM PDT 24
Finished	Jun 23 06:25:06 PM PDT 24
Peak memory	203120 kb
Host	smart-6a4cb1f1-790d-4639-9ed2-4fcf419a6828
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822293126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.822293126
Directory	/workspace/8.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/8.sram_ctrl_regwen.579810660
Short name	T394
Test name
Test status
Simulation time	7505813697 ps
CPU time	61.41 seconds
Started	Jun 23 06:25:03 PM PDT 24
Finished	Jun 23 06:26:05 PM PDT 24
Peak memory	261472 kb
Host	smart-4eec89e8-5d8e-4f89-b213-3e7bd59996ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579810660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.579810660
Directory	/workspace/8.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/8.sram_ctrl_smoke.3840067090
Short name	T155
Test name
Test status
Simulation time	470576572 ps
CPU time	13.15 seconds
Started	Jun 23 06:25:02 PM PDT 24
Finished	Jun 23 06:25:16 PM PDT 24
Peak memory	255636 kb
Host	smart-1b1eee34-d5ae-4a12-8785-253539f49ec7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840067090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3840067090
Directory	/workspace/8.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all.3753195643
Short name	T695
Test name
Test status
Simulation time	63848649798 ps
CPU time	6394.93 seconds
Started	Jun 23 06:25:03 PM PDT 24
Finished	Jun 23 08:11:39 PM PDT 24
Peak memory	377032 kb
Host	smart-3d222834-9be1-4eb8-94dd-834bd2b735e6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753195643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.3753195643
Directory	/workspace/8.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1250959867
Short name	T45
Test name
Test status
Simulation time	8230388031 ps
CPU time	60.68 seconds
Started	Jun 23 06:25:04 PM PDT 24
Finished	Jun 23 06:26:05 PM PDT 24
Peak memory	234656 kb
Host	smart-ada007e9-a2a4-4ce3-82c4-2f669a84d370
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1250959867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1250959867
Directory	/workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1520889342
Short name	T100
Test name
Test status
Simulation time	28234602739 ps
CPU time	252.7 seconds
Started	Jun 23 06:24:59 PM PDT 24
Finished	Jun 23 06:29:12 PM PDT 24
Peak memory	203176 kb
Host	smart-0a7c91be-314c-4a0c-9247-c57b570b64a8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520889342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.1520889342
Directory	/workspace/8.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1576624027
Short name	T837
Test name
Test status
Simulation time	440696121 ps
CPU time	54.02 seconds
Started	Jun 23 06:25:00 PM PDT 24
Finished	Jun 23 06:25:54 PM PDT 24
Peak memory	303272 kb
Host	smart-04b07f39-4988-4742-ad58-9cfd3254bfc7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576624027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1576624027
Directory	/workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3590183346
Short name	T408
Test name
Test status
Simulation time	11179619716 ps
CPU time	1447.89 seconds
Started	Jun 23 06:25:08 PM PDT 24
Finished	Jun 23 06:49:17 PM PDT 24
Peak memory	372944 kb
Host	smart-7baf180f-578a-4528-aafe-b731072de010
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590183346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.3590183346
Directory	/workspace/9.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/9.sram_ctrl_alert_test.1636893692
Short name	T241
Test name
Test status
Simulation time	22175946 ps
CPU time	0.65 seconds
Started	Jun 23 06:25:08 PM PDT 24
Finished	Jun 23 06:25:09 PM PDT 24
Peak memory	202880 kb
Host	smart-a296c98a-b258-47f6-8840-bdf2297afe3c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636893692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1636893692
Directory	/workspace/9.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.sram_ctrl_bijection.2548755389
Short name	T834
Test name
Test status
Simulation time	12130192220 ps
CPU time	69.83 seconds
Started	Jun 23 06:25:04 PM PDT 24
Finished	Jun 23 06:26:14 PM PDT 24
Peak memory	203176 kb
Host	smart-da0a9b15-597e-462b-ac3b-ca56789f0e08
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548755389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 2548755389
Directory	/workspace/9.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/9.sram_ctrl_executable.2322539874
Short name	T669
Test name
Test status
Simulation time	50167538075 ps
CPU time	1103.07 seconds
Started	Jun 23 06:25:07 PM PDT 24
Finished	Jun 23 06:43:31 PM PDT 24
Peak memory	358620 kb
Host	smart-963ffa66-349b-4f84-a2c4-27649e8ad1f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322539874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.2322539874
Directory	/workspace/9.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/9.sram_ctrl_lc_escalation.3013544989
Short name	T253
Test name
Test status
Simulation time	1111491799 ps
CPU time	10.49 seconds
Started	Jun 23 06:25:07 PM PDT 24
Finished	Jun 23 06:25:18 PM PDT 24
Peak memory	203052 kb
Host	smart-1b7bf565-9ca1-411a-b2b0-32aab27852e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013544989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.3013544989
Directory	/workspace/9.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/9.sram_ctrl_max_throughput.2552765369
Short name	T194
Test name
Test status
Simulation time	207658002 ps
CPU time	6 seconds
Started	Jun 23 06:25:08 PM PDT 24
Finished	Jun 23 06:25:14 PM PDT 24
Peak memory	235532 kb
Host	smart-8c443f7e-a2c6-405e-96e3-4bf5847fb405
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552765369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.2552765369
Directory	/workspace/9.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1101889438
Short name	T486
Test name
Test status
Simulation time	65176300 ps
CPU time	4.46 seconds
Started	Jun 23 06:25:10 PM PDT 24
Finished	Jun 23 06:25:15 PM PDT 24
Peak memory	211280 kb
Host	smart-fe5c4454-94e4-4e02-9e99-6d331ad7664c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101889438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.1101889438
Directory	/workspace/9.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_walk.3386703714
Short name	T44
Test name
Test status
Simulation time	443759603 ps
CPU time	10.45 seconds
Started	Jun 23 06:25:09 PM PDT 24
Finished	Jun 23 06:25:20 PM PDT 24
Peak memory	211260 kb
Host	smart-f7762190-b045-4977-ab5d-188efec0c7c3
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386703714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3386703714
Directory	/workspace/9.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/9.sram_ctrl_multiple_keys.3761114071
Short name	T163
Test name
Test status
Simulation time	23112463850 ps
CPU time	549.24 seconds
Started	Jun 23 06:25:03 PM PDT 24
Finished	Jun 23 06:34:13 PM PDT 24
Peak memory	375764 kb
Host	smart-c3f81662-ac40-4743-8e15-1ad7593bc1fd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761114071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.3761114071
Directory	/workspace/9.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access.1057359897
Short name	T572
Test name
Test status
Simulation time	711919411 ps
CPU time	16.52 seconds
Started	Jun 23 06:25:08 PM PDT 24
Finished	Jun 23 06:25:25 PM PDT 24
Peak memory	203092 kb
Host	smart-9c02912f-6166-409d-91ea-79aa36eab221
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057359897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.1057359897
Directory	/workspace/9.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3986947165
Short name	T907
Test name
Test status
Simulation time	10719896591 ps
CPU time	212.58 seconds
Started	Jun 23 06:25:06 PM PDT 24
Finished	Jun 23 06:28:39 PM PDT 24
Peak memory	203208 kb
Host	smart-c4041946-017c-4a20-bbaf-c4b89b0e4910
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986947165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.3986947165
Directory	/workspace/9.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/9.sram_ctrl_ram_cfg.2206339901
Short name	T804
Test name
Test status
Simulation time	49213785 ps
CPU time	0.79 seconds
Started	Jun 23 06:25:09 PM PDT 24
Finished	Jun 23 06:25:10 PM PDT 24
Peak memory	203132 kb
Host	smart-38ba5541-2a98-4786-94e4-062989b4cd88
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206339901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2206339901
Directory	/workspace/9.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/9.sram_ctrl_regwen.2906023956
Short name	T627
Test name
Test status
Simulation time	10887042304 ps
CPU time	435.37 seconds
Started	Jun 23 06:25:08 PM PDT 24
Finished	Jun 23 06:32:24 PM PDT 24
Peak memory	359380 kb
Host	smart-2113928f-338e-4d05-951b-7f840b5731a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906023956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2906023956
Directory	/workspace/9.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/9.sram_ctrl_smoke.3554616438
Short name	T925
Test name
Test status
Simulation time	862140597 ps
CPU time	13.38 seconds
Started	Jun 23 06:25:03 PM PDT 24
Finished	Jun 23 06:25:17 PM PDT 24
Peak memory	203012 kb
Host	smart-aa72bab3-710c-4c16-9ae1-8b06da813ce3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554616438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3554616438
Directory	/workspace/9.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1073531070
Short name	T70
Test name
Test status
Simulation time	613129266 ps
CPU time	40.58 seconds
Started	Jun 23 06:25:09 PM PDT 24
Finished	Jun 23 06:25:50 PM PDT 24
Peak memory	293068 kb
Host	smart-22788508-076e-49de-a031-1918abfb3752
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1073531070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1073531070
Directory	/workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1590845244
Short name	T365
Test name
Test status
Simulation time	14395309346 ps
CPU time	224.31 seconds
Started	Jun 23 06:25:09 PM PDT 24
Finished	Jun 23 06:28:53 PM PDT 24
Peak memory	203172 kb
Host	smart-85d80e42-1200-475c-be63-581b419d2cc3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590845244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.1590845244
Directory	/workspace/9.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2183439405
Short name	T651
Test name
Test status
Simulation time	166451567 ps
CPU time	1.6 seconds
Started	Jun 23 06:25:10 PM PDT 24
Finished	Jun 23 06:25:12 PM PDT 24
Peak memory	211272 kb
Host	smart-6785671f-4372-4256-8eda-9ac92be61420
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183439405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2183439405
Directory	/workspace/9.sram_ctrl_throughput_w_partial_write/latest

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