Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
13848494 |
1 |
|
|
T1 |
96 |
|
T2 |
109 |
|
T4 |
17074 |
full_word |
52778539 |
1 |
|
|
T1 |
983 |
|
T2 |
958 |
|
T3 |
3071 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
66626753 |
1 |
|
|
T1 |
1079 |
|
T2 |
1067 |
|
T3 |
3071 |
auto[TlIntgErrCmd] |
95 |
1 |
|
|
T49 |
2 |
|
T50 |
4 |
|
T51 |
10 |
auto[TlIntgErrData] |
83 |
1 |
|
|
T49 |
3 |
|
T50 |
3 |
|
T51 |
3 |
auto[TlIntgErrBoth] |
102 |
1 |
|
|
T49 |
5 |
|
T50 |
3 |
|
T51 |
7 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
30489726 |
1 |
|
|
T1 |
522 |
|
T2 |
543 |
|
T3 |
1024 |
auto[1] |
36137307 |
1 |
|
|
T1 |
557 |
|
T2 |
524 |
|
T3 |
2047 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
6633822 |
1 |
|
|
T1 |
42 |
|
T2 |
46 |
|
T4 |
8601 |
auto[TlIntgErrNone] |
partial |
auto[1] |
7214418 |
1 |
|
|
T1 |
54 |
|
T2 |
63 |
|
T4 |
8473 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
23855787 |
1 |
|
|
T1 |
480 |
|
T2 |
497 |
|
T3 |
1024 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
28922726 |
1 |
|
|
T1 |
503 |
|
T2 |
461 |
|
T3 |
2047 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
33 |
1 |
|
|
T50 |
2 |
|
T51 |
3 |
|
T138 |
4 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
54 |
1 |
|
|
T49 |
2 |
|
T50 |
2 |
|
T51 |
6 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
2 |
1 |
|
|
T139 |
1 |
|
T140 |
1 |
|
- |
- |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
6 |
1 |
|
|
T51 |
1 |
|
T139 |
1 |
|
T140 |
2 |
auto[TlIntgErrData] |
partial |
auto[0] |
35 |
1 |
|
|
T50 |
3 |
|
T51 |
1 |
|
T137 |
3 |
auto[TlIntgErrData] |
partial |
auto[1] |
40 |
1 |
|
|
T49 |
3 |
|
T51 |
2 |
|
T137 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
3 |
1 |
|
|
T135 |
1 |
|
T140 |
1 |
|
T141 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
5 |
1 |
|
|
T142 |
1 |
|
T143 |
1 |
|
T140 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
40 |
1 |
|
|
T49 |
2 |
|
T50 |
2 |
|
T137 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
52 |
1 |
|
|
T49 |
2 |
|
T50 |
1 |
|
T51 |
6 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
4 |
1 |
|
|
T51 |
1 |
|
T136 |
1 |
|
T142 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
6 |
1 |
|
|
T49 |
1 |
|
T137 |
1 |
|
T142 |
1 |