Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	594398	1			T4	13541		T31	1305		T23	152
auto[1]	10646123	1			T2	468		T4	3272		T5	43895
auto[2]	502176	1			T4	12160		T31	971		T23	132
auto[3]	10552942	1			T2	449		T4	1849		T5	44044

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14367392	1			T2	750		T4	24328		T5	73383
auto[1]	2126291	1			T2	84		T4	3328		T5	6865
auto[2]	2153939	1			T2	69		T4	2795		T5	7054
auto[3]	3648017	1			T2	14		T4	371		T5	637

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8163693

1

T2

917

T4

30797

T5

87841

auto[1]

14131946

1

T4

25

T5

98

T10

10

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	171840	1			T4	11188		T31	38		T23	124
auto[0]	auto[0]	auto[1]	18253	1			T4	1131		T31	189		T23	13
auto[0]	auto[0]	auto[2]	18242	1			T4	1104		T31	187		T23	15
auto[0]	auto[0]	auto[3]	8334	1			T4	106		T31	888		T60	174
auto[0]	auto[1]	auto[0]	3184886	1			T2	390		T4	1844		T5	36602
auto[0]	auto[1]	auto[1]	325704	1			T2	39		T4	1111		T5	3211
auto[0]	auto[1]	auto[2]	322927	1			T2	33		T4	198		T5	3742
auto[0]	auto[1]	auto[3]	62263	1			T2	6		T4	118		T5	295
auto[0]	auto[2]	auto[0]	144897	1			T4	10334		T31	45		T23	105
auto[0]	auto[2]	auto[1]	15127	1			T4	1000		T31	193		T23	13
auto[0]	auto[2]	auto[2]	19327	1			T4	751		T31	144		T23	12
auto[0]	auto[2]	auto[3]	6572	1			T4	65		T31	588		T23	2
auto[0]	auto[3]	auto[0]	3155617	1			T2	360		T4	942		T5	36700
auto[0]	auto[3]	auto[1]	319089	1			T2	45		T4	85		T5	3646
auto[0]	auto[3]	auto[2]	326716	1			T2	36		T4	738		T5	3304
auto[0]	auto[3]	auto[3]	63899	1			T2	8		T4	82		T5	341
auto[1]	auto[0]	auto[0]	12591	1			T4	9		T60	15		T98	393
auto[1]	auto[0]	auto[1]	56607	1			T4	1		T31	1		T60	2
auto[1]	auto[0]	auto[2]	56413	1			T4	2		T60	4		T98	1937
auto[1]	auto[0]	auto[3]	252118	1			T31	2		T98	8598		T71	2212
auto[1]	auto[1]	auto[0]	3847009	1			T4	1		T5	36		T10	5
auto[1]	auto[1]	auto[1]	691589	1			T5	6		T25	17		T31	1
auto[1]	auto[1]	auto[2]	678179	1			T5	3		T30	1		T25	16
auto[1]	auto[1]	auto[3]	1533566	1			T25	3		T31	2		T47	955
auto[1]	auto[2]	auto[0]	8905	1			T4	10		T60	17		T98	242
auto[1]	auto[2]	auto[1]	39199	1			T31	1		T98	1172		T101	4929
auto[1]	auto[2]	auto[2]	48575	1			T60	1		T98	2076		T71	445
auto[1]	auto[2]	auto[3]	219574	1			T98	9333		T71	2025		T101	20345
auto[1]	auto[3]	auto[0]	3841647	1			T5	45		T10	5		T30	4
auto[1]	auto[3]	auto[1]	660723	1			T5	2		T25	11		T24	1
auto[1]	auto[3]	auto[2]	683560	1			T4	2		T5	5		T30	1
auto[1]	auto[3]	auto[3]	1501691	1			T5	1		T25	2		T31	3