Module Definition
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Module : prim_ram_1p_scr
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.53 98.11 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_ram_1p_scr 99.53 98.11 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_ram_1p_scr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.53 98.11 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.85 99.26 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_addr_scr.u_prim_subst_perm 100.00 100.00
gen_diffuse_data[0].u_prim_subst_perm_dec 100.00 100.00
gen_diffuse_data[0].u_prim_subst_perm_enc 100.00 100.00
gen_par_scr[0].u_prim_prince 100.00 100.00
u_addr_collision_flop 100.00 100.00 100.00
u_addr_match_buf 100.00 100.00
u_intg_error 100.00 100.00
u_prim_ram_1p_adv 100.00 100.00 100.00 100.00
u_read_en_buf 100.00 100.00
u_rvalid_flop 100.00 100.00 100.00
u_write_en_d_buf 100.00 100.00
u_write_en_flop 100.00 100.00 100.00
u_write_pending_flop 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_ram_1p_scr
Line No.TotalCoveredPercent
TOTAL535298.11
CONT_ASSIGN13311100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN19011100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN23211100.00
CONT_ASSIGN24511100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN30611100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN36111100.00
CONT_ASSIGN37011100.00
ALWAYS37610990.00
CONT_ASSIGN40411100.00
CONT_ASSIGN44811100.00
CONT_ASSIGN44911100.00
ALWAYS4521818100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
133 1 1
135 1 1
136 1 1
145 1 1
154 1 1
163 1 1
171 1 1
182 1 1
186 1 1
190 1 1
194 1 1
198 1 1
206 1 1
211 1 1
232 1 1
245 1 1
274 1 1
280 1 1
306 1 1
336 1 1
361 1 1
370 1 1
376 1 1
377 1 1
379 1 1
380 1 1
383 1 1
384 1 1
385 1 1
386 1 1
388 0 1
394 1 1
MISSING_ELSE
404 1 1
448 1 1
449 1 1
452 1 1
453 1 1
454 1 1
455 1 1
456 1 1
457 1 1
458 1 1
459 1 1
461 1 1
463 1 1
464 1 1
MISSING_ELSE
466 1 1
467 1 1
468 1 1
469 1 1
470 1 1
MISSING_ELSE
472 1 1
473 1 1
MISSING_ELSE


Cond Coverage for Module : prim_ram_1p_scr
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       133
 EXPRESSION (req_i & key_valid_i)
             --1--   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T32
11CoveredT2,T3,T4

 LINE       163
 EXPRESSION ((addr_scr == waddr_scr_q) ? MuBi4True : MuBi4False)
             ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       163
 SUB-EXPRESSION (addr_scr == waddr_scr_q)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       361
 EXPRESSION (macro_write ? MuBi4False : (rw_collision ? MuBi4True : write_pending_q))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       361
 SUB-EXPRESSION (rw_collision ? MuBi4True : write_pending_q)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

Branch Coverage for Module : prim_ram_1p_scr
Line No.TotalCoveredPercent
Branches 15 15 100.00
TERNARY 163 2 2 100.00
TERNARY 361 3 3 100.00
IF 379 3 3 100.00
IF 452 7 7 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 163 ((addr_scr == waddr_scr_q)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 361 (macro_write) ? -2-: 361 (rw_collision) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 379 if (((!intg_error_r_q) && prim_mubi_pkg::mubi4_test_true_loose(rvalid_q))) -2-: 383 if (prim_mubi_pkg::mubi4_test_true_loose(addr_collision_q))

Branches:
-1--2-StatusTests
1 1 Covered T5,T10,T30
1 0 Covered T2,T3,T4
0 - Covered T1,T2,T3


LineNo. Expression -1-: 452 if ((!rst_ni)) -2-: 463 if (read_en_b) -3-: 466 if (write_en_b) -4-: 472 if (rw_collision)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T2,T3,T4
0 0 - - Covered T1,T2,T3
0 - 1 - Covered T2,T3,T4
0 - 0 - Covered T1,T2,T3
0 - - 1 Covered T2,T4,T5
0 - - 0 Covered T1,T2,T3


Assert Coverage for Module : prim_ram_1p_scr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DepthPow2Check_A 893 893 0 0
DiffWidthMinimum_A 893 893 0 0
DiffWidthWithParity_A 893 893 0 0


DepthPow2Check_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 893 893 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

DiffWidthMinimum_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 893 893 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

DiffWidthWithParity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 893 893 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%