Assert Coverage for Module :
sram_ctrl_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
293231075 |
166679 |
0 |
0 |
T12 |
1539 |
0 |
0 |
0 |
T18 |
64259 |
0 |
0 |
0 |
T23 |
82828 |
2116 |
0 |
0 |
T24 |
212693 |
10901 |
0 |
0 |
T26 |
0 |
4668 |
0 |
0 |
T35 |
0 |
4208 |
0 |
0 |
T39 |
0 |
3742 |
0 |
0 |
T44 |
0 |
5041 |
0 |
0 |
T46 |
0 |
2170 |
0 |
0 |
T47 |
306440 |
0 |
0 |
0 |
T48 |
13218 |
0 |
0 |
0 |
T52 |
39958 |
0 |
0 |
0 |
T53 |
327664 |
0 |
0 |
0 |
T56 |
0 |
1291 |
0 |
0 |
T57 |
0 |
799 |
0 |
0 |
T58 |
0 |
1157 |
0 |
0 |
T59 |
5155 |
0 |
0 |
0 |
T60 |
229131 |
0 |
0 |
0 |
ctrl_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
293231075 |
3372 |
0 |
0 |
T35 |
0 |
367 |
0 |
0 |
T39 |
0 |
311 |
0 |
0 |
T57 |
17683 |
77 |
0 |
0 |
T116 |
0 |
68 |
0 |
0 |
T117 |
0 |
94 |
0 |
0 |
T118 |
0 |
146 |
0 |
0 |
T119 |
0 |
181 |
0 |
0 |
T120 |
0 |
178 |
0 |
0 |
T121 |
0 |
66 |
0 |
0 |
T122 |
0 |
52 |
0 |
0 |
T123 |
29683 |
0 |
0 |
0 |
T124 |
178123 |
0 |
0 |
0 |
T125 |
59874 |
0 |
0 |
0 |
T126 |
949 |
0 |
0 |
0 |
T127 |
1894 |
0 |
0 |
0 |
T128 |
1227 |
0 |
0 |
0 |
T129 |
489547 |
0 |
0 |
0 |
T130 |
56122 |
0 |
0 |
0 |
T131 |
781819 |
0 |
0 |
0 |
exec_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
293231075 |
2658 |
0 |
0 |
T35 |
0 |
246 |
0 |
0 |
T39 |
0 |
240 |
0 |
0 |
T57 |
17683 |
95 |
0 |
0 |
T116 |
0 |
58 |
0 |
0 |
T117 |
0 |
49 |
0 |
0 |
T118 |
0 |
158 |
0 |
0 |
T119 |
0 |
159 |
0 |
0 |
T120 |
0 |
137 |
0 |
0 |
T121 |
0 |
39 |
0 |
0 |
T122 |
0 |
40 |
0 |
0 |
T123 |
29683 |
0 |
0 |
0 |
T124 |
178123 |
0 |
0 |
0 |
T125 |
59874 |
0 |
0 |
0 |
T126 |
949 |
0 |
0 |
0 |
T127 |
1894 |
0 |
0 |
0 |
T128 |
1227 |
0 |
0 |
0 |
T129 |
489547 |
0 |
0 |
0 |
T130 |
56122 |
0 |
0 |
0 |
T131 |
781819 |
0 |
0 |
0 |
exec_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
293231075 |
2979 |
0 |
0 |
T35 |
0 |
352 |
0 |
0 |
T39 |
0 |
263 |
0 |
0 |
T57 |
17683 |
77 |
0 |
0 |
T116 |
0 |
89 |
0 |
0 |
T117 |
0 |
89 |
0 |
0 |
T118 |
0 |
186 |
0 |
0 |
T119 |
0 |
147 |
0 |
0 |
T120 |
0 |
171 |
0 |
0 |
T121 |
0 |
75 |
0 |
0 |
T122 |
0 |
50 |
0 |
0 |
T123 |
29683 |
0 |
0 |
0 |
T124 |
178123 |
0 |
0 |
0 |
T125 |
59874 |
0 |
0 |
0 |
T126 |
949 |
0 |
0 |
0 |
T127 |
1894 |
0 |
0 |
0 |
T128 |
1227 |
0 |
0 |
0 |
T129 |
489547 |
0 |
0 |
0 |
T130 |
56122 |
0 |
0 |
0 |
T131 |
781819 |
0 |
0 |
0 |
readback_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
293231075 |
1976 |
0 |
0 |
T35 |
0 |
347 |
0 |
0 |
T39 |
0 |
226 |
0 |
0 |
T57 |
17683 |
70 |
0 |
0 |
T116 |
0 |
72 |
0 |
0 |
T117 |
0 |
51 |
0 |
0 |
T118 |
0 |
115 |
0 |
0 |
T119 |
0 |
126 |
0 |
0 |
T120 |
0 |
109 |
0 |
0 |
T121 |
0 |
64 |
0 |
0 |
T122 |
0 |
30 |
0 |
0 |
T123 |
29683 |
0 |
0 |
0 |
T124 |
178123 |
0 |
0 |
0 |
T125 |
59874 |
0 |
0 |
0 |
T126 |
949 |
0 |
0 |
0 |
T127 |
1894 |
0 |
0 |
0 |
T128 |
1227 |
0 |
0 |
0 |
T129 |
489547 |
0 |
0 |
0 |
T130 |
56122 |
0 |
0 |
0 |
T131 |
781819 |
0 |
0 |
0 |
readback_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
293231075 |
1763 |
0 |
0 |
T35 |
0 |
312 |
0 |
0 |
T39 |
0 |
198 |
0 |
0 |
T57 |
17683 |
60 |
0 |
0 |
T116 |
0 |
69 |
0 |
0 |
T117 |
0 |
75 |
0 |
0 |
T118 |
0 |
91 |
0 |
0 |
T119 |
0 |
99 |
0 |
0 |
T120 |
0 |
89 |
0 |
0 |
T121 |
0 |
33 |
0 |
0 |
T122 |
0 |
30 |
0 |
0 |
T123 |
29683 |
0 |
0 |
0 |
T124 |
178123 |
0 |
0 |
0 |
T125 |
59874 |
0 |
0 |
0 |
T126 |
949 |
0 |
0 |
0 |
T127 |
1894 |
0 |
0 |
0 |
T128 |
1227 |
0 |
0 |
0 |
T129 |
489547 |
0 |
0 |
0 |
T130 |
56122 |
0 |
0 |
0 |
T131 |
781819 |
0 |
0 |
0 |