Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : tlul_sram_byte
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.84 99.31 93.07 100.00 91.80 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_adapter_sram.u_sram_byte 97.40 99.31 95.88 100.00 91.80 100.00



Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.40 99.31 95.88 100.00 91.80 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.19 98.79 94.94 100.00 92.23 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.26 98.70 89.47 96.88 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_integ_handling.gen_readback_logic.u_rdback_check_flop 100.00 100.00 100.00
gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf 100.00 100.00
gen_integ_handling.gen_readback_logic.u_rdback_data_exp 100.00 100.00 100.00
gen_integ_handling.gen_readback_logic.u_rdback_data_exp_intg 100.00 100.00 100.00
gen_integ_handling.gen_readback_logic.u_rdback_en_flop 100.00 100.00 100.00
gen_integ_handling.u_sync_fifo 90.73 95.00 86.67 81.25 100.00
gen_integ_handling.u_sync_fifo_a_size 100.00 100.00 100.00 100.00 100.00
gen_integ_handling.u_tlul_data_integ_enc 100.00 100.00

Line Coverage for Module : tlul_sram_byte
Line No.TotalCoveredPercent
TOTAL14514499.31
ALWAYS10533100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15611100.00
ALWAYS239959498.95
CONT_ASSIGN50611100.00
CONT_ASSIGN51711100.00
ALWAYS54222100.00
ALWAYS55300
ALWAYS55322100.00
ALWAYS57222100.00
ALWAYS5792222100.00
CONT_ASSIGN63311100.00
ALWAYS65844100.00
CONT_ASSIGN67611100.00
CONT_ASSIGN69911100.00
CONT_ASSIGN71611100.00
CONT_ASSIGN71711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
106 1 1
108 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
144 1 1
145 1 1
156 1 1
239 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
253 1 1
255 1 1
257 1 1
262 1 1
263 1 1
266 1 1
267 0 1
MISSING_ELSE
MISSING_ELSE
271 1 1
272 1 1
273 1 1
274 1 1
MISSING_ELSE
276 1 1
280 1 1
281 1 1
MISSING_ELSE
284 1 1
287 1 1
MISSING_ELSE
295 1 1
296 1 1
297 1 1
298 1 1
299 1 1
300 1 1
==> MISSING_ELSE
MISSING_ELSE
306 1 1
307 1 1
309 1 1
310 1 1
311 1 1
312 1 1
313 1 1
==> MISSING_ELSE
320 1 1
322 unreachable
MISSING_ELSE
326 1 1
330 1 1
331 1 1
334 1 1
335 1 1
336 1 1
337 1 1
340 1 1
343 1 1
MISSING_ELSE
350 1 1
352 unreachable
MISSING_ELSE
355 1 1
357 1 1
359 1 1
365 1 1
367 unreachable
MISSING_ELSE
371 1 1
373 1 1
375 1 1
378 1 1
MISSING_ELSE
385 1 1
387 unreachable
MISSING_ELSE
392 1 1
395 1 1
398 1 1
400 1 1
403 1 1
409 1 1
==> MISSING_ELSE
417 1 1
419 unreachable
MISSING_ELSE
422 1 1
424 1 1
426 1 1
430 1 1
432 unreachable
MISSING_ELSE
435 1 1
438 1 1
440 1 1
443 1 1
MISSING_ELSE
448 1 1
450 unreachable
MISSING_ELSE
455 1 1
459 1 1
460 1 1
462 1 1
463 1 1
465 1 1
466 1 1
467 1 1
470 1 1
MISSING_ELSE
476 1 1
478 unreachable
MISSING_ELSE
481 1 1
483 1 1
486 1 1
488 1 1
489 1 1
490 1 1
MISSING_ELSE
506 1 1
517 1 1
542 1 1
543 1 1
MISSING_ELSE
553 1 1
554 1 1
572 1 1
573 1 1
579 1 1
581 1 1
590 1 1
591 1 1
593 1 1
596 1 1
598 1 1
602 1 1
603 1 1
605 1 1
606 1 1
607 1 1
608 1 1
610 1 1
612 1 1
614 1 1
617 1 1
618 1 1
620 1 1
621 1 1
MISSING_ELSE
623 1 1
626 1 1
MISSING_ELSE
633 1 1
658 1 1
661 1 1
665 1 1
670 1 1
676 1 1
699 1 1
716 1 1
717 1 1


Cond Coverage for Module : tlul_sram_byte
TotalCoveredPercent
Conditions1019493.07
Logical1019493.07
Non-Logical00
Event00

 LINE       138
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       139
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       140
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T11,T31
11CoveredT2,T3,T4

 LINE       141
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       142
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       144
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT2,T4,T5
110CoveredT5,T10,T25
111CoveredT2,T4,T5

 LINE       145
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT2,T4,T5
111CoveredT2,T4,T5

 LINE       156
 EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       266
 EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
             ------------------1------------------    ------2-----
-1--2-StatusTests
01CoveredT3,T11,T23
10Not Covered
11Not Covered

 LINE       281
 EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
             ------------1------------
-1-StatusTests
0CoveredT3,T11,T24
1CoveredT3,T11,T23

 LINE       297
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------
-1-StatusTests
0CoveredT4,T31,T23
1CoveredT2,T4,T5

 LINE       330
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------
-1-StatusTests
0CoveredT23,T35,T36
1CoveredT3,T11,T23

 LINE       395
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------
-1-StatusTests
0Not Covered
1CoveredT11,T24,T37

 LINE       459
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------
-1-StatusTests
0CoveredT35,T36,T38
1CoveredT3,T11,T24

 LINE       517
 EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
             ---------------1---------------   ---------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T5
10CoveredT3,T11,T23

 LINE       542
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T4,T5

 LINE       554
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT2,T3,T4

 LINE       581
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
             ------1-----   -------------2------------   ---------------3--------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT3,T11,T23
010CoveredT2,T4,T5
100CoveredT1,T2,T3

 LINE       590
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT11,T24,T37
010CoveredT3,T11,T23
100CoveredT2,T4,T5

 LINE       593
 EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
             -------------1-------------
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       596
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       596
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------
-1--2-StatusTests
00CoveredT3,T11,T23
01CoveredT11,T24,T37
10CoveredT2,T4,T5

 LINE       598
 EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
             -------------------------------------1------------------------------------
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       598
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------
-1--2-StatusTests
00CoveredT3,T11,T23
01CoveredT11,T24,T37
10CoveredT2,T4,T5

 LINE       603
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       603
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------
-1--2-StatusTests
00CoveredT3,T11,T23
01CoveredT11,T24,T37
10CoveredT2,T4,T5

 LINE       607
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
             -------------1-------------
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       608
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
             -------------1-------------
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       614
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------
-1--2-StatusTests
00CoveredT5,T10,T25
01CoveredT2,T4,T5
10CoveredT2,T4,T5

 LINE       620
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T4,T5
11CoveredT2,T4,T5

 LINE       633
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       661
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------
-1--2--3--4-StatusTests
0111CoveredT2,T4,T7
1011CoveredT11,T24,T37
1101Not Covered
1110Not Covered
1111CoveredT1,T2,T3

 LINE       665
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
             --------1--------   ---------------2---------------   -----------------3-----------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T4,T5
110CoveredT3,T11,T23
111CoveredT2,T3,T4

 LINE       699
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT11,T24,T37
010CoveredT3,T11,T23
100CoveredT2,T4,T5

FSM Coverage for Module : tlul_sram_byte
Summary for FSM :: gen_integ_handling.state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 17 17 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q
statesLine No.CoveredTests
StByteWrReadBack 403 Covered T11,T24,T37
StByteWrReadBackDWait 409 Covered T11,T26,T39
StByteWrReadBackInit 310 Covered T11,T24,T37
StPassThru 310 Covered T1,T2,T3
StRdReadBack 281 Covered T3,T11,T24
StRdReadBackDWait 470 Covered T3,T11,T40
StWaitRd 274 Covered T2,T4,T5
StWrReadBack 340 Covered T3,T11,T23
StWrReadBackDWait 343 Covered T3,T11,T23
StWrReadBackInit 281 Covered T3,T11,T23
StWriteCmd 300 Covered T2,T4,T5


transitionsLine No.CoveredTests
StByteWrReadBack->StPassThru 426 Covered T11,T24,T37
StByteWrReadBackDWait->StByteWrReadBack 443 Covered T11,T26,T39
StByteWrReadBackInit->StByteWrReadBack 403 Covered T11,T24,T37
StByteWrReadBackInit->StByteWrReadBackDWait 409 Covered T11,T26,T39
StPassThru->StRdReadBack 281 Covered T3,T11,T24
StPassThru->StWaitRd 274 Covered T2,T4,T5
StPassThru->StWrReadBackInit 281 Covered T3,T11,T23
StRdReadBack->StPassThru 463 Covered T3,T11,T24
StRdReadBack->StRdReadBackDWait 470 Covered T3,T11,T40
StRdReadBackDWait->StPassThru 486 Covered T3,T11,T40
StWaitRd->StWriteCmd 300 Covered T2,T4,T5
StWrReadBack->StPassThru 359 Covered T3,T11,T23
StWrReadBackDWait->StWrReadBack 378 Covered T3,T11,T23
StWrReadBackInit->StWrReadBack 340 Covered T3,T11,T23
StWrReadBackInit->StWrReadBackDWait 343 Covered T3,T11,T23
StWriteCmd->StByteWrReadBackInit 310 Covered T11,T24,T37
StWriteCmd->StPassThru 310 Covered T2,T4,T5



Branch Coverage for Module : tlul_sram_byte
Line No.TotalCoveredPercent
Branches 61 56 91.80
IF 105 2 2 100.00
CASE 255 39 34 87.18
IF 542 2 2 100.00
TERNARY 554 2 2 100.00
IF 590 16 16 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 105 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 255 case (gen_integ_handling.state_q) -2-: 257 if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q))) -3-: 266 if (((!gen_integ_handling.rdback_chk_ok) && (!error_i))) -4-: 271 if (gen_integ_handling.byte_wr_txn) -5-: 273 if (gen_integ_handling.byte_req_ack) -6-: 276 if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i))) -7-: 281 (gen_integ_handling.wr_txn) ? -8-: 284 if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q))) -9-: 297 if ((gen_integ_handling.pending_txn_cnt == 2'(1))) -10-: 299 if (gen_integ_handling.sram_d_ack) -11-: 309 if (gen_integ_handling.sram_a_ack) -12-: 320 if ((EnableReadback == 1'b0)) -13-: 330 if ((gen_integ_handling.pending_txn_cnt == 2'(1))) -14-: 337 if (gen_integ_handling.d_ack) -15-: 350 if ((EnableReadback == 1'b0)) -16-: 365 if ((EnableReadback == 1'b0)) -17-: 375 if (gen_integ_handling.d_ack) -18-: 385 if ((EnableReadback == 1'b0)) -19-: 395 if ((gen_integ_handling.pending_txn_cnt == 2'(1))) -20-: 400 if (gen_integ_handling.d_ack) -21-: 417 if ((EnableReadback == 1'b0)) -22-: 430 if ((EnableReadback == 1'b0)) -23-: 440 if (gen_integ_handling.d_ack) -24-: 448 if ((EnableReadback == 1'b0)) -25-: 459 if ((gen_integ_handling.pending_txn_cnt == 2'(1))) -26-: 462 if (gen_integ_handling.d_ack) -27-: 476 if ((EnableReadback == 1'b0)) -28-: 483 if (gen_integ_handling.d_ack)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28-StatusTests
StPassThru 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
StPassThru 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T3,T11,T23
StPassThru 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StPassThru - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T5
StPassThru - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T5,T10
StPassThru - - 0 - 1 1 - - - - - - - - - - - - - - - - - - - - - Covered T3,T11,T23
StPassThru - - 0 - 1 0 - - - - - - - - - - - - - - - - - - - - - Covered T3,T11,T24
StPassThru - - 0 - 0 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StPassThru - - - - - - 1 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StPassThru - - - - - - 0 - - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
StWaitRd - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - Covered T2,T4,T5
StWaitRd - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - Not Covered
StWaitRd - - - - - - - 0 - - - - - - - - - - - - - - - - - - - Covered T4,T31,T23
StWriteCmd - - - - - - - - - 1 - - - - - - - - - - - - - - - - - Covered T2,T4,T5
StWriteCmd - - - - - - - - - 0 - - - - - - - - - - - - - - - - - Not Covered
StWrReadBackInit - - - - - - - - - - 1 - - - - - - - - - - - - - - - - Unreachable
StWrReadBackInit - - - - - - - - - - 0 - - - - - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackInit - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackInit - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackInit - - - - - - - - - - - 0 - - - - - - - - - - - - - - - Covered T23,T35,T36
StWrReadBack - - - - - - - - - - - - - 1 - - - - - - - - - - - - - Unreachable
StWrReadBack - - - - - - - - - - - - - 0 - - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackDWait - - - - - - - - - - - - - - 1 - - - - - - - - - - - - Unreachable
StWrReadBackDWait - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackDWait - - - - - - - - - - - - - - - 1 - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackDWait - - - - - - - - - - - - - - - 0 - - - - - - - - - - - Covered T3,T11,T23
StByteWrReadBackInit - - - - - - - - - - - - - - - - 1 - - - - - - - - - - Unreachable
StByteWrReadBackInit - - - - - - - - - - - - - - - - 0 - - - - - - - - - - Covered T11,T24,T37
StByteWrReadBackInit - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - Covered T11,T24,T37
StByteWrReadBackInit - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - Covered T11,T37,T26
StByteWrReadBackInit - - - - - - - - - - - - - - - - - 0 - - - - - - - - - Not Covered
StByteWrReadBack - - - - - - - - - - - - - - - - - - - 1 - - - - - - - Unreachable
StByteWrReadBack - - - - - - - - - - - - - - - - - - - 0 - - - - - - - Covered T11,T24,T37
StByteWrReadBackDWait - - - - - - - - - - - - - - - - - - - - 1 - - - - - - Unreachable
StByteWrReadBackDWait - - - - - - - - - - - - - - - - - - - - 0 - - - - - - Covered T11,T26,T39
StByteWrReadBackDWait - - - - - - - - - - - - - - - - - - - - - 1 - - - - - Covered T11,T26,T39
StByteWrReadBackDWait - - - - - - - - - - - - - - - - - - - - - 0 - - - - - Covered T11,T26,T39
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - 1 - - - - Unreachable
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - 0 - - - - Covered T3,T11,T24
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - Covered T3,T11,T24
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - Covered T3,T11,T41
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Covered T35,T36,T38
StRdReadBackDWait - - - - - - - - - - - - - - - - - - - - - - - - - 1 - Unreachable
StRdReadBackDWait - - - - - - - - - - - - - - - - - - - - - - - - - 0 - Covered T3,T11,T40
StRdReadBackDWait - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T3,T11,T40
StRdReadBackDWait - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T3,T11,T40
default - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 542 if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:
-1-StatusTests
1 Covered T2,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 554 (gen_integ_handling.held_data.a_mask[i]) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T4,T5


LineNo. Expression -1-: 590 if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback)) -2-: 593 (gen_integ_handling.wr_phase) ? -3-: 596 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? -4-: 598 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? -5-: 603 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? -6-: 607 (gen_integ_handling.wr_phase) ? -7-: 608 (gen_integ_handling.wr_phase) ? -8-: 610 if (gen_integ_handling.rd_phase) -9-: 614 if (((!error_i) || gen_integ_handling.stall_host)) -10-: 623 if (gen_integ_handling.wait_phase)

Branches:
-1--2--3--4--5--6--7--8--9--10-StatusTests
1 1 - - - - - - - - Covered T2,T4,T5
1 0 - - - - - - - - Covered T3,T11,T23
1 - 1 - - - - - - - Covered T2,T4,T5
1 - 0 - - - - - - - Covered T3,T11,T23
1 - - 1 - - - - - - Covered T2,T4,T5
1 - - 0 - - - - - - Covered T3,T11,T23
1 - - - 1 - - - - - Covered T2,T4,T5
1 - - - 0 - - - - - Covered T3,T11,T23
1 - - - - 1 - - - - Covered T2,T4,T5
1 - - - - 0 - - - - Covered T3,T11,T23
1 - - - - - 1 - - - Covered T2,T4,T5
1 - - - - - 0 - - - Covered T3,T11,T23
0 - - - - - - 1 1 - Covered T2,T4,T5
0 - - - - - - 1 0 - Covered T5,T10,T25
0 - - - - - - 0 - 1 Covered T3,T11,T23
0 - - - - - - 0 - 0 Covered T1,T2,T3


Assert Coverage for Module : tlul_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 893 893 0 0
gen_integ_handling.ByteAccessStateChange_A 292034742 6355876 0 0
gen_integ_handling.ReadCompleteStateChange_A 292034742 6355876 0 0
gen_integ_handling.ReadbackAccessAlwaysGranted_A 292034742 100926 0 0
gen_integ_handling.ReadbackDataImmediatelyAvailable_A 292034742 156045 0 0
gen_integ_handling.TlulSramByteTlSize_A 292034742 291903293 0 0
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A 292034742 21346 0 0
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A 292034742 297306 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 893 893 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_integ_handling.ByteAccessStateChange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 6355876 0 0
T2 53880 63 0 0
T3 32722 0 0 0
T4 163544 8473 0 0
T5 757906 12304 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 3410 0 0
T11 9838 521 0 0
T22 0 83 0 0
T23 0 150 0 0
T25 0 31723 0 0
T30 14855 908 0 0
T31 0 4117 0 0

gen_integ_handling.ReadCompleteStateChange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 6355876 0 0
T2 53880 63 0 0
T3 32722 0 0 0
T4 163544 8473 0 0
T5 757906 12304 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 3410 0 0
T11 9838 521 0 0
T22 0 83 0 0
T23 0 150 0 0
T25 0 31723 0 0
T30 14855 908 0 0
T31 0 4117 0 0

gen_integ_handling.ReadbackAccessAlwaysGranted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 100926 0 0
T3 32722 29 0 0
T4 163544 0 0 0
T5 757906 0 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 0 0 0
T11 9838 349 0 0
T23 0 8 0 0
T24 0 3122 0 0
T25 131402 0 0 0
T26 0 66 0 0
T30 14855 0 0 0
T37 0 882 0 0
T40 0 61 0 0
T41 0 209 0 0
T42 0 70 0 0
T43 0 1816 0 0

gen_integ_handling.ReadbackDataImmediatelyAvailable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 156045 0 0
T3 32722 89 0 0
T4 163544 0 0 0
T5 757906 0 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 0 0 0
T11 9838 540 0 0
T23 0 14 0 0
T24 0 4472 0 0
T25 131402 0 0 0
T26 0 218 0 0
T30 14855 0 0 0
T37 0 872 0 0
T40 0 202 0 0
T41 0 519 0 0
T42 0 173 0 0
T43 0 1809 0 0

gen_integ_handling.TlulSramByteTlSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 291903293 0 0
T1 22985 17658 0 0
T2 53880 53628 0 0
T3 32722 32649 0 0
T4 163544 163537 0 0
T5 757906 757424 0 0
T7 3243 3160 0 0
T8 2469 2395 0 0
T9 220288 220218 0 0
T10 310452 310394 0 0
T11 9838 9769 0 0

gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 21346 0 0
T11 9838 521 0 0
T18 64259 0 0 0
T22 4707 0 0 0
T23 82828 0 0 0
T24 212693 530 0 0
T25 131402 0 0 0
T26 0 22 0 0
T30 14855 0 0 0
T31 78144 0 0 0
T35 0 115 0 0
T37 0 538 0 0
T39 0 445 0 0
T43 0 933 0 0
T44 0 74 0 0
T45 0 514 0 0
T46 0 19 0 0
T47 306440 0 0 0
T48 13218 0 0 0

gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 297306 0 0
T3 32722 613 0 0
T4 163544 0 0 0
T5 757906 0 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 0 0 0
T11 9838 928 0 0
T23 0 72 0 0
T24 0 11584 0 0
T25 131402 0 0 0
T26 0 1622 0 0
T30 14855 0 0 0
T37 0 932 0 0
T40 0 1267 0 0
T41 0 3419 0 0
T42 0 1134 0 0
T43 0 1868 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
Line No.TotalCoveredPercent
TOTAL14514499.31
ALWAYS10533100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15611100.00
ALWAYS239959498.95
CONT_ASSIGN50611100.00
CONT_ASSIGN51711100.00
ALWAYS54222100.00
ALWAYS55300
ALWAYS55322100.00
ALWAYS57222100.00
ALWAYS5792222100.00
CONT_ASSIGN63311100.00
ALWAYS65844100.00
CONT_ASSIGN67611100.00
CONT_ASSIGN69911100.00
CONT_ASSIGN71611100.00
CONT_ASSIGN71711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
106 1 1
108 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
144 1 1
145 1 1
156 1 1
239 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
253 1 1
255 1 1
257 1 1
262 1 1
263 1 1
266 1 1
267 0 1
MISSING_ELSE
MISSING_ELSE
271 1 1
272 1 1
273 1 1
274 1 1
MISSING_ELSE
276 1 1
280 1 1
281 1 1
MISSING_ELSE
284 1 1
287 1 1
MISSING_ELSE
295 1 1
296 1 1
297 1 1
298 1 1
299 1 1
300 1 1
==> MISSING_ELSE
MISSING_ELSE
306 1 1
307 1 1
309 1 1
310 1 1
311 1 1
312 1 1
313 1 1
==> MISSING_ELSE
320 1 1
322 unreachable
MISSING_ELSE
326 1 1
330 1 1
331 1 1
334 1 1
335 1 1
336 1 1
337 1 1
340 1 1
343 1 1
MISSING_ELSE
350 1 1
352 unreachable
MISSING_ELSE
355 1 1
357 1 1
359 1 1
365 1 1
367 unreachable
MISSING_ELSE
371 1 1
373 1 1
375 1 1
378 1 1
MISSING_ELSE
385 1 1
387 unreachable
MISSING_ELSE
392 1 1
395 1 1
398 1 1
400 1 1
403 1 1
409 1 1
==> MISSING_ELSE
417 1 1
419 unreachable
MISSING_ELSE
422 1 1
424 1 1
426 1 1
430 1 1
432 unreachable
MISSING_ELSE
435 1 1
438 1 1
440 1 1
443 1 1
MISSING_ELSE
448 1 1
450 unreachable
MISSING_ELSE
455 1 1
459 1 1
460 1 1
462 1 1
463 1 1
465 1 1
466 1 1
467 1 1
470 1 1
MISSING_ELSE
476 1 1
478 unreachable
MISSING_ELSE
481 1 1
483 1 1
486 1 1
488 1 1
489 1 1
490 1 1
MISSING_ELSE
506 1 1
517 1 1
542 1 1
543 1 1
MISSING_ELSE
553 1 1
554 1 1
572 1 1
573 1 1
579 1 1
581 1 1
590 1 1
591 1 1
593 1 1
596 1 1
598 1 1
602 1 1
603 1 1
605 1 1
606 1 1
607 1 1
608 1 1
610 1 1
612 1 1
614 1 1
617 1 1
618 1 1
620 1 1
621 1 1
MISSING_ELSE
623 1 1
626 1 1
MISSING_ELSE
633 1 1
658 1 1
661 1 1
665 1 1
670 1 1
676 1 1
699 1 1
716 1 1
717 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
TotalCoveredPercent
Conditions979395.88
Logical979395.88
Non-Logical00
Event00

 LINE       138
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       139
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       140
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T11,T31
11CoveredT2,T3,T4

 LINE       141
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       142
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       144
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT2,T4,T5
110CoveredT5,T10,T25
111CoveredT2,T4,T5

 LINE       145
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT2,T4,T5
111CoveredT2,T4,T5

 LINE       156
 EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       266
 EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
             ------------------1------------------    ------2-----
-1--2-StatusTests
01CoveredT3,T11,T23
10Not Covered
11Not Covered

 LINE       281
 EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
             ------------1------------
-1-StatusTests
0CoveredT3,T11,T24
1CoveredT3,T11,T23

 LINE       297
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------
-1-StatusTests
0CoveredT4,T31,T23
1CoveredT2,T4,T5

 LINE       330
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------
-1-StatusTests
0CoveredT23,T35,T36
1CoveredT3,T11,T23

 LINE       395
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------
-1-StatusTests
0Not Covered
1CoveredT11,T24,T37

 LINE       459
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------
-1-StatusTests
0CoveredT35,T36,T38
1CoveredT3,T11,T24

 LINE       517
 EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
             ---------------1---------------   ---------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T5
10CoveredT3,T11,T23

 LINE       542
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------
-1--2-StatusTestsExclude Annotation
01Excluded [UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle
10CoveredT2,T3,T4
11CoveredT2,T4,T5

 LINE       554
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT2,T3,T4

 LINE       581
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
             ------1-----   -------------2------------   ---------------3--------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT3,T11,T23
010CoveredT2,T4,T5
100CoveredT1,T2,T3

 LINE       590
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT11,T24,T37
010CoveredT3,T11,T23
100CoveredT2,T4,T5

 LINE       593
 EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
             -------------1-------------
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       596
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       596
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------
-1--2-StatusTests
00CoveredT3,T11,T23
01CoveredT11,T24,T37
10CoveredT2,T4,T5

 LINE       598
 EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
             -------------------------------------1------------------------------------
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       598
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------
-1--2-StatusTests
00CoveredT3,T11,T23
01CoveredT11,T24,T37
10CoveredT2,T4,T5

 LINE       603
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       603
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------
-1--2-StatusTests
00CoveredT3,T11,T23
01CoveredT11,T24,T37
10CoveredT2,T4,T5

 LINE       607
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
             -------------1-------------
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       608
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
             -------------1-------------
-1-StatusTests
0CoveredT3,T11,T23
1CoveredT2,T4,T5

 LINE       614
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------
-1--2-StatusTests
00CoveredT5,T10,T25
01CoveredT2,T4,T5
10CoveredT2,T4,T5

 LINE       620
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T4,T5
11CoveredT2,T4,T5

 LINE       633
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       661
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT2,T4,T7
1011ExcludedT11,T24,T37 VC_COV_UNR
1101Excluded VC_COV_UNR
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3

 LINE       665
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
             --------1--------   ---------------2---------------   -----------------3-----------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T4,T5
110CoveredT3,T11,T23
111CoveredT2,T3,T4

 LINE       699
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT11,T24,T37
010CoveredT3,T11,T23
100CoveredT2,T4,T5

FSM Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
Summary for FSM :: gen_integ_handling.state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 17 17 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q
statesLine No.CoveredTests
StByteWrReadBack 403 Covered T11,T24,T37
StByteWrReadBackDWait 409 Covered T11,T26,T39
StByteWrReadBackInit 310 Covered T11,T24,T37
StPassThru 310 Covered T1,T2,T3
StRdReadBack 281 Covered T3,T11,T24
StRdReadBackDWait 470 Covered T3,T11,T40
StWaitRd 274 Covered T2,T4,T5
StWrReadBack 340 Covered T3,T11,T23
StWrReadBackDWait 343 Covered T3,T11,T23
StWrReadBackInit 281 Covered T3,T11,T23
StWriteCmd 300 Covered T2,T4,T5


transitionsLine No.CoveredTests
StByteWrReadBack->StPassThru 426 Covered T11,T24,T37
StByteWrReadBackDWait->StByteWrReadBack 443 Covered T11,T26,T39
StByteWrReadBackInit->StByteWrReadBack 403 Covered T11,T24,T37
StByteWrReadBackInit->StByteWrReadBackDWait 409 Covered T11,T26,T39
StPassThru->StRdReadBack 281 Covered T3,T11,T24
StPassThru->StWaitRd 274 Covered T2,T4,T5
StPassThru->StWrReadBackInit 281 Covered T3,T11,T23
StRdReadBack->StPassThru 463 Covered T3,T11,T24
StRdReadBack->StRdReadBackDWait 470 Covered T3,T11,T40
StRdReadBackDWait->StPassThru 486 Covered T3,T11,T40
StWaitRd->StWriteCmd 300 Covered T2,T4,T5
StWrReadBack->StPassThru 359 Covered T3,T11,T23
StWrReadBackDWait->StWrReadBack 378 Covered T3,T11,T23
StWrReadBackInit->StWrReadBack 340 Covered T3,T11,T23
StWrReadBackInit->StWrReadBackDWait 343 Covered T3,T11,T23
StWriteCmd->StByteWrReadBackInit 310 Covered T11,T24,T37
StWriteCmd->StPassThru 310 Covered T2,T4,T5



Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
Line No.TotalCoveredPercent
Branches 61 56 91.80
IF 105 2 2 100.00
CASE 255 39 34 87.18
IF 542 2 2 100.00
TERNARY 554 2 2 100.00
IF 590 16 16 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 105 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 255 case (gen_integ_handling.state_q) -2-: 257 if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q))) -3-: 266 if (((!gen_integ_handling.rdback_chk_ok) && (!error_i))) -4-: 271 if (gen_integ_handling.byte_wr_txn) -5-: 273 if (gen_integ_handling.byte_req_ack) -6-: 276 if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i))) -7-: 281 (gen_integ_handling.wr_txn) ? -8-: 284 if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q))) -9-: 297 if ((gen_integ_handling.pending_txn_cnt == 2'(1))) -10-: 299 if (gen_integ_handling.sram_d_ack) -11-: 309 if (gen_integ_handling.sram_a_ack) -12-: 320 if ((EnableReadback == 1'b0)) -13-: 330 if ((gen_integ_handling.pending_txn_cnt == 2'(1))) -14-: 337 if (gen_integ_handling.d_ack) -15-: 350 if ((EnableReadback == 1'b0)) -16-: 365 if ((EnableReadback == 1'b0)) -17-: 375 if (gen_integ_handling.d_ack) -18-: 385 if ((EnableReadback == 1'b0)) -19-: 395 if ((gen_integ_handling.pending_txn_cnt == 2'(1))) -20-: 400 if (gen_integ_handling.d_ack) -21-: 417 if ((EnableReadback == 1'b0)) -22-: 430 if ((EnableReadback == 1'b0)) -23-: 440 if (gen_integ_handling.d_ack) -24-: 448 if ((EnableReadback == 1'b0)) -25-: 459 if ((gen_integ_handling.pending_txn_cnt == 2'(1))) -26-: 462 if (gen_integ_handling.d_ack) -27-: 476 if ((EnableReadback == 1'b0)) -28-: 483 if (gen_integ_handling.d_ack)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28-StatusTests
StPassThru 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
StPassThru 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T3,T11,T23
StPassThru 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StPassThru - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T5
StPassThru - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T5,T10
StPassThru - - 0 - 1 1 - - - - - - - - - - - - - - - - - - - - - Covered T3,T11,T23
StPassThru - - 0 - 1 0 - - - - - - - - - - - - - - - - - - - - - Covered T3,T11,T24
StPassThru - - 0 - 0 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StPassThru - - - - - - 1 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StPassThru - - - - - - 0 - - - - - - - - - - - - - - - - - - - - Covered T2,T3,T4
StWaitRd - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - Covered T2,T4,T5
StWaitRd - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - Not Covered
StWaitRd - - - - - - - 0 - - - - - - - - - - - - - - - - - - - Covered T4,T31,T23
StWriteCmd - - - - - - - - - 1 - - - - - - - - - - - - - - - - - Covered T2,T4,T5
StWriteCmd - - - - - - - - - 0 - - - - - - - - - - - - - - - - - Not Covered
StWrReadBackInit - - - - - - - - - - 1 - - - - - - - - - - - - - - - - Unreachable
StWrReadBackInit - - - - - - - - - - 0 - - - - - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackInit - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackInit - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackInit - - - - - - - - - - - 0 - - - - - - - - - - - - - - - Covered T23,T35,T36
StWrReadBack - - - - - - - - - - - - - 1 - - - - - - - - - - - - - Unreachable
StWrReadBack - - - - - - - - - - - - - 0 - - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackDWait - - - - - - - - - - - - - - 1 - - - - - - - - - - - - Unreachable
StWrReadBackDWait - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackDWait - - - - - - - - - - - - - - - 1 - - - - - - - - - - - Covered T3,T11,T23
StWrReadBackDWait - - - - - - - - - - - - - - - 0 - - - - - - - - - - - Covered T3,T11,T23
StByteWrReadBackInit - - - - - - - - - - - - - - - - 1 - - - - - - - - - - Unreachable
StByteWrReadBackInit - - - - - - - - - - - - - - - - 0 - - - - - - - - - - Covered T11,T24,T37
StByteWrReadBackInit - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - Covered T11,T24,T37
StByteWrReadBackInit - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - Covered T11,T37,T26
StByteWrReadBackInit - - - - - - - - - - - - - - - - - 0 - - - - - - - - - Not Covered
StByteWrReadBack - - - - - - - - - - - - - - - - - - - 1 - - - - - - - Unreachable
StByteWrReadBack - - - - - - - - - - - - - - - - - - - 0 - - - - - - - Covered T11,T24,T37
StByteWrReadBackDWait - - - - - - - - - - - - - - - - - - - - 1 - - - - - - Unreachable
StByteWrReadBackDWait - - - - - - - - - - - - - - - - - - - - 0 - - - - - - Covered T11,T26,T39
StByteWrReadBackDWait - - - - - - - - - - - - - - - - - - - - - 1 - - - - - Covered T11,T26,T39
StByteWrReadBackDWait - - - - - - - - - - - - - - - - - - - - - 0 - - - - - Covered T11,T26,T39
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - 1 - - - - Unreachable
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - 0 - - - - Covered T3,T11,T24
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - - 1 1 - - Covered T3,T11,T24
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - - 1 0 - - Covered T3,T11,T41
StRdReadBack - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Covered T35,T36,T38
StRdReadBackDWait - - - - - - - - - - - - - - - - - - - - - - - - - 1 - Unreachable
StRdReadBackDWait - - - - - - - - - - - - - - - - - - - - - - - - - 0 - Covered T3,T11,T40
StRdReadBackDWait - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T3,T11,T40
StRdReadBackDWait - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T3,T11,T40
default - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 542 if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:
-1-StatusTests
1 Covered T2,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 554 (gen_integ_handling.held_data.a_mask[i]) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T4,T5


LineNo. Expression -1-: 590 if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback)) -2-: 593 (gen_integ_handling.wr_phase) ? -3-: 596 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? -4-: 598 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? -5-: 603 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? -6-: 607 (gen_integ_handling.wr_phase) ? -7-: 608 (gen_integ_handling.wr_phase) ? -8-: 610 if (gen_integ_handling.rd_phase) -9-: 614 if (((!error_i) || gen_integ_handling.stall_host)) -10-: 623 if (gen_integ_handling.wait_phase)

Branches:
-1--2--3--4--5--6--7--8--9--10-StatusTests
1 1 - - - - - - - - Covered T2,T4,T5
1 0 - - - - - - - - Covered T3,T11,T23
1 - 1 - - - - - - - Covered T2,T4,T5
1 - 0 - - - - - - - Covered T3,T11,T23
1 - - 1 - - - - - - Covered T2,T4,T5
1 - - 0 - - - - - - Covered T3,T11,T23
1 - - - 1 - - - - - Covered T2,T4,T5
1 - - - 0 - - - - - Covered T3,T11,T23
1 - - - - 1 - - - - Covered T2,T4,T5
1 - - - - 0 - - - - Covered T3,T11,T23
1 - - - - - 1 - - - Covered T2,T4,T5
1 - - - - - 0 - - - Covered T3,T11,T23
0 - - - - - - 1 1 - Covered T2,T4,T5
0 - - - - - - 1 0 - Covered T5,T10,T25
0 - - - - - - 0 - 1 Covered T3,T11,T23
0 - - - - - - 0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 893 893 0 0
gen_integ_handling.ByteAccessStateChange_A 292034742 6355876 0 0
gen_integ_handling.ReadCompleteStateChange_A 292034742 6355876 0 0
gen_integ_handling.ReadbackAccessAlwaysGranted_A 292034742 100926 0 0
gen_integ_handling.ReadbackDataImmediatelyAvailable_A 292034742 156045 0 0
gen_integ_handling.TlulSramByteTlSize_A 292034742 291903293 0 0
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A 292034742 21346 0 0
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A 292034742 297306 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 893 893 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

gen_integ_handling.ByteAccessStateChange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 6355876 0 0
T2 53880 63 0 0
T3 32722 0 0 0
T4 163544 8473 0 0
T5 757906 12304 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 3410 0 0
T11 9838 521 0 0
T22 0 83 0 0
T23 0 150 0 0
T25 0 31723 0 0
T30 14855 908 0 0
T31 0 4117 0 0

gen_integ_handling.ReadCompleteStateChange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 6355876 0 0
T2 53880 63 0 0
T3 32722 0 0 0
T4 163544 8473 0 0
T5 757906 12304 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 3410 0 0
T11 9838 521 0 0
T22 0 83 0 0
T23 0 150 0 0
T25 0 31723 0 0
T30 14855 908 0 0
T31 0 4117 0 0

gen_integ_handling.ReadbackAccessAlwaysGranted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 100926 0 0
T3 32722 29 0 0
T4 163544 0 0 0
T5 757906 0 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 0 0 0
T11 9838 349 0 0
T23 0 8 0 0
T24 0 3122 0 0
T25 131402 0 0 0
T26 0 66 0 0
T30 14855 0 0 0
T37 0 882 0 0
T40 0 61 0 0
T41 0 209 0 0
T42 0 70 0 0
T43 0 1816 0 0

gen_integ_handling.ReadbackDataImmediatelyAvailable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 156045 0 0
T3 32722 89 0 0
T4 163544 0 0 0
T5 757906 0 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 0 0 0
T11 9838 540 0 0
T23 0 14 0 0
T24 0 4472 0 0
T25 131402 0 0 0
T26 0 218 0 0
T30 14855 0 0 0
T37 0 872 0 0
T40 0 202 0 0
T41 0 519 0 0
T42 0 173 0 0
T43 0 1809 0 0

gen_integ_handling.TlulSramByteTlSize_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 291903293 0 0
T1 22985 17658 0 0
T2 53880 53628 0 0
T3 32722 32649 0 0
T4 163544 163537 0 0
T5 757906 757424 0 0
T7 3243 3160 0 0
T8 2469 2395 0 0
T9 220288 220218 0 0
T10 310452 310394 0 0
T11 9838 9769 0 0

gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 21346 0 0
T11 9838 521 0 0
T18 64259 0 0 0
T22 4707 0 0 0
T23 82828 0 0 0
T24 212693 530 0 0
T25 131402 0 0 0
T26 0 22 0 0
T30 14855 0 0 0
T31 78144 0 0 0
T35 0 115 0 0
T37 0 538 0 0
T39 0 445 0 0
T43 0 933 0 0
T44 0 74 0 0
T45 0 514 0 0
T46 0 19 0 0
T47 306440 0 0 0
T48 13218 0 0 0

gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 292034742 297306 0 0
T3 32722 613 0 0
T4 163544 0 0 0
T5 757906 0 0 0
T7 3243 0 0 0
T8 2469 0 0 0
T9 220288 0 0 0
T10 310452 0 0 0
T11 9838 928 0 0
T23 0 72 0 0
T24 0 11584 0 0
T25 131402 0 0 0
T26 0 1622 0 0
T30 14855 0 0 0
T37 0 932 0 0
T40 0 1267 0 0
T41 0 3419 0 0
T42 0 1134 0 0
T43 0 1868 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%