T796 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1572994626 |
|
|
Jun 26 05:34:21 PM PDT 24 |
Jun 26 05:38:18 PM PDT 24 |
9101019141 ps |
T797 |
/workspace/coverage/default/12.sram_ctrl_executable.1191620611 |
|
|
Jun 26 05:29:32 PM PDT 24 |
Jun 26 05:43:20 PM PDT 24 |
15157532846 ps |
T798 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.2352782817 |
|
|
Jun 26 05:30:17 PM PDT 24 |
Jun 26 05:30:23 PM PDT 24 |
233657739 ps |
T799 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.4266046003 |
|
|
Jun 26 05:32:15 PM PDT 24 |
Jun 26 05:32:19 PM PDT 24 |
160052474 ps |
T800 |
/workspace/coverage/default/34.sram_ctrl_executable.139613894 |
|
|
Jun 26 05:32:29 PM PDT 24 |
Jun 26 05:48:39 PM PDT 24 |
6170704852 ps |
T801 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.2502749976 |
|
|
Jun 26 05:32:38 PM PDT 24 |
Jun 26 05:33:35 PM PDT 24 |
107066995 ps |
T802 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3657029898 |
|
|
Jun 26 05:34:42 PM PDT 24 |
Jun 26 05:34:51 PM PDT 24 |
724480604 ps |
T803 |
/workspace/coverage/default/2.sram_ctrl_bijection.2464578437 |
|
|
Jun 26 05:27:57 PM PDT 24 |
Jun 26 05:29:00 PM PDT 24 |
947040379 ps |
T804 |
/workspace/coverage/default/37.sram_ctrl_regwen.1409688762 |
|
|
Jun 26 05:32:59 PM PDT 24 |
Jun 26 05:36:35 PM PDT 24 |
6085000987 ps |
T805 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1250042584 |
|
|
Jun 26 05:28:14 PM PDT 24 |
Jun 26 05:30:47 PM PDT 24 |
465913126 ps |
T806 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.515891429 |
|
|
Jun 26 05:30:18 PM PDT 24 |
Jun 26 05:30:23 PM PDT 24 |
27720921 ps |
T807 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3760130054 |
|
|
Jun 26 05:28:05 PM PDT 24 |
Jun 26 05:29:32 PM PDT 24 |
1635189711 ps |
T808 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1007494382 |
|
|
Jun 26 05:33:20 PM PDT 24 |
Jun 26 05:48:58 PM PDT 24 |
21556302722 ps |
T809 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1298735828 |
|
|
Jun 26 05:33:37 PM PDT 24 |
Jun 26 05:33:41 PM PDT 24 |
91383288 ps |
T810 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2513492524 |
|
|
Jun 26 05:27:48 PM PDT 24 |
Jun 26 05:27:56 PM PDT 24 |
995223082 ps |
T811 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.440604258 |
|
|
Jun 26 05:33:05 PM PDT 24 |
Jun 26 05:33:09 PM PDT 24 |
253381469 ps |
T812 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2300289705 |
|
|
Jun 26 05:31:49 PM PDT 24 |
Jun 26 05:31:53 PM PDT 24 |
90037678 ps |
T813 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2649261423 |
|
|
Jun 26 05:31:24 PM PDT 24 |
Jun 26 05:40:06 PM PDT 24 |
6306721183 ps |
T814 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2894718803 |
|
|
Jun 26 05:32:58 PM PDT 24 |
Jun 26 05:37:56 PM PDT 24 |
6009092381 ps |
T815 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1857982056 |
|
|
Jun 26 05:27:53 PM PDT 24 |
Jun 26 05:28:03 PM PDT 24 |
66564129 ps |
T816 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1270271973 |
|
|
Jun 26 05:34:08 PM PDT 24 |
Jun 26 05:34:16 PM PDT 24 |
474998213 ps |
T817 |
/workspace/coverage/default/9.sram_ctrl_smoke.168518209 |
|
|
Jun 26 05:28:48 PM PDT 24 |
Jun 26 05:29:05 PM PDT 24 |
444175198 ps |
T818 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3606859547 |
|
|
Jun 26 05:32:30 PM PDT 24 |
Jun 26 05:34:41 PM PDT 24 |
1296661318 ps |
T819 |
/workspace/coverage/default/6.sram_ctrl_smoke.1057998877 |
|
|
Jun 26 05:28:21 PM PDT 24 |
Jun 26 05:28:37 PM PDT 24 |
1260966319 ps |
T820 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3384959525 |
|
|
Jun 26 05:32:40 PM PDT 24 |
Jun 26 05:32:45 PM PDT 24 |
621163445 ps |
T821 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.3847749663 |
|
|
Jun 26 05:33:36 PM PDT 24 |
Jun 26 05:33:39 PM PDT 24 |
512662596 ps |
T822 |
/workspace/coverage/default/12.sram_ctrl_regwen.2393136947 |
|
|
Jun 26 05:29:30 PM PDT 24 |
Jun 26 05:30:34 PM PDT 24 |
11242265523 ps |
T823 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2537966669 |
|
|
Jun 26 05:30:12 PM PDT 24 |
Jun 26 05:30:14 PM PDT 24 |
30090053 ps |
T824 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1654300065 |
|
|
Jun 26 05:29:20 PM PDT 24 |
Jun 26 05:29:24 PM PDT 24 |
541113659 ps |
T825 |
/workspace/coverage/default/36.sram_ctrl_partial_access.1848785293 |
|
|
Jun 26 05:32:40 PM PDT 24 |
Jun 26 05:32:58 PM PDT 24 |
2216305882 ps |
T826 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.3176770529 |
|
|
Jun 26 05:33:29 PM PDT 24 |
Jun 26 05:47:51 PM PDT 24 |
11492912493 ps |
T827 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1496736097 |
|
|
Jun 26 05:31:18 PM PDT 24 |
Jun 26 05:32:35 PM PDT 24 |
474031653 ps |
T828 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2025078992 |
|
|
Jun 26 05:28:26 PM PDT 24 |
Jun 26 06:51:51 PM PDT 24 |
15139213937 ps |
T829 |
/workspace/coverage/default/24.sram_ctrl_smoke.1468316270 |
|
|
Jun 26 05:31:04 PM PDT 24 |
Jun 26 05:33:09 PM PDT 24 |
1268808388 ps |
T830 |
/workspace/coverage/default/2.sram_ctrl_executable.896796261 |
|
|
Jun 26 05:28:01 PM PDT 24 |
Jun 26 05:34:37 PM PDT 24 |
2622555229 ps |
T831 |
/workspace/coverage/default/16.sram_ctrl_partial_access.634097491 |
|
|
Jun 26 05:30:03 PM PDT 24 |
Jun 26 05:30:18 PM PDT 24 |
1764317516 ps |
T832 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3858674200 |
|
|
Jun 26 05:31:26 PM PDT 24 |
Jun 26 05:31:29 PM PDT 24 |
148054463 ps |
T833 |
/workspace/coverage/default/7.sram_ctrl_bijection.3912795355 |
|
|
Jun 26 05:28:28 PM PDT 24 |
Jun 26 05:29:30 PM PDT 24 |
1014184010 ps |
T84 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3467881242 |
|
|
Jun 26 05:34:29 PM PDT 24 |
Jun 26 05:34:35 PM PDT 24 |
1262542624 ps |
T834 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.982156109 |
|
|
Jun 26 05:31:25 PM PDT 24 |
Jun 26 05:31:27 PM PDT 24 |
96218448 ps |
T835 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2056979041 |
|
|
Jun 26 05:28:49 PM PDT 24 |
Jun 26 05:29:37 PM PDT 24 |
202092428 ps |
T836 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3090362511 |
|
|
Jun 26 05:28:26 PM PDT 24 |
Jun 26 05:53:50 PM PDT 24 |
16904744244 ps |
T837 |
/workspace/coverage/default/24.sram_ctrl_regwen.24520621 |
|
|
Jun 26 05:31:09 PM PDT 24 |
Jun 26 05:40:58 PM PDT 24 |
10157967932 ps |
T838 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1453021053 |
|
|
Jun 26 05:30:25 PM PDT 24 |
Jun 26 05:45:13 PM PDT 24 |
45590852664 ps |
T839 |
/workspace/coverage/default/28.sram_ctrl_bijection.2668406883 |
|
|
Jun 26 05:31:25 PM PDT 24 |
Jun 26 05:32:29 PM PDT 24 |
930800783 ps |
T840 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3074544678 |
|
|
Jun 26 05:30:16 PM PDT 24 |
Jun 26 05:37:28 PM PDT 24 |
4701364725 ps |
T841 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1587463546 |
|
|
Jun 26 05:34:27 PM PDT 24 |
Jun 26 05:36:24 PM PDT 24 |
5556502493 ps |
T842 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3072462952 |
|
|
Jun 26 05:33:57 PM PDT 24 |
Jun 26 05:33:58 PM PDT 24 |
140173335 ps |
T843 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2631907965 |
|
|
Jun 26 05:33:21 PM PDT 24 |
Jun 26 05:33:51 PM PDT 24 |
315466062 ps |
T844 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.175891227 |
|
|
Jun 26 05:32:38 PM PDT 24 |
Jun 26 05:37:10 PM PDT 24 |
2979881233 ps |
T845 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.1914379224 |
|
|
Jun 26 05:32:15 PM PDT 24 |
Jun 26 05:48:22 PM PDT 24 |
33691079316 ps |
T846 |
/workspace/coverage/default/39.sram_ctrl_smoke.2269703029 |
|
|
Jun 26 05:33:04 PM PDT 24 |
Jun 26 05:33:36 PM PDT 24 |
162741431 ps |
T847 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.4093260147 |
|
|
Jun 26 05:29:19 PM PDT 24 |
Jun 26 05:46:52 PM PDT 24 |
75223237584 ps |
T848 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1522459658 |
|
|
Jun 26 05:28:05 PM PDT 24 |
Jun 26 05:35:13 PM PDT 24 |
34925119679 ps |
T849 |
/workspace/coverage/default/44.sram_ctrl_executable.3788071544 |
|
|
Jun 26 05:34:09 PM PDT 24 |
Jun 26 05:47:49 PM PDT 24 |
14173657148 ps |
T850 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.552355298 |
|
|
Jun 26 05:29:05 PM PDT 24 |
Jun 26 05:29:13 PM PDT 24 |
1102660283 ps |
T851 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3736193933 |
|
|
Jun 26 05:34:05 PM PDT 24 |
Jun 26 05:34:13 PM PDT 24 |
1331606425 ps |
T852 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3749861853 |
|
|
Jun 26 05:30:47 PM PDT 24 |
Jun 26 05:31:32 PM PDT 24 |
440719496 ps |
T853 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3677381011 |
|
|
Jun 26 05:34:02 PM PDT 24 |
Jun 26 05:34:07 PM PDT 24 |
79763491 ps |
T854 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.1106323610 |
|
|
Jun 26 05:29:32 PM PDT 24 |
Jun 26 05:29:38 PM PDT 24 |
80112349 ps |
T855 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2192224771 |
|
|
Jun 26 05:32:10 PM PDT 24 |
Jun 26 05:38:14 PM PDT 24 |
14712817670 ps |
T856 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.532565921 |
|
|
Jun 26 05:33:21 PM PDT 24 |
Jun 26 05:34:15 PM PDT 24 |
106393583 ps |
T857 |
/workspace/coverage/default/1.sram_ctrl_executable.3505417057 |
|
|
Jun 26 05:27:54 PM PDT 24 |
Jun 26 05:41:07 PM PDT 24 |
11584126921 ps |
T858 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3918121250 |
|
|
Jun 26 05:34:39 PM PDT 24 |
Jun 26 05:37:43 PM PDT 24 |
1841704095 ps |
T29 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.4126554914 |
|
|
Jun 26 05:28:00 PM PDT 24 |
Jun 26 05:28:05 PM PDT 24 |
1675888745 ps |
T859 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3355570107 |
|
|
Jun 26 05:29:00 PM PDT 24 |
Jun 26 05:30:19 PM PDT 24 |
438557399 ps |
T860 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2515754934 |
|
|
Jun 26 05:35:12 PM PDT 24 |
Jun 26 05:35:21 PM PDT 24 |
902510926 ps |
T861 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.905891749 |
|
|
Jun 26 05:31:18 PM PDT 24 |
Jun 26 05:33:30 PM PDT 24 |
146148209 ps |
T862 |
/workspace/coverage/default/12.sram_ctrl_smoke.2726759365 |
|
|
Jun 26 05:29:18 PM PDT 24 |
Jun 26 05:29:41 PM PDT 24 |
1672747242 ps |
T863 |
/workspace/coverage/default/1.sram_ctrl_smoke.972445088 |
|
|
Jun 26 05:27:56 PM PDT 24 |
Jun 26 05:28:07 PM PDT 24 |
272048350 ps |
T864 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.271342985 |
|
|
Jun 26 05:28:59 PM PDT 24 |
Jun 26 05:32:53 PM PDT 24 |
16279437300 ps |
T865 |
/workspace/coverage/default/14.sram_ctrl_partial_access.2849374889 |
|
|
Jun 26 05:29:40 PM PDT 24 |
Jun 26 05:29:48 PM PDT 24 |
508771841 ps |
T866 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2881702949 |
|
|
Jun 26 05:28:27 PM PDT 24 |
Jun 26 05:28:31 PM PDT 24 |
944990368 ps |
T867 |
/workspace/coverage/default/18.sram_ctrl_executable.4046652452 |
|
|
Jun 26 05:30:38 PM PDT 24 |
Jun 26 05:59:44 PM PDT 24 |
35106809193 ps |
T868 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1804008246 |
|
|
Jun 26 05:30:29 PM PDT 24 |
Jun 26 05:31:06 PM PDT 24 |
976175604 ps |
T869 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2073631497 |
|
|
Jun 26 05:30:51 PM PDT 24 |
Jun 26 05:30:54 PM PDT 24 |
185650060 ps |
T870 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3024036097 |
|
|
Jun 26 05:32:00 PM PDT 24 |
Jun 26 05:44:46 PM PDT 24 |
8513540167 ps |
T871 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.3514234659 |
|
|
Jun 26 05:28:04 PM PDT 24 |
Jun 26 05:28:18 PM PDT 24 |
2721733010 ps |
T872 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.3883680082 |
|
|
Jun 26 05:32:40 PM PDT 24 |
Jun 26 05:42:28 PM PDT 24 |
13213228383 ps |
T873 |
/workspace/coverage/default/9.sram_ctrl_regwen.2732453974 |
|
|
Jun 26 05:28:50 PM PDT 24 |
Jun 26 05:32:22 PM PDT 24 |
6108016085 ps |
T874 |
/workspace/coverage/default/23.sram_ctrl_partial_access.1663993627 |
|
|
Jun 26 05:31:02 PM PDT 24 |
Jun 26 05:32:02 PM PDT 24 |
172240214 ps |
T875 |
/workspace/coverage/default/36.sram_ctrl_smoke.3082890100 |
|
|
Jun 26 05:32:36 PM PDT 24 |
Jun 26 05:32:38 PM PDT 24 |
44724382 ps |
T876 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3707976869 |
|
|
Jun 26 05:29:51 PM PDT 24 |
Jun 26 05:29:57 PM PDT 24 |
438468224 ps |
T877 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2434012114 |
|
|
Jun 26 05:29:00 PM PDT 24 |
Jun 26 05:29:14 PM PDT 24 |
204526707 ps |
T878 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.396061253 |
|
|
Jun 26 05:28:28 PM PDT 24 |
Jun 26 05:32:06 PM PDT 24 |
8872628982 ps |
T879 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.4245929468 |
|
|
Jun 26 05:29:55 PM PDT 24 |
Jun 26 05:30:07 PM PDT 24 |
363243078 ps |
T880 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3655133889 |
|
|
Jun 26 05:32:08 PM PDT 24 |
Jun 26 05:38:43 PM PDT 24 |
13169729956 ps |
T881 |
/workspace/coverage/default/43.sram_ctrl_executable.2979466294 |
|
|
Jun 26 05:34:02 PM PDT 24 |
Jun 26 05:49:48 PM PDT 24 |
65384969899 ps |
T882 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1578133165 |
|
|
Jun 26 05:33:48 PM PDT 24 |
Jun 26 05:45:47 PM PDT 24 |
5963327560 ps |
T883 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2799075907 |
|
|
Jun 26 05:30:30 PM PDT 24 |
Jun 26 05:30:36 PM PDT 24 |
393253096 ps |
T884 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1535867679 |
|
|
Jun 26 05:34:40 PM PDT 24 |
Jun 26 05:37:18 PM PDT 24 |
151913203 ps |
T885 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2936990552 |
|
|
Jun 26 05:35:16 PM PDT 24 |
Jun 26 06:04:02 PM PDT 24 |
115665930396 ps |
T886 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2582265175 |
|
|
Jun 26 05:34:59 PM PDT 24 |
Jun 26 05:38:58 PM PDT 24 |
9507969884 ps |
T887 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.130332475 |
|
|
Jun 26 05:31:11 PM PDT 24 |
Jun 26 05:34:39 PM PDT 24 |
8371165943 ps |
T888 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2407245982 |
|
|
Jun 26 05:31:16 PM PDT 24 |
Jun 26 05:31:18 PM PDT 24 |
26118962 ps |
T889 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3142185801 |
|
|
Jun 26 05:28:35 PM PDT 24 |
Jun 26 05:28:48 PM PDT 24 |
2578878540 ps |
T890 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.508419171 |
|
|
Jun 26 05:28:35 PM PDT 24 |
Jun 26 05:28:38 PM PDT 24 |
27458544 ps |
T891 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.87755120 |
|
|
Jun 26 05:28:01 PM PDT 24 |
Jun 26 05:28:09 PM PDT 24 |
440589023 ps |
T892 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.255141198 |
|
|
Jun 26 05:30:55 PM PDT 24 |
Jun 26 05:35:04 PM PDT 24 |
3519521787 ps |
T893 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2984522092 |
|
|
Jun 26 05:34:05 PM PDT 24 |
Jun 26 05:34:12 PM PDT 24 |
362568761 ps |
T894 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.263769390 |
|
|
Jun 26 05:28:01 PM PDT 24 |
Jun 26 05:40:52 PM PDT 24 |
11870831217 ps |
T895 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3396739516 |
|
|
Jun 26 05:30:33 PM PDT 24 |
Jun 26 05:42:11 PM PDT 24 |
2144824734 ps |
T896 |
/workspace/coverage/default/37.sram_ctrl_stress_all.559560263 |
|
|
Jun 26 05:33:00 PM PDT 24 |
Jun 26 05:54:54 PM PDT 24 |
68006700303 ps |
T897 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.321627541 |
|
|
Jun 26 05:31:03 PM PDT 24 |
Jun 26 05:39:58 PM PDT 24 |
90046602059 ps |
T898 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.3808428904 |
|
|
Jun 26 05:33:37 PM PDT 24 |
Jun 26 05:33:48 PM PDT 24 |
682344385 ps |
T899 |
/workspace/coverage/default/28.sram_ctrl_executable.591938921 |
|
|
Jun 26 05:31:24 PM PDT 24 |
Jun 26 05:53:50 PM PDT 24 |
28291404422 ps |
T900 |
/workspace/coverage/default/25.sram_ctrl_smoke.979202381 |
|
|
Jun 26 05:31:14 PM PDT 24 |
Jun 26 05:31:49 PM PDT 24 |
372759136 ps |
T901 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.1156724498 |
|
|
Jun 26 05:30:05 PM PDT 24 |
Jun 26 05:30:37 PM PDT 24 |
170532435 ps |
T902 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3836958821 |
|
|
Jun 26 05:34:07 PM PDT 24 |
Jun 26 05:41:46 PM PDT 24 |
18142496509 ps |
T903 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.4209437107 |
|
|
Jun 26 05:28:20 PM PDT 24 |
Jun 26 05:28:30 PM PDT 24 |
59896842 ps |
T904 |
/workspace/coverage/default/15.sram_ctrl_regwen.3868368681 |
|
|
Jun 26 05:29:55 PM PDT 24 |
Jun 26 05:51:55 PM PDT 24 |
47801742256 ps |
T905 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2727756707 |
|
|
Jun 26 05:27:56 PM PDT 24 |
Jun 26 05:27:59 PM PDT 24 |
149017608 ps |
T906 |
/workspace/coverage/default/10.sram_ctrl_stress_all.96651961 |
|
|
Jun 26 05:29:04 PM PDT 24 |
Jun 26 06:14:45 PM PDT 24 |
40688339839 ps |
T907 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.2664919898 |
|
|
Jun 26 05:29:34 PM PDT 24 |
Jun 26 05:29:48 PM PDT 24 |
62458253 ps |
T908 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1887935415 |
|
|
Jun 26 05:32:45 PM PDT 24 |
Jun 26 05:32:47 PM PDT 24 |
16777366 ps |
T909 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2318330189 |
|
|
Jun 26 05:30:46 PM PDT 24 |
Jun 26 05:31:06 PM PDT 24 |
177279416 ps |
T910 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.195539416 |
|
|
Jun 26 05:34:36 PM PDT 24 |
Jun 26 05:34:43 PM PDT 24 |
111349443 ps |
T911 |
/workspace/coverage/default/46.sram_ctrl_alert_test.3065845809 |
|
|
Jun 26 05:34:42 PM PDT 24 |
Jun 26 05:34:43 PM PDT 24 |
14955182 ps |
T912 |
/workspace/coverage/default/3.sram_ctrl_smoke.2372202065 |
|
|
Jun 26 05:28:02 PM PDT 24 |
Jun 26 05:28:20 PM PDT 24 |
740859781 ps |
T913 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.325142163 |
|
|
Jun 26 05:27:54 PM PDT 24 |
Jun 26 05:28:45 PM PDT 24 |
407918105 ps |
T914 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.430677834 |
|
|
Jun 26 05:31:40 PM PDT 24 |
Jun 26 05:45:47 PM PDT 24 |
1068440099 ps |
T915 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.4053981491 |
|
|
Jun 26 05:33:44 PM PDT 24 |
Jun 26 05:37:39 PM PDT 24 |
2403907000 ps |
T916 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2308234771 |
|
|
Jun 26 05:28:57 PM PDT 24 |
Jun 26 05:32:23 PM PDT 24 |
744870078 ps |
T917 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3493173387 |
|
|
Jun 26 05:34:27 PM PDT 24 |
Jun 26 05:34:35 PM PDT 24 |
155928582 ps |
T918 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3546001420 |
|
|
Jun 26 05:28:45 PM PDT 24 |
Jun 26 05:29:19 PM PDT 24 |
193560664 ps |
T919 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3051000585 |
|
|
Jun 26 05:30:50 PM PDT 24 |
Jun 26 05:30:57 PM PDT 24 |
900028048 ps |
T920 |
/workspace/coverage/default/0.sram_ctrl_partial_access.1489279673 |
|
|
Jun 26 05:27:49 PM PDT 24 |
Jun 26 05:29:10 PM PDT 24 |
515926830 ps |
T921 |
/workspace/coverage/default/39.sram_ctrl_bijection.37245210 |
|
|
Jun 26 05:33:10 PM PDT 24 |
Jun 26 05:34:04 PM PDT 24 |
9692200332 ps |
T922 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2189376782 |
|
|
Jun 26 05:34:56 PM PDT 24 |
Jun 26 05:39:25 PM PDT 24 |
873721524 ps |
T923 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.1030414962 |
|
|
Jun 26 05:28:03 PM PDT 24 |
Jun 26 05:28:11 PM PDT 24 |
429631052 ps |
T924 |
/workspace/coverage/default/34.sram_ctrl_bijection.2312225213 |
|
|
Jun 26 05:32:16 PM PDT 24 |
Jun 26 05:32:53 PM PDT 24 |
3265026536 ps |
T925 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.2553455618 |
|
|
Jun 26 05:34:43 PM PDT 24 |
Jun 26 05:34:53 PM PDT 24 |
245355504 ps |
T926 |
/workspace/coverage/default/4.sram_ctrl_regwen.1902056579 |
|
|
Jun 26 05:28:15 PM PDT 24 |
Jun 26 05:42:35 PM PDT 24 |
5195191857 ps |
T927 |
/workspace/coverage/default/43.sram_ctrl_bijection.679558358 |
|
|
Jun 26 05:33:54 PM PDT 24 |
Jun 26 05:34:52 PM PDT 24 |
7218320589 ps |
T928 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1624934993 |
|
|
Jun 26 05:33:00 PM PDT 24 |
Jun 26 05:33:02 PM PDT 24 |
183211522 ps |
T929 |
/workspace/coverage/default/1.sram_ctrl_regwen.382113481 |
|
|
Jun 26 05:27:54 PM PDT 24 |
Jun 26 05:29:19 PM PDT 24 |
622990653 ps |
T930 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.3157842528 |
|
|
Jun 26 05:31:34 PM PDT 24 |
Jun 26 05:33:08 PM PDT 24 |
471825099 ps |
T931 |
/workspace/coverage/default/18.sram_ctrl_regwen.2492287476 |
|
|
Jun 26 05:30:34 PM PDT 24 |
Jun 26 05:49:31 PM PDT 24 |
21076787522 ps |
T932 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.646402605 |
|
|
Jun 26 05:30:17 PM PDT 24 |
Jun 26 05:30:24 PM PDT 24 |
693270624 ps |
T933 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2522706186 |
|
|
Jun 26 05:31:40 PM PDT 24 |
Jun 26 05:41:40 PM PDT 24 |
3420951838 ps |
T934 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3771743831 |
|
|
Jun 26 05:32:47 PM PDT 24 |
Jun 26 05:37:27 PM PDT 24 |
2795869465 ps |
T935 |
/workspace/coverage/default/46.sram_ctrl_regwen.2831649671 |
|
|
Jun 26 05:34:39 PM PDT 24 |
Jun 26 05:35:48 PM PDT 24 |
1674128417 ps |
T936 |
/workspace/coverage/default/31.sram_ctrl_regwen.1973041763 |
|
|
Jun 26 05:31:58 PM PDT 24 |
Jun 26 05:44:10 PM PDT 24 |
20766462697 ps |
T937 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1888013492 |
|
|
Jun 26 07:26:11 PM PDT 24 |
Jun 26 07:26:18 PM PDT 24 |
151029369 ps |
T938 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3630230106 |
|
|
Jun 26 07:26:12 PM PDT 24 |
Jun 26 07:26:17 PM PDT 24 |
34542759 ps |
T54 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2607865150 |
|
|
Jun 26 07:25:55 PM PDT 24 |
Jun 26 07:26:00 PM PDT 24 |
278112018 ps |
T939 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3722964519 |
|
|
Jun 26 07:25:26 PM PDT 24 |
Jun 26 07:25:32 PM PDT 24 |
520582107 ps |
T940 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3312574794 |
|
|
Jun 26 07:25:56 PM PDT 24 |
Jun 26 07:26:02 PM PDT 24 |
277339403 ps |
T55 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3593539395 |
|
|
Jun 26 07:26:12 PM PDT 24 |
Jun 26 07:26:16 PM PDT 24 |
15462615 ps |
T49 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1149701182 |
|
|
Jun 26 07:25:48 PM PDT 24 |
Jun 26 07:25:54 PM PDT 24 |
70009229 ps |
T93 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3382980107 |
|
|
Jun 26 07:25:43 PM PDT 24 |
Jun 26 07:25:47 PM PDT 24 |
39499143 ps |
T63 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3098776401 |
|
|
Jun 26 07:25:57 PM PDT 24 |
Jun 26 07:26:02 PM PDT 24 |
11724973 ps |
T941 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2376210736 |
|
|
Jun 26 07:25:14 PM PDT 24 |
Jun 26 07:25:20 PM PDT 24 |
126433176 ps |
T50 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2609077667 |
|
|
Jun 26 07:25:57 PM PDT 24 |
Jun 26 07:26:02 PM PDT 24 |
106972349 ps |
T942 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3164627988 |
|
|
Jun 26 07:25:45 PM PDT 24 |
Jun 26 07:25:52 PM PDT 24 |
37116000 ps |
T64 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.816705945 |
|
|
Jun 26 07:27:44 PM PDT 24 |
Jun 26 07:27:46 PM PDT 24 |
21484385 ps |
T65 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.132223239 |
|
|
Jun 26 07:26:09 PM PDT 24 |
Jun 26 07:26:12 PM PDT 24 |
13941080 ps |
T51 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4064356341 |
|
|
Jun 26 07:25:45 PM PDT 24 |
Jun 26 07:25:51 PM PDT 24 |
290804933 ps |
T943 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2456353416 |
|
|
Jun 26 07:26:08 PM PDT 24 |
Jun 26 07:26:12 PM PDT 24 |
26597393 ps |
T944 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2950466783 |
|
|
Jun 26 07:26:09 PM PDT 24 |
Jun 26 07:26:13 PM PDT 24 |
154478458 ps |
T945 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3236177503 |
|
|
Jun 26 07:25:46 PM PDT 24 |
Jun 26 07:25:54 PM PDT 24 |
493003109 ps |
T114 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.227333629 |
|
|
Jun 26 07:25:26 PM PDT 24 |
Jun 26 07:25:30 PM PDT 24 |
44901406 ps |
T115 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.424198335 |
|
|
Jun 26 07:25:43 PM PDT 24 |
Jun 26 07:25:47 PM PDT 24 |
13142877 ps |
T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3000015558 |
|
|
Jun 26 07:25:27 PM PDT 24 |
Jun 26 07:25:32 PM PDT 24 |
16097266 ps |
T95 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3044772120 |
|
|
Jun 26 07:25:45 PM PDT 24 |
Jun 26 07:25:50 PM PDT 24 |
47715173 ps |
T96 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2602901561 |
|
|
Jun 26 07:25:44 PM PDT 24 |
Jun 26 07:25:51 PM PDT 24 |
1298407018 ps |
T66 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3169179338 |
|
|
Jun 26 07:25:26 PM PDT 24 |
Jun 26 07:25:30 PM PDT 24 |
59348808 ps |
T67 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4077549091 |
|
|
Jun 26 07:25:44 PM PDT 24 |
Jun 26 07:25:50 PM PDT 24 |
453120106 ps |
T946 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1636945170 |
|
|
Jun 26 07:25:39 PM PDT 24 |
Jun 26 07:25:42 PM PDT 24 |
123832361 ps |
T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3524029372 |
|
|
Jun 26 07:25:11 PM PDT 24 |
Jun 26 07:25:15 PM PDT 24 |
26995985 ps |
T948 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2560109404 |
|
|
Jun 26 07:25:46 PM PDT 24 |
Jun 26 07:25:53 PM PDT 24 |
36427293 ps |
T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2171634976 |
|
|
Jun 26 07:25:43 PM PDT 24 |
Jun 26 07:25:51 PM PDT 24 |
588289512 ps |
T97 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.245213179 |
|
|
Jun 26 07:25:47 PM PDT 24 |
Jun 26 07:25:52 PM PDT 24 |
15318662 ps |
T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2474989241 |
|
|
Jun 26 07:25:44 PM PDT 24 |
Jun 26 07:25:49 PM PDT 24 |
204639112 ps |
T68 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3567688161 |
|
|
Jun 26 07:25:55 PM PDT 24 |
Jun 26 07:25:59 PM PDT 24 |
32454724 ps |
T69 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3600248285 |
|
|
Jun 26 07:25:42 PM PDT 24 |
Jun 26 07:25:46 PM PDT 24 |
34776218 ps |
T70 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3389905919 |
|
|
Jun 26 07:25:27 PM PDT 24 |
Jun 26 07:25:31 PM PDT 24 |
28726928 ps |
T137 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3262888811 |
|
|
Jun 26 07:25:47 PM PDT 24 |
Jun 26 07:25:53 PM PDT 24 |
202629311 ps |
T73 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3176949429 |
|
|
Jun 26 07:26:08 PM PDT 24 |
Jun 26 07:26:13 PM PDT 24 |
474797108 ps |
T135 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.102839292 |
|
|
Jun 26 07:26:09 PM PDT 24 |
Jun 26 07:26:13 PM PDT 24 |
344015040 ps |
T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1594378185 |
|
|
Jun 26 07:25:27 PM PDT 24 |
Jun 26 07:25:31 PM PDT 24 |
44209262 ps |
T952 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1665390334 |
|
|
Jun 26 07:25:28 PM PDT 24 |
Jun 26 07:25:33 PM PDT 24 |
72892965 ps |
T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1030974737 |
|
|
Jun 26 07:26:10 PM PDT 24 |
Jun 26 07:26:14 PM PDT 24 |
15648486 ps |
T136 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.386967043 |
|
|
Jun 26 07:25:58 PM PDT 24 |
Jun 26 07:26:04 PM PDT 24 |
276072574 ps |
T74 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2542278483 |
|
|
Jun 26 07:25:30 PM PDT 24 |
Jun 26 07:25:35 PM PDT 24 |
66527502 ps |
T954 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.499725130 |
|
|
Jun 26 07:26:11 PM PDT 24 |
Jun 26 07:26:15 PM PDT 24 |
14280401 ps |
T955 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.546171941 |
|
|
Jun 26 07:25:58 PM PDT 24 |
Jun 26 07:26:03 PM PDT 24 |
86684657 ps |
T956 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3573407494 |
|
|
Jun 26 07:25:15 PM PDT 24 |
Jun 26 07:25:21 PM PDT 24 |
35343514 ps |
T75 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3607900483 |
|
|
Jun 26 07:25:59 PM PDT 24 |
Jun 26 07:26:06 PM PDT 24 |
1535482495 ps |
T957 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3677133548 |
|
|
Jun 26 07:25:49 PM PDT 24 |
Jun 26 07:25:56 PM PDT 24 |
483779736 ps |
T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2993463535 |
|
|
Jun 26 07:25:27 PM PDT 24 |
Jun 26 07:25:32 PM PDT 24 |
148371117 ps |
T959 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4109063244 |
|
|
Jun 26 07:25:48 PM PDT 24 |
Jun 26 07:25:54 PM PDT 24 |
15388286 ps |
T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.355842102 |
|
|
Jun 26 07:25:59 PM PDT 24 |
Jun 26 07:26:04 PM PDT 24 |
46539238 ps |
T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.790572880 |
|
|
Jun 26 07:25:47 PM PDT 24 |
Jun 26 07:25:53 PM PDT 24 |
833371061 ps |
T962 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1998880141 |
|
|
Jun 26 07:25:45 PM PDT 24 |
Jun 26 07:25:50 PM PDT 24 |
27091883 ps |
T963 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1736746979 |
|
|
Jun 26 07:25:42 PM PDT 24 |
Jun 26 07:25:47 PM PDT 24 |
28107151 ps |
T76 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.861332720 |
|
|
Jun 26 07:25:47 PM PDT 24 |
Jun 26 07:25:52 PM PDT 24 |
17932567 ps |
T77 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3412789343 |
|
|
Jun 26 07:25:45 PM PDT 24 |
Jun 26 07:25:52 PM PDT 24 |
392443003 ps |
T142 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2673071400 |
|
|
Jun 26 07:25:56 PM PDT 24 |
Jun 26 07:26:01 PM PDT 24 |
93258507 ps |
T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1850643134 |
|
|
Jun 26 07:25:27 PM PDT 24 |
Jun 26 07:25:31 PM PDT 24 |
45091453 ps |
T78 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1225220740 |
|
|
Jun 26 07:26:08 PM PDT 24 |
Jun 26 07:26:14 PM PDT 24 |
432258081 ps |
T138 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.419789065 |
|
|
Jun 26 07:25:42 PM PDT 24 |
Jun 26 07:25:48 PM PDT 24 |
517402708 ps |
T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1258037222 |
|
|
Jun 26 07:25:26 PM PDT 24 |
Jun 26 07:25:29 PM PDT 24 |
91849249 ps |
T966 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.646573206 |
|
|
Jun 26 07:26:09 PM PDT 24 |
Jun 26 07:26:16 PM PDT 24 |
452447852 ps |
T967 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.550367227 |
|
|
Jun 26 07:25:53 PM PDT 24 |
Jun 26 07:26:00 PM PDT 24 |
368042700 ps |
T968 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1876135413 |
|
|
Jun 26 07:25:45 PM PDT 24 |
Jun 26 07:25:50 PM PDT 24 |
47964816 ps |
T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1410235584 |
|
|
Jun 26 07:25:11 PM PDT 24 |
Jun 26 07:25:15 PM PDT 24 |
207039956 ps |
T969 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.636102296 |
|
|
Jun 26 07:25:48 PM PDT 24 |
Jun 26 07:25:55 PM PDT 24 |
320865362 ps |
T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2663825461 |
|
|
Jun 26 07:26:10 PM PDT 24 |
Jun 26 07:26:14 PM PDT 24 |
15374945 ps |
T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3851885427 |
|
|
Jun 26 07:26:08 PM PDT 24 |
Jun 26 07:26:11 PM PDT 24 |
15884282 ps |
T972 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2906268148 |
|
|
Jun 26 07:25:59 PM PDT 24 |
Jun 26 07:26:04 PM PDT 24 |
45798256 ps |
T973 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3897623257 |
|
|
Jun 26 07:25:45 PM PDT 24 |
Jun 26 07:25:49 PM PDT 24 |
12138787 ps |
T87 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1254287653 |
|
|
Jun 26 07:25:55 PM PDT 24 |
Jun 26 07:26:01 PM PDT 24 |
312122927 ps |
T88 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1923025798 |
|
|
Jun 26 07:26:09 PM PDT 24 |
Jun 26 07:26:14 PM PDT 24 |
507641184 ps |
T974 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4277025455 |
|
|
Jun 26 07:25:46 PM PDT 24 |
Jun 26 07:25:53 PM PDT 24 |
73551489 ps |
T975 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.231842993 |
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Jun 26 07:25:11 PM PDT 24 |
Jun 26 07:25:16 PM PDT 24 |
101306547 ps |
T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1247684441 |
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Jun 26 07:25:59 PM PDT 24 |
Jun 26 07:26:06 PM PDT 24 |
372128988 ps |
T977 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2326194239 |
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Jun 26 07:26:08 PM PDT 24 |
Jun 26 07:26:13 PM PDT 24 |
283514815 ps |
T978 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.841325322 |
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Jun 26 07:25:55 PM PDT 24 |
Jun 26 07:25:59 PM PDT 24 |
61302428 ps |
T979 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.233272132 |
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Jun 26 07:26:10 PM PDT 24 |
Jun 26 07:26:14 PM PDT 24 |
31592978 ps |
T980 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1129998516 |
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Jun 26 07:25:45 PM PDT 24 |
Jun 26 07:25:50 PM PDT 24 |
77633384 ps |
T981 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1890805630 |
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Jun 26 07:26:11 PM PDT 24 |
Jun 26 07:26:19 PM PDT 24 |
529182467 ps |
T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3884948399 |
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Jun 26 07:25:26 PM PDT 24 |
Jun 26 07:25:32 PM PDT 24 |
220312506 ps |
T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3475215125 |
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Jun 26 07:25:10 PM PDT 24 |
Jun 26 07:25:14 PM PDT 24 |
790054512 ps |
T984 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2312235672 |
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Jun 26 07:25:48 PM PDT 24 |
Jun 26 07:25:55 PM PDT 24 |
383110069 ps |
T985 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3487914592 |
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Jun 26 07:26:09 PM PDT 24 |
Jun 26 07:26:14 PM PDT 24 |
247471800 ps |
T986 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.857792567 |
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Jun 26 07:25:56 PM PDT 24 |
Jun 26 07:26:00 PM PDT 24 |
39514237 ps |
T987 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2838873279 |
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Jun 26 07:25:49 PM PDT 24 |
Jun 26 07:25:55 PM PDT 24 |
53361033 ps |
T988 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3124622625 |
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Jun 26 07:25:43 PM PDT 24 |
Jun 26 07:25:48 PM PDT 24 |
47839583 ps |
T989 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1136574370 |
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Jun 26 07:25:41 PM PDT 24 |
Jun 26 07:25:47 PM PDT 24 |
74503781 ps |
T143 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3603545525 |
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Jun 26 07:26:11 PM PDT 24 |
Jun 26 07:26:15 PM PDT 24 |
131051076 ps |
T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.197645907 |
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Jun 26 07:25:26 PM PDT 24 |
Jun 26 07:25:31 PM PDT 24 |
70864590 ps |
T991 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1692753310 |
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Jun 26 07:25:56 PM PDT 24 |
Jun 26 07:26:01 PM PDT 24 |
158001569 ps |
T992 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1714804635 |
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Jun 26 07:25:45 PM PDT 24 |
Jun 26 07:25:51 PM PDT 24 |
74457659 ps |
T91 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1744435094 |
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Jun 26 07:25:26 PM PDT 24 |
Jun 26 07:25:29 PM PDT 24 |
12398139 ps |
T89 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3916084885 |
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Jun 26 07:25:55 PM PDT 24 |
Jun 26 07:26:00 PM PDT 24 |
281763489 ps |
T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.930222979 |
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Jun 26 07:25:12 PM PDT 24 |
Jun 26 07:25:17 PM PDT 24 |
206262385 ps |
T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2810614834 |
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Jun 26 07:25:56 PM PDT 24 |
Jun 26 07:26:02 PM PDT 24 |
495068333 ps |
T994 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3978135043 |
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Jun 26 07:25:52 PM PDT 24 |
Jun 26 07:25:57 PM PDT 24 |
49949662 ps |
T85 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3936690312 |
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Jun 26 07:25:26 PM PDT 24 |
Jun 26 07:25:30 PM PDT 24 |
37542850 ps |
T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2065585802 |
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Jun 26 07:25:42 PM PDT 24 |
Jun 26 07:25:48 PM PDT 24 |
250888396 ps |
T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.725202924 |
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Jun 26 07:25:27 PM PDT 24 |
Jun 26 07:25:34 PM PDT 24 |
404100235 ps |
T997 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.927193050 |
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Jun 26 07:25:59 PM PDT 24 |
Jun 26 07:26:04 PM PDT 24 |
23107027 ps |
T998 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3091138204 |
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Jun 26 07:26:09 PM PDT 24 |
Jun 26 07:26:15 PM PDT 24 |
526620679 ps |
T999 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4248609121 |
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Jun 26 07:25:56 PM PDT 24 |
Jun 26 07:26:01 PM PDT 24 |
13527857 ps |
T139 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.992383175 |
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Jun 26 07:25:55 PM PDT 24 |
Jun 26 07:26:01 PM PDT 24 |
2053415238 ps |
T140 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2186941800 |
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Jun 26 07:26:11 PM PDT 24 |
Jun 26 07:26:16 PM PDT 24 |
516156391 ps |
T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3036622467 |
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Jun 26 07:25:28 PM PDT 24 |
Jun 26 07:25:34 PM PDT 24 |
127403349 ps |
T1001 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.969276368 |
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Jun 26 07:26:09 PM PDT 24 |
Jun 26 07:26:12 PM PDT 24 |
36389691 ps |
T1002 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3051042711 |
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Jun 26 07:26:11 PM PDT 24 |
Jun 26 07:26:17 PM PDT 24 |
186524396 ps |