SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[sram_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[sram_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 64267298 | 0 | T1 | 893 | T2 | 104911 | T5 | 10000 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 64267100 | 1 | T1 | 893 | T2 | 104911 | T5 | 10000 | ||||
values[1] | 24 | 1 | T55 | 3 | T56 | 2 | T121 | 2 | ||||
values[2] | 4 | 1 | T56 | 1 | T122 | 1 | T121 | 1 | ||||
values[3] | 93 | 1 | T54 | 3 | T55 | 1 | T56 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 64267115 | 1 | T1 | 893 | T2 | 104911 | T5 | 10000 | ||||
values[1] | 18 | 1 | T54 | 1 | T55 | 1 | T56 | 1 | ||||
values[2] | 6 | 1 | T55 | 1 | T56 | 1 | T123 | 2 | ||||
values[3] | 105 | 1 | T54 | 3 | T55 | 2 | T56 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 64267008 | 1 | T1 | 893 | T2 | 104911 | T5 | 10000 | ||||
auto[TlIntgErrCmd] | 107 | 1 | T54 | 1 | T55 | 6 | T56 | 7 | ||||
auto[TlIntgErrData] | 92 | 1 | T54 | 5 | T55 | 3 | T56 | 7 | ||||
auto[TlIntgErrBoth] | 91 | 1 | T54 | 4 | T55 | 1 | T56 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 443973 | 0 | T1 | 53 | T2 | 55 | T3 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 443786 | 1 | T1 | 53 | T2 | 55 | T3 | 11 | ||||
values[1] | 23 | 1 | T55 | 1 | T56 | 1 | T122 | 3 | ||||
values[2] | 1 | 1 | T124 | 1 | - | - | - | - | ||||
values[3] | 88 | 1 | T54 | 4 | T55 | 2 | T56 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 443776 | 1 | T1 | 53 | T2 | 55 | T3 | 11 | ||||
values[1] | 18 | 1 | T54 | 2 | T55 | 1 | T56 | 1 | ||||
values[2] | 4 | 1 | T125 | 1 | T126 | 2 | T127 | 1 | ||||
values[3] | 104 | 1 | T54 | 7 | T55 | 6 | T56 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 443683 | 1 | T1 | 53 | T2 | 55 | T3 | 11 | ||||
auto[TlIntgErrCmd] | 93 | 1 | T54 | 1 | T55 | 2 | T56 | 5 | ||||
auto[TlIntgErrData] | 103 | 1 | T54 | 6 | T55 | 6 | T56 | 7 | ||||
auto[TlIntgErrBoth] | 94 | 1 | T54 | 3 | T55 | 2 | T56 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |