Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13854430	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

55167173

1

T1

2428

T2

119345

T5

10000

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34389941	1			T1	1378		T2	65907		T5	5050
values[0x0]	15928389	1			T1	589		T2	31280		T5	2451
values[0x1]	18703273	1			T1	723		T2	34085		T5	2499

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6902195	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62119408

1

T1

2552

T2

125349

T5

10000

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	282754	1			T1	105		T2	554		T5	29
valid_sources[0x01]	255958	1			T2	439		T5	45		T4	45
valid_sources[0x02]	276647	1			T2	504		T5	47		T4	20
valid_sources[0x03]	235665	1			T2	487		T5	36		T4	41
valid_sources[0x04]	249706	1			T2	542		T5	42		T4	34
valid_sources[0x05]	305050	1			T1	20		T2	570		T5	50
valid_sources[0x06]	395884	1			T2	439		T5	36		T4	38
valid_sources[0x07]	261664	1			T2	483		T5	32		T4	38
valid_sources[0x08]	236238	1			T2	526		T5	34		T4	37
valid_sources[0x09]	288201	1			T1	34		T2	502		T5	36
valid_sources[0x0a]	249948	1			T2	494		T5	40		T4	36
valid_sources[0x0b]	257120	1			T2	630		T5	43		T4	32
valid_sources[0x0c]	240393	1			T2	559		T5	32		T4	36
valid_sources[0x0d]	274838	1			T2	487		T5	40		T4	37
valid_sources[0x0e]	251442	1			T2	558		T5	47		T4	24
valid_sources[0x0f]	269279	1			T2	528		T5	52		T4	41
valid_sources[0x10]	243995	1			T2	510		T5	51		T4	31
valid_sources[0x11]	267780	1			T2	458		T5	34		T4	19
valid_sources[0x12]	272562	1			T2	467		T5	42		T4	38
valid_sources[0x13]	259561	1			T2	557		T5	39		T4	38
valid_sources[0x14]	280186	1			T2	455		T5	47		T4	38
valid_sources[0x15]	266007	1			T2	532		T5	53		T4	34
valid_sources[0x16]	241782	1			T1	77		T2	617		T5	47
valid_sources[0x17]	237481	1			T2	580		T5	48		T4	46
valid_sources[0x18]	248953	1			T2	506		T5	28		T4	26
valid_sources[0x19]	237086	1			T2	527		T5	29		T4	46
valid_sources[0x1a]	249417	1			T2	515		T5	18		T4	40
valid_sources[0x1b]	253963	1			T2	583		T5	31		T4	36
valid_sources[0x1c]	257314	1			T1	21		T2	550		T5	59
valid_sources[0x1d]	263122	1			T2	459		T5	34		T4	40
valid_sources[0x1e]	286195	1			T2	512		T5	40		T4	41
valid_sources[0x1f]	250926	1			T2	505		T5	33		T4	32
valid_sources[0x20]	334062	1			T2	551		T5	30		T4	34
valid_sources[0x21]	260989	1			T1	15		T2	468		T5	43
valid_sources[0x22]	249826	1			T2	539		T5	61		T4	37
valid_sources[0x23]	254022	1			T2	589		T5	27		T4	39
valid_sources[0x24]	239314	1			T2	624		T5	20		T4	39
valid_sources[0x25]	303519	1			T2	501		T5	38		T4	44
valid_sources[0x26]	235052	1			T2	585		T5	42		T4	34
valid_sources[0x27]	238205	1			T2	433		T5	66		T4	41
valid_sources[0x28]	264027	1			T2	542		T5	37		T4	44
valid_sources[0x29]	255089	1			T2	475		T5	60		T4	51
valid_sources[0x2a]	283371	1			T1	56		T2	546		T5	37
valid_sources[0x2b]	244002	1			T1	154		T2	465		T5	55
valid_sources[0x2c]	292121	1			T2	544		T5	27		T4	35
valid_sources[0x2d]	262984	1			T2	550		T5	32		T4	35
valid_sources[0x2e]	270599	1			T2	518		T5	47		T4	46
valid_sources[0x2f]	270162	1			T2	435		T5	40		T4	26
valid_sources[0x30]	266403	1			T1	29		T2	550		T5	32
valid_sources[0x31]	304070	1			T2	488		T5	53		T4	29
valid_sources[0x32]	256837	1			T1	54		T2	484		T5	39
valid_sources[0x33]	248529	1			T2	541		T5	25		T4	32
valid_sources[0x34]	273955	1			T2	573		T5	40		T4	50
valid_sources[0x35]	315923	1			T1	79		T2	521		T5	35
valid_sources[0x36]	251075	1			T2	597		T5	35		T4	37
valid_sources[0x37]	283788	1			T2	466		T5	30		T4	33
valid_sources[0x38]	261891	1			T2	608		T5	21		T4	42
valid_sources[0x39]	276318	1			T1	43		T2	569		T5	25
valid_sources[0x3a]	245513	1			T1	118		T2	520		T5	30
valid_sources[0x3b]	259894	1			T1	28		T2	526		T5	53
valid_sources[0x3c]	308942	1			T2	491		T5	30		T4	38
valid_sources[0x3d]	260399	1			T2	518		T5	56		T4	28
valid_sources[0x3e]	246037	1			T2	577		T5	42		T4	42
valid_sources[0x3f]	321597	1			T2	566		T5	45		T4	37
valid_sources[0x40]	244395	1			T2	500		T5	21		T4	32
valid_sources[0x41]	321835	1			T2	513		T5	46		T4	33
valid_sources[0x42]	296138	1			T1	104		T2	410		T5	40
valid_sources[0x43]	267253	1			T2	565		T5	27		T4	40
valid_sources[0x44]	284604	1			T2	410		T5	32		T4	34
valid_sources[0x45]	268091	1			T2	420		T5	21		T4	31
valid_sources[0x46]	355094	1			T2	461		T5	39		T4	43
valid_sources[0x47]	248227	1			T1	22		T2	523		T5	26
valid_sources[0x48]	313337	1			T1	21		T2	509		T5	31
valid_sources[0x49]	256986	1			T2	524		T5	44		T4	41
valid_sources[0x4a]	291193	1			T2	455		T5	74		T4	31
valid_sources[0x4b]	279858	1			T1	12		T2	544		T5	51
valid_sources[0x4c]	275663	1			T1	76		T2	472		T5	18
valid_sources[0x4d]	247698	1			T2	508		T5	36		T4	46
valid_sources[0x4e]	296300	1			T2	429		T5	55		T4	40
valid_sources[0x4f]	266402	1			T2	504		T5	63		T4	40
valid_sources[0x50]	235423	1			T1	73		T2	503		T5	27
valid_sources[0x51]	253188	1			T2	467		T5	60		T4	38
valid_sources[0x52]	277816	1			T2	502		T5	61		T4	29
valid_sources[0x53]	248604	1			T2	511		T5	53		T4	31
valid_sources[0x54]	250376	1			T2	454		T5	17		T4	26
valid_sources[0x55]	254942	1			T2	405		T5	47		T4	39
valid_sources[0x56]	242157	1			T2	435		T5	35		T4	35
valid_sources[0x57]	263981	1			T2	436		T5	29		T4	41
valid_sources[0x58]	303489	1			T2	501		T5	40		T4	26
valid_sources[0x59]	244730	1			T2	454		T5	48		T4	27
valid_sources[0x5a]	254945	1			T2	467		T5	49		T4	31
valid_sources[0x5b]	280719	1			T2	610		T5	20		T4	31
valid_sources[0x5c]	310209	1			T2	557		T5	52		T4	41
valid_sources[0x5d]	271185	1			T2	591		T5	22		T4	31
valid_sources[0x5e]	254973	1			T2	466		T5	43		T4	37
valid_sources[0x5f]	283286	1			T2	535		T5	38		T4	50
valid_sources[0x60]	249106	1			T2	446		T5	35		T4	49
valid_sources[0x61]	264378	1			T2	574		T5	29		T4	29
valid_sources[0x62]	287430	1			T1	49		T2	478		T5	30
valid_sources[0x63]	272045	1			T2	507		T5	60		T4	28
valid_sources[0x64]	318383	1			T2	519		T5	42		T4	38
valid_sources[0x65]	309071	1			T1	37		T2	539		T5	26
valid_sources[0x66]	268929	1			T2	496		T5	27		T4	37
valid_sources[0x67]	286268	1			T2	434		T5	45		T4	28
valid_sources[0x68]	275828	1			T2	514		T5	26		T4	36
valid_sources[0x69]	265321	1			T2	507		T5	36		T4	43
valid_sources[0x6a]	245691	1			T2	430		T5	39		T4	36
valid_sources[0x6b]	300493	1			T2	463		T5	50		T4	38
valid_sources[0x6c]	298326	1			T2	556		T5	43		T4	34
valid_sources[0x6d]	244203	1			T2	505		T5	33		T4	32
valid_sources[0x6e]	241324	1			T2	483		T5	41		T4	43
valid_sources[0x6f]	375997	1			T1	27		T2	440		T5	31
valid_sources[0x70]	250907	1			T2	457		T5	73		T4	35
valid_sources[0x71]	253484	1			T2	442		T5	52		T4	36
valid_sources[0x72]	251820	1			T2	464		T5	33		T4	45
valid_sources[0x73]	261054	1			T2	509		T5	26		T4	35
valid_sources[0x74]	240128	1			T2	536		T5	37		T4	37
valid_sources[0x75]	269800	1			T2	474		T5	27		T4	34
valid_sources[0x76]	254586	1			T2	469		T5	33		T4	29
valid_sources[0x77]	281255	1			T1	33		T2	493		T5	62
valid_sources[0x78]	249514	1			T2	465		T5	30		T4	31
valid_sources[0x79]	299886	1			T1	11		T2	443		T5	56
valid_sources[0x7a]	248593	1			T1	42		T2	599		T5	35
valid_sources[0x7b]	274989	1			T2	614		T5	41		T4	44
valid_sources[0x7c]	264449	1			T1	100		T2	544		T5	24
valid_sources[0x7d]	291450	1			T2	507		T5	33		T4	42
valid_sources[0x7e]	239569	1			T1	17		T2	469		T5	44
valid_sources[0x7f]	288089	1			T2	558		T5	43		T4	30
valid_sources[0x80]	286948	1			T1	61		T2	521		T5	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27465740

1

T1

1248

T2

59895

T5

5050

values[0x0]

all_enables

biggest_size

13849546

1

T1

547

T2

29566

T5

2451

values[0x1]

all_enables

biggest_size

13851887

1

T1

633

T2

29884

T5

2499

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37126	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

154208

1

T1

20

T2

16

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55079	1			T1	25		T2	12		T7	31
values[0x0]	65460	1			T1	17		T2	21		T3	4
values[0x1]	70795	1			T1	11		T2	22		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27697	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163637

1

T1

21

T2

16

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	744	1			T10	1		T28	1		T21	8
valid_sources[0x01]	861	1			T2	1		T9	1		T21	15
valid_sources[0x02]	514	1			T21	14		T16	24		T31	1
valid_sources[0x03]	966	1			T21	6		T16	24		T137	4
valid_sources[0x04]	643	1			T1	1		T7	2		T21	7
valid_sources[0x05]	902	1			T2	3		T9	1		T21	7
valid_sources[0x06]	519	1			T28	3		T21	18		T16	22
valid_sources[0x07]	757	1			T7	1		T21	10		T16	21
valid_sources[0x08]	461	1			T19	2		T21	17		T16	26
valid_sources[0x09]	638	1			T21	8		T16	18		T148	2
valid_sources[0x0a]	702	1			T9	1		T21	16		T16	23
valid_sources[0x0b]	730	1			T2	1		T21	10		T16	20
valid_sources[0x0c]	560	1			T2	1		T21	17		T16	9
valid_sources[0x0d]	756	1			T21	17		T16	19		T145	8
valid_sources[0x0e]	574	1			T21	17		T16	18		T149	2
valid_sources[0x0f]	744	1			T7	1		T9	1		T21	13
valid_sources[0x10]	741	1			T9	1		T21	21		T16	10
valid_sources[0x11]	853	1			T1	1		T21	14		T16	9
valid_sources[0x12]	741	1			T1	1		T7	1		T21	14
valid_sources[0x13]	579	1			T1	1		T2	2		T9	1
valid_sources[0x14]	474	1			T21	10		T16	18		T77	3
valid_sources[0x15]	839	1			T21	27		T16	18		T63	1
valid_sources[0x16]	670	1			T21	18		T16	20		T31	2
valid_sources[0x17]	549	1			T21	21		T16	11		T150	1
valid_sources[0x18]	590	1			T12	2		T9	1		T21	9
valid_sources[0x19]	974	1			T21	5		T16	19		T151	1
valid_sources[0x1a]	874	1			T9	3		T28	1		T21	11
valid_sources[0x1b]	578	1			T21	12		T16	16		T63	1
valid_sources[0x1c]	488	1			T7	1		T21	19		T16	18
valid_sources[0x1d]	536	1			T11	4		T21	15		T16	20
valid_sources[0x1e]	1034	1			T2	2		T21	4		T16	17
valid_sources[0x1f]	680	1			T11	1		T21	1		T16	15
valid_sources[0x20]	688	1			T7	1		T9	1		T21	12
valid_sources[0x21]	669	1			T7	2		T21	25		T16	11
valid_sources[0x22]	591	1			T11	2		T21	7		T16	18
valid_sources[0x23]	641	1			T1	2		T7	1		T20	1
valid_sources[0x24]	698	1			T1	1		T9	3		T21	12
valid_sources[0x25]	675	1			T21	30		T16	21		T152	1
valid_sources[0x26]	650	1			T7	2		T20	1		T21	5
valid_sources[0x27]	1159	1			T1	2		T21	8		T16	22
valid_sources[0x28]	902	1			T21	8		T16	13		T18	1
valid_sources[0x29]	789	1			T2	1		T7	2		T21	20
valid_sources[0x2a]	806	1			T21	6		T16	25		T77	2
valid_sources[0x2b]	636	1			T7	1		T21	3		T16	22
valid_sources[0x2c]	716	1			T7	5		T9	5		T21	16
valid_sources[0x2d]	1277	1			T21	18		T16	19		T145	2
valid_sources[0x2e]	586	1			T7	1		T21	26		T16	22
valid_sources[0x2f]	1002	1			T1	1		T21	4		T16	16
valid_sources[0x30]	1107	1			T21	11		T16	20		T33	12
valid_sources[0x31]	578	1			T1	2		T2	1		T21	17
valid_sources[0x32]	605	1			T2	1		T21	26		T16	15
valid_sources[0x33]	731	1			T7	1		T21	11		T16	15
valid_sources[0x34]	708	1			T28	1		T21	12		T16	21
valid_sources[0x35]	812	1			T7	4		T21	8		T16	15
valid_sources[0x36]	858	1			T21	18		T16	9		T145	11
valid_sources[0x37]	887	1			T21	4		T16	23		T49	2
valid_sources[0x38]	726	1			T6	3		T21	17		T16	12
valid_sources[0x39]	741	1			T21	14		T16	18		T149	1
valid_sources[0x3a]	696	1			T2	1		T21	13		T16	23
valid_sources[0x3b]	490	1			T21	25		T16	18		T153	1
valid_sources[0x3c]	674	1			T21	5		T16	20		T149	2
valid_sources[0x3d]	847	1			T7	1		T21	2		T16	16
valid_sources[0x3e]	671	1			T21	16		T16	17		T149	1
valid_sources[0x3f]	542	1			T1	1		T7	1		T21	16
valid_sources[0x40]	885	1			T1	1		T2	1		T21	15
valid_sources[0x41]	673	1			T7	2		T21	14		T16	26
valid_sources[0x42]	924	1			T2	2		T7	2		T21	14
valid_sources[0x43]	682	1			T6	9		T28	1		T21	8
valid_sources[0x44]	839	1			T7	2		T21	8		T16	30
valid_sources[0x45]	639	1			T28	2		T21	11		T16	12
valid_sources[0x46]	673	1			T7	2		T28	3		T21	16
valid_sources[0x47]	646	1			T7	1		T28	2		T21	27
valid_sources[0x48]	546	1			T21	6		T16	20		T77	2
valid_sources[0x49]	860	1			T2	1		T11	2		T7	2
valid_sources[0x4a]	567	1			T2	2		T21	19		T16	30
valid_sources[0x4b]	535	1			T20	1		T9	4		T28	1
valid_sources[0x4c]	907	1			T1	1		T21	9		T16	16
valid_sources[0x4d]	703	1			T21	12		T16	16		T63	1
valid_sources[0x4e]	499	1			T9	8		T21	14		T16	27
valid_sources[0x4f]	934	1			T9	2		T21	8		T16	25
valid_sources[0x50]	724	1			T7	1		T28	1		T21	19
valid_sources[0x51]	668	1			T21	4		T16	11		T132	2
valid_sources[0x52]	692	1			T7	1		T21	25		T16	16
valid_sources[0x53]	580	1			T1	2		T7	1		T21	6
valid_sources[0x54]	702	1			T21	23		T16	17		T150	1
valid_sources[0x55]	624	1			T28	1		T21	12		T16	26
valid_sources[0x56]	741	1			T21	14		T16	14		T134	1
valid_sources[0x57]	621	1			T1	1		T11	2		T21	37
valid_sources[0x58]	664	1			T21	12		T16	21		T132	1
valid_sources[0x59]	518	1			T1	1		T2	1		T21	22
valid_sources[0x5a]	484	1			T2	1		T11	2		T21	25
valid_sources[0x5b]	779	1			T2	1		T9	1		T21	31
valid_sources[0x5c]	822	1			T7	1		T21	19		T16	9
valid_sources[0x5d]	663	1			T7	3		T21	7		T16	23
valid_sources[0x5e]	590	1			T9	1		T21	24		T16	12
valid_sources[0x5f]	879	1			T2	1		T21	7		T16	26
valid_sources[0x60]	636	1			T1	2		T21	19		T16	19
valid_sources[0x61]	721	1			T7	2		T21	21		T16	21
valid_sources[0x62]	618	1			T1	1		T21	14		T16	12
valid_sources[0x63]	816	1			T7	2		T9	1		T21	9
valid_sources[0x64]	457	1			T1	1		T21	7		T16	11
valid_sources[0x65]	705	1			T11	3		T21	24		T16	12
valid_sources[0x66]	639	1			T7	2		T21	12		T16	17
valid_sources[0x67]	1082	1			T2	1		T23	69		T21	3
valid_sources[0x68]	723	1			T1	1		T2	1		T21	15
valid_sources[0x69]	586	1			T11	2		T21	22		T16	31
valid_sources[0x6a]	507	1			T2	1		T7	2		T21	11
valid_sources[0x6b]	621	1			T21	11		T16	23		T62	4
valid_sources[0x6c]	859	1			T21	17		T16	15		T77	1
valid_sources[0x6d]	774	1			T1	1		T21	25		T16	21
valid_sources[0x6e]	534	1			T11	5		T21	7		T16	25
valid_sources[0x6f]	726	1			T21	7		T16	22		T153	1
valid_sources[0x70]	969	1			T12	1		T21	4		T16	19
valid_sources[0x71]	928	1			T12	2		T7	3		T9	1
valid_sources[0x72]	725	1			T1	1		T21	6		T16	24
valid_sources[0x73]	1636	1			T19	1		T21	16		T16	21
valid_sources[0x74]	611	1			T1	2		T9	1		T21	8
valid_sources[0x75]	883	1			T21	13		T16	25		T62	8
valid_sources[0x76]	1085	1			T7	3		T21	19		T16	16
valid_sources[0x77]	522	1			T21	25		T16	19		T36	1
valid_sources[0x78]	721	1			T21	20		T16	19		T63	1
valid_sources[0x79]	1315	1			T11	2		T7	1		T28	1
valid_sources[0x7a]	771	1			T7	1		T21	12		T16	15
valid_sources[0x7b]	693	1			T12	3		T19	6		T21	14
valid_sources[0x7c]	877	1			T21	11		T16	18		T148	1
valid_sources[0x7d]	704	1			T21	12		T16	22		T63	1
valid_sources[0x7e]	514	1			T2	2		T11	1		T28	1
valid_sources[0x7f]	1157	1			T21	18		T16	17		T78	6
valid_sources[0x80]	718	1			T21	13		T16	21		T62	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41915

1

T1

12

T2

8

T7

17

values[0x0]

all_enables

biggest_size

57232

1

T1

7

T2

4

T5

1

values[0x1]

all_enables

biggest_size

55061

1

T1

1

T2

4

T3

1