Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
13630545 |
1 |
|
|
T1 |
85 |
|
T2 |
9501 |
|
T4 |
7568 |
full_word |
50636753 |
1 |
|
|
T1 |
808 |
|
T2 |
95410 |
|
T5 |
10000 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
64267008 |
1 |
|
|
T1 |
893 |
|
T2 |
104911 |
|
T5 |
10000 |
auto[TlIntgErrCmd] |
107 |
1 |
|
|
T54 |
1 |
|
T55 |
6 |
|
T56 |
7 |
auto[TlIntgErrData] |
92 |
1 |
|
|
T54 |
5 |
|
T55 |
3 |
|
T56 |
7 |
auto[TlIntgErrBoth] |
91 |
1 |
|
|
T54 |
4 |
|
T55 |
1 |
|
T56 |
6 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
29528187 |
1 |
|
|
T1 |
455 |
|
T2 |
39546 |
|
T5 |
5050 |
auto[1] |
34739111 |
1 |
|
|
T1 |
438 |
|
T2 |
65365 |
|
T5 |
4950 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
6523652 |
1 |
|
|
T1 |
44 |
|
T2 |
3586 |
|
T4 |
3762 |
auto[TlIntgErrNone] |
partial |
auto[1] |
7106625 |
1 |
|
|
T1 |
41 |
|
T2 |
5915 |
|
T4 |
3806 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
23004411 |
1 |
|
|
T1 |
411 |
|
T2 |
35960 |
|
T5 |
5050 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
27632320 |
1 |
|
|
T1 |
397 |
|
T2 |
59450 |
|
T5 |
4950 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
49 |
1 |
|
|
T54 |
1 |
|
T55 |
3 |
|
T56 |
4 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
54 |
1 |
|
|
T55 |
3 |
|
T56 |
3 |
|
T122 |
5 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
1 |
1 |
|
|
T128 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
3 |
1 |
|
|
T121 |
1 |
|
T129 |
1 |
|
T126 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
42 |
1 |
|
|
T54 |
1 |
|
T55 |
3 |
|
T56 |
3 |
auto[TlIntgErrData] |
partial |
auto[1] |
38 |
1 |
|
|
T54 |
3 |
|
T56 |
3 |
|
T122 |
7 |
auto[TlIntgErrData] |
full_word |
auto[0] |
3 |
1 |
|
|
T122 |
1 |
|
T125 |
1 |
|
T128 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
9 |
1 |
|
|
T54 |
1 |
|
T56 |
1 |
|
T123 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
28 |
1 |
|
|
T56 |
2 |
|
T122 |
1 |
|
T121 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
57 |
1 |
|
|
T54 |
4 |
|
T55 |
1 |
|
T56 |
3 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
1 |
1 |
|
|
T130 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
5 |
1 |
|
|
T56 |
1 |
|
T131 |
2 |
|
T126 |
1 |