Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	719601	1			T32	2990		T20	2581		T34	139
auto[1]	9794299	1			T1	386		T2	3863		T5	5049
auto[2]	580722	1			T32	2303		T20	1939		T34	101
auto[3]	9663462	1			T1	390		T2	3772		T5	4949

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13686398	1			T1	648		T2	6321		T5	9998
auto[1]	1941858	1			T1	60		T2	617		T4	3
auto[2]	1960096	1			T1	66		T2	620		T4	2
auto[3]	3169732	1			T1	2		T2	77		T4	27

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8200228

1

T1

774

T2

7625

T5

9990

auto[1]

12557856

1

T1

2

T2

10

T5

8

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	210399	1			T34	8		T8	18		T33	846
auto[0]	auto[0]	auto[1]	21653	1			T34	23		T8	1		T33	91
auto[0]	auto[0]	auto[2]	21471	1			T34	16		T8	1		T33	75
auto[0]	auto[0]	auto[3]	5672	1			T32	1		T34	92		T33	15
auto[0]	auto[1]	auto[0]	3172803	1			T1	324		T2	3222		T5	5047
auto[0]	auto[1]	auto[1]	323680	1			T1	22		T2	310		T4	1
auto[0]	auto[1]	auto[2]	318934	1			T1	37		T2	287		T11	3607
auto[0]	auto[1]	auto[3]	63186	1			T1	1		T2	39		T4	12
auto[0]	auto[2]	auto[0]	176312	1			T8	17		T33	754		T62	3550
auto[0]	auto[2]	auto[1]	18082	1			T8	2		T33	83		T62	361
auto[0]	auto[2]	auto[2]	21275	1			T34	18		T8	1		T33	63
auto[0]	auto[2]	auto[3]	4771	1			T34	83		T33	7		T17	8
auto[0]	auto[3]	auto[0]	3137515	1			T1	323		T2	3090		T5	4943
auto[0]	auto[3]	auto[1]	315799	1			T1	37		T2	306		T4	2
auto[0]	auto[3]	auto[2]	324091	1			T1	29		T2	333		T4	2
auto[0]	auto[3]	auto[3]	64585	1			T1	1		T2	38		T4	15
auto[1]	auto[0]	auto[0]	15246	1			T32	100		T20	87		T33	1
auto[1]	auto[0]	auto[1]	68209	1			T32	432		T20	371		T139	3
auto[1]	auto[0]	auto[2]	68504	1			T32	432		T20	381		T140	1
auto[1]	auto[0]	auto[3]	308447	1			T32	2025		T20	1742		T139	2
auto[1]	auto[1]	auto[0]	3483418	1			T1	1		T2	5		T5	2
auto[1]	auto[1]	auto[1]	598125	1			T1	1		T11	9		T32	1419
auto[1]	auto[1]	auto[2]	565116	1			T11	1		T7	3		T32	840
auto[1]	auto[1]	auto[3]	1269037	1			T32	6233		T20	5223		T19	1
auto[1]	auto[2]	auto[0]	11270	1			T33	4		T62	2		T141	15
auto[1]	auto[2]	auto[1]	49567	1			T141	1		T142	3781		T143	1
auto[1]	auto[2]	auto[2]	54166	1			T32	408		T20	328		T144	1
auto[1]	auto[2]	auto[3]	245279	1			T32	1895		T20	1611		T141	1
auto[1]	auto[3]	auto[0]	3479435	1			T2	4		T5	6		T11	34
auto[1]	auto[3]	auto[1]	546743	1			T2	1		T11	4		T7	2
auto[1]	auto[3]	auto[2]	586539	1			T11	3		T7	5		T32	1366
auto[1]	auto[3]	auto[3]	1208755	1			T32	6113		T20	5105		T97	775