Module Definition
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Module : sram_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sram_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 302346402 233439 0 0
ctrl_regwen_rd_A 302346402 3782 0 0
exec_rd_A 302346402 3399 0 0
exec_regwen_rd_A 302346402 4020 0 0
readback_rd_A 302346402 2348 0 0
readback_regwen_rd_A 302346402 2051 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 302346402 233439 0 0
T16 237576 8457 0 0
T21 123316 6453 0 0
T22 0 1160 0 0
T24 2048 0 0 0
T25 2641 0 0 0
T29 3892 0 0 0
T30 4320 0 0 0
T31 319248 0 0 0
T34 38676 0 0 0
T38 0 6242 0 0
T39 0 5015 0 0
T49 7859 0 0 0
T50 13533 0 0 0
T51 0 5291 0 0
T53 0 8116 0 0
T59 0 7869 0 0
T60 0 8945 0 0
T61 0 938 0 0

ctrl_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 302346402 3782 0 0
T14 9239 0 0 0
T22 64205 40 0 0
T47 16945 0 0 0
T61 0 31 0 0
T82 5957 0 0 0
T102 14538 0 0 0
T108 0 343 0 0
T109 0 346 0 0
T110 0 124 0 0
T111 0 98 0 0
T112 0 168 0 0
T113 0 209 0 0
T114 0 318 0 0
T115 0 222 0 0
T116 184677 0 0 0
T117 135609 0 0 0
T118 7309 0 0 0
T119 12905 0 0 0
T120 170804 0 0 0

exec_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 302346402 3399 0 0
T14 9239 0 0 0
T22 64205 47 0 0
T47 16945 0 0 0
T61 0 60 0 0
T82 5957 0 0 0
T102 14538 0 0 0
T108 0 331 0 0
T109 0 388 0 0
T110 0 53 0 0
T111 0 110 0 0
T112 0 165 0 0
T113 0 187 0 0
T114 0 261 0 0
T115 0 187 0 0
T116 184677 0 0 0
T117 135609 0 0 0
T118 7309 0 0 0
T119 12905 0 0 0
T120 170804 0 0 0

exec_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 302346402 4020 0 0
T14 9239 0 0 0
T22 64205 35 0 0
T47 16945 0 0 0
T61 0 67 0 0
T82 5957 0 0 0
T102 14538 0 0 0
T108 0 455 0 0
T109 0 346 0 0
T110 0 87 0 0
T111 0 111 0 0
T112 0 194 0 0
T113 0 264 0 0
T114 0 368 0 0
T115 0 256 0 0
T116 184677 0 0 0
T117 135609 0 0 0
T118 7309 0 0 0
T119 12905 0 0 0
T120 170804 0 0 0

readback_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 302346402 2348 0 0
T14 9239 0 0 0
T22 64205 45 0 0
T47 16945 0 0 0
T61 0 50 0 0
T82 5957 0 0 0
T102 14538 0 0 0
T108 0 400 0 0
T109 0 283 0 0
T110 0 31 0 0
T111 0 78 0 0
T112 0 128 0 0
T113 0 187 0 0
T114 0 299 0 0
T115 0 255 0 0
T116 184677 0 0 0
T117 135609 0 0 0
T118 7309 0 0 0
T119 12905 0 0 0
T120 170804 0 0 0

readback_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 302346402 2051 0 0
T14 9239 0 0 0
T22 64205 51 0 0
T47 16945 0 0 0
T61 0 56 0 0
T82 5957 0 0 0
T102 14538 0 0 0
T108 0 335 0 0
T109 0 305 0 0
T110 0 49 0 0
T111 0 62 0 0
T112 0 108 0 0
T113 0 174 0 0
T114 0 323 0 0
T115 0 111 0 0
T116 184677 0 0 0
T117 135609 0 0 0
T118 7309 0 0 0
T119 12905 0 0 0
T120 170804 0 0 0

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