SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1782 | 1782 | 0 | 0 |
OutputsKnown_A | 602047688 | 601798020 | 0 | 0 |
gen_flops.OutputDelay_A | 301023844 | 300886273 | 0 | 2673 |
gen_no_flops.OutputDelay_A | 301023844 | 300899010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1782 | 1782 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
T11 | 2 | 2 | 0 | 0 |
T12 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 602047688 | 601798020 | 0 | 0 |
T1 | 74606 | 74156 | 0 | 0 |
T2 | 392592 | 392462 | 0 | 0 |
T3 | 2806 | 2686 | 0 | 0 |
T4 | 56758 | 56628 | 0 | 0 |
T5 | 27710 | 27580 | 0 | 0 |
T6 | 676132 | 675952 | 0 | 0 |
T7 | 1229996 | 1223514 | 0 | 0 |
T10 | 5450 | 5330 | 0 | 0 |
T11 | 751762 | 751636 | 0 | 0 |
T12 | 2732 | 2620 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 301023844 | 300886273 | 0 | 2673 |
T1 | 37303 | 37000 | 0 | 3 |
T2 | 196296 | 196228 | 0 | 3 |
T3 | 1403 | 1340 | 0 | 3 |
T4 | 28379 | 28311 | 0 | 3 |
T5 | 13855 | 13787 | 0 | 3 |
T6 | 338066 | 337973 | 0 | 3 |
T7 | 614998 | 611655 | 0 | 3 |
T10 | 2725 | 2662 | 0 | 3 |
T11 | 375881 | 375815 | 0 | 3 |
T12 | 1366 | 1307 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 301023844 | 300899010 | 0 | 0 |
T1 | 37303 | 37078 | 0 | 0 |
T2 | 196296 | 196231 | 0 | 0 |
T3 | 1403 | 1343 | 0 | 0 |
T4 | 28379 | 28314 | 0 | 0 |
T5 | 13855 | 13790 | 0 | 0 |
T6 | 338066 | 337976 | 0 | 0 |
T7 | 614998 | 611757 | 0 | 0 |
T10 | 2725 | 2665 | 0 | 0 |
T11 | 375881 | 375818 | 0 | 0 |
T12 | 1366 | 1310 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 891 | 891 | 0 | 0 |
OutputsKnown_A | 301023844 | 300899010 | 0 | 0 |
gen_flops.OutputDelay_A | 301023844 | 300886273 | 0 | 2673 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 891 | 891 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 301023844 | 300899010 | 0 | 0 |
T1 | 37303 | 37078 | 0 | 0 |
T2 | 196296 | 196231 | 0 | 0 |
T3 | 1403 | 1343 | 0 | 0 |
T4 | 28379 | 28314 | 0 | 0 |
T5 | 13855 | 13790 | 0 | 0 |
T6 | 338066 | 337976 | 0 | 0 |
T7 | 614998 | 611757 | 0 | 0 |
T10 | 2725 | 2665 | 0 | 0 |
T11 | 375881 | 375818 | 0 | 0 |
T12 | 1366 | 1310 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 301023844 | 300886273 | 0 | 2673 |
T1 | 37303 | 37000 | 0 | 3 |
T2 | 196296 | 196228 | 0 | 3 |
T3 | 1403 | 1340 | 0 | 3 |
T4 | 28379 | 28311 | 0 | 3 |
T5 | 13855 | 13787 | 0 | 3 |
T6 | 338066 | 337973 | 0 | 3 |
T7 | 614998 | 611655 | 0 | 3 |
T10 | 2725 | 2662 | 0 | 3 |
T11 | 375881 | 375815 | 0 | 3 |
T12 | 1366 | 1307 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 891 | 891 | 0 | 0 |
OutputsKnown_A | 301023844 | 300899010 | 0 | 0 |
gen_no_flops.OutputDelay_A | 301023844 | 300899010 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 891 | 891 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 301023844 | 300899010 | 0 | 0 |
T1 | 37303 | 37078 | 0 | 0 |
T2 | 196296 | 196231 | 0 | 0 |
T3 | 1403 | 1343 | 0 | 0 |
T4 | 28379 | 28314 | 0 | 0 |
T5 | 13855 | 13790 | 0 | 0 |
T6 | 338066 | 337976 | 0 | 0 |
T7 | 614998 | 611757 | 0 | 0 |
T10 | 2725 | 2665 | 0 | 0 |
T11 | 375881 | 375818 | 0 | 0 |
T12 | 1366 | 1310 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 301023844 | 300899010 | 0 | 0 |
T1 | 37303 | 37078 | 0 | 0 |
T2 | 196296 | 196231 | 0 | 0 |
T3 | 1403 | 1343 | 0 | 0 |
T4 | 28379 | 28314 | 0 | 0 |
T5 | 13855 | 13790 | 0 | 0 |
T6 | 338066 | 337976 | 0 | 0 |
T7 | 614998 | 611757 | 0 | 0 |
T10 | 2725 | 2665 | 0 | 0 |
T11 | 375881 | 375818 | 0 | 0 |
T12 | 1366 | 1310 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |