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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1024
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T795 /workspace/coverage/default/15.sram_ctrl_mem_walk.3445541530 Jun 27 06:27:16 PM PDT 24 Jun 27 06:27:37 PM PDT 24 76871882 ps
T796 /workspace/coverage/default/30.sram_ctrl_bijection.3686828933 Jun 27 06:27:40 PM PDT 24 Jun 27 06:28:51 PM PDT 24 3466275220 ps
T797 /workspace/coverage/default/44.sram_ctrl_ram_cfg.609888672 Jun 27 06:28:56 PM PDT 24 Jun 27 06:29:00 PM PDT 24 27288549 ps
T798 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1731720448 Jun 27 06:27:41 PM PDT 24 Jun 27 06:28:08 PM PDT 24 276705662 ps
T799 /workspace/coverage/default/48.sram_ctrl_smoke.3313296605 Jun 27 06:29:27 PM PDT 24 Jun 27 06:29:31 PM PDT 24 29603374 ps
T800 /workspace/coverage/default/17.sram_ctrl_regwen.923037951 Jun 27 06:27:15 PM PDT 24 Jun 27 06:42:41 PM PDT 24 11547892137 ps
T801 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.214112956 Jun 27 06:27:19 PM PDT 24 Jun 27 06:29:03 PM PDT 24 134437270 ps
T802 /workspace/coverage/default/26.sram_ctrl_regwen.782050361 Jun 27 06:27:40 PM PDT 24 Jun 27 06:34:10 PM PDT 24 16599597331 ps
T803 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1391206129 Jun 27 06:26:30 PM PDT 24 Jun 27 06:32:41 PM PDT 24 3504069291 ps
T804 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2229331384 Jun 27 06:28:42 PM PDT 24 Jun 27 06:33:34 PM PDT 24 1041566421 ps
T805 /workspace/coverage/default/48.sram_ctrl_max_throughput.1006759528 Jun 27 06:29:43 PM PDT 24 Jun 27 06:30:26 PM PDT 24 98809692 ps
T806 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3040811147 Jun 27 06:27:40 PM PDT 24 Jun 27 06:30:07 PM PDT 24 1502468035 ps
T807 /workspace/coverage/default/31.sram_ctrl_lc_escalation.3362372892 Jun 27 06:27:57 PM PDT 24 Jun 27 06:28:23 PM PDT 24 1864518832 ps
T808 /workspace/coverage/default/20.sram_ctrl_regwen.1679496276 Jun 27 06:27:34 PM PDT 24 Jun 27 06:36:51 PM PDT 24 15395825730 ps
T809 /workspace/coverage/default/25.sram_ctrl_bijection.2709994313 Jun 27 06:27:40 PM PDT 24 Jun 27 06:28:42 PM PDT 24 12862063456 ps
T810 /workspace/coverage/default/32.sram_ctrl_partial_access.3925377780 Jun 27 06:27:59 PM PDT 24 Jun 27 06:28:17 PM PDT 24 346109516 ps
T811 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2031980438 Jun 27 06:29:21 PM PDT 24 Jun 27 06:29:27 PM PDT 24 361669058 ps
T812 /workspace/coverage/default/40.sram_ctrl_stress_all.4197190133 Jun 27 06:28:45 PM PDT 24 Jun 27 06:54:15 PM PDT 24 43474345523 ps
T813 /workspace/coverage/default/12.sram_ctrl_executable.3547678495 Jun 27 06:27:07 PM PDT 24 Jun 27 06:28:27 PM PDT 24 5528889717 ps
T814 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1860067361 Jun 27 06:28:10 PM PDT 24 Jun 27 06:35:23 PM PDT 24 17748947086 ps
T815 /workspace/coverage/default/12.sram_ctrl_partial_access.2249690998 Jun 27 06:27:05 PM PDT 24 Jun 27 06:27:35 PM PDT 24 106104479 ps
T816 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4280194847 Jun 27 06:27:58 PM PDT 24 Jun 27 06:32:55 PM PDT 24 21920836324 ps
T817 /workspace/coverage/default/25.sram_ctrl_executable.2872642179 Jun 27 06:27:39 PM PDT 24 Jun 27 06:37:19 PM PDT 24 100670218866 ps
T818 /workspace/coverage/default/46.sram_ctrl_smoke.526848516 Jun 27 06:29:22 PM PDT 24 Jun 27 06:29:40 PM PDT 24 245859662 ps
T819 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2575029448 Jun 27 06:29:25 PM PDT 24 Jun 27 06:29:53 PM PDT 24 1445650663 ps
T820 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3598533576 Jun 27 06:26:36 PM PDT 24 Jun 27 06:36:13 PM PDT 24 3248302538 ps
T821 /workspace/coverage/default/35.sram_ctrl_executable.824682815 Jun 27 06:28:10 PM PDT 24 Jun 27 06:40:33 PM PDT 24 1780628087 ps
T822 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3680416261 Jun 27 06:27:00 PM PDT 24 Jun 27 06:27:39 PM PDT 24 1173179906 ps
T823 /workspace/coverage/default/22.sram_ctrl_ram_cfg.2347550670 Jun 27 06:27:23 PM PDT 24 Jun 27 06:27:42 PM PDT 24 28075630 ps
T824 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3097277740 Jun 27 06:27:28 PM PDT 24 Jun 27 06:27:52 PM PDT 24 65833673 ps
T825 /workspace/coverage/default/34.sram_ctrl_max_throughput.1285499164 Jun 27 06:28:10 PM PDT 24 Jun 27 06:29:11 PM PDT 24 114181793 ps
T826 /workspace/coverage/default/24.sram_ctrl_bijection.3458245528 Jun 27 06:27:40 PM PDT 24 Jun 27 06:28:57 PM PDT 24 5793323544 ps
T827 /workspace/coverage/default/19.sram_ctrl_smoke.3590348917 Jun 27 06:27:25 PM PDT 24 Jun 27 06:28:40 PM PDT 24 201145313 ps
T828 /workspace/coverage/default/20.sram_ctrl_bijection.629429025 Jun 27 06:27:28 PM PDT 24 Jun 27 06:28:29 PM PDT 24 1990335080 ps
T829 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2942651571 Jun 27 06:28:41 PM PDT 24 Jun 27 06:33:28 PM PDT 24 5855517746 ps
T830 /workspace/coverage/default/8.sram_ctrl_mem_walk.2972499625 Jun 27 06:27:01 PM PDT 24 Jun 27 06:27:12 PM PDT 24 1157457044 ps
T831 /workspace/coverage/default/13.sram_ctrl_bijection.3702353845 Jun 27 06:27:02 PM PDT 24 Jun 27 06:27:49 PM PDT 24 3294355082 ps
T832 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.4030259694 Jun 27 06:28:43 PM PDT 24 Jun 27 06:44:19 PM PDT 24 3712192935 ps
T833 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.4155056718 Jun 27 06:27:21 PM PDT 24 Jun 27 06:30:38 PM PDT 24 7980944398 ps
T834 /workspace/coverage/default/43.sram_ctrl_multiple_keys.725368615 Jun 27 06:28:56 PM PDT 24 Jun 27 06:37:36 PM PDT 24 21712124318 ps
T835 /workspace/coverage/default/9.sram_ctrl_multiple_keys.3213618134 Jun 27 06:27:00 PM PDT 24 Jun 27 06:31:10 PM PDT 24 46243900532 ps
T836 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1739907961 Jun 27 06:29:40 PM PDT 24 Jun 27 06:31:00 PM PDT 24 1217358320 ps
T837 /workspace/coverage/default/38.sram_ctrl_regwen.1147305817 Jun 27 06:28:45 PM PDT 24 Jun 27 06:31:48 PM PDT 24 7501574373 ps
T838 /workspace/coverage/default/33.sram_ctrl_partial_access.3456113426 Jun 27 06:27:57 PM PDT 24 Jun 27 06:28:23 PM PDT 24 213009537 ps
T839 /workspace/coverage/default/9.sram_ctrl_ram_cfg.1458052157 Jun 27 06:27:01 PM PDT 24 Jun 27 06:27:07 PM PDT 24 122928844 ps
T840 /workspace/coverage/default/34.sram_ctrl_ram_cfg.1041326975 Jun 27 06:28:10 PM PDT 24 Jun 27 06:28:23 PM PDT 24 44382100 ps
T841 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1146797634 Jun 27 06:29:20 PM PDT 24 Jun 27 06:29:24 PM PDT 24 124540884 ps
T842 /workspace/coverage/default/7.sram_ctrl_multiple_keys.1713552395 Jun 27 06:26:48 PM PDT 24 Jun 27 06:44:54 PM PDT 24 38114742158 ps
T843 /workspace/coverage/default/49.sram_ctrl_executable.2870558054 Jun 27 06:29:42 PM PDT 24 Jun 27 06:39:59 PM PDT 24 30941938648 ps
T844 /workspace/coverage/default/40.sram_ctrl_multiple_keys.1372008063 Jun 27 06:28:46 PM PDT 24 Jun 27 06:42:57 PM PDT 24 28545221897 ps
T845 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3007159572 Jun 27 06:27:40 PM PDT 24 Jun 27 06:32:38 PM PDT 24 1431014184 ps
T846 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.4105297596 Jun 27 06:27:23 PM PDT 24 Jun 27 06:31:30 PM PDT 24 750617882 ps
T847 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.222786285 Jun 27 06:26:43 PM PDT 24 Jun 27 06:35:27 PM PDT 24 78909303499 ps
T848 /workspace/coverage/default/1.sram_ctrl_ram_cfg.2551624138 Jun 27 06:26:33 PM PDT 24 Jun 27 06:26:39 PM PDT 24 32907852 ps
T849 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2421422213 Jun 27 06:26:54 PM PDT 24 Jun 27 06:36:30 PM PDT 24 4785553867 ps
T850 /workspace/coverage/default/42.sram_ctrl_executable.1657221729 Jun 27 06:28:56 PM PDT 24 Jun 27 06:49:59 PM PDT 24 161691982409 ps
T851 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4183485034 Jun 27 06:28:42 PM PDT 24 Jun 27 06:35:36 PM PDT 24 126860653222 ps
T852 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3431025457 Jun 27 06:29:03 PM PDT 24 Jun 27 06:34:15 PM PDT 24 33394330972 ps
T853 /workspace/coverage/default/45.sram_ctrl_partial_access.816664041 Jun 27 06:29:22 PM PDT 24 Jun 27 06:31:37 PM PDT 24 6148526883 ps
T854 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2245208837 Jun 27 06:27:24 PM PDT 24 Jun 27 06:35:41 PM PDT 24 27178020403 ps
T855 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.4170260766 Jun 27 06:27:39 PM PDT 24 Jun 27 06:27:58 PM PDT 24 91205687 ps
T856 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1133114186 Jun 27 06:27:15 PM PDT 24 Jun 27 06:48:46 PM PDT 24 9031725139 ps
T857 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2306801896 Jun 27 06:28:58 PM PDT 24 Jun 27 06:36:47 PM PDT 24 8512404850 ps
T858 /workspace/coverage/default/26.sram_ctrl_bijection.329284931 Jun 27 06:27:41 PM PDT 24 Jun 27 06:28:23 PM PDT 24 828321326 ps
T859 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1204419733 Jun 27 06:26:28 PM PDT 24 Jun 27 06:31:07 PM PDT 24 1202692906 ps
T860 /workspace/coverage/default/40.sram_ctrl_executable.1726059881 Jun 27 06:28:46 PM PDT 24 Jun 27 07:04:09 PM PDT 24 21188056889 ps
T861 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2692238676 Jun 27 06:28:09 PM PDT 24 Jun 27 06:28:26 PM PDT 24 903570877 ps
T862 /workspace/coverage/default/16.sram_ctrl_regwen.1995744564 Jun 27 06:27:24 PM PDT 24 Jun 27 06:47:43 PM PDT 24 61409745752 ps
T863 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2775577645 Jun 27 06:28:44 PM PDT 24 Jun 27 06:28:51 PM PDT 24 108439477 ps
T864 /workspace/coverage/default/22.sram_ctrl_stress_all.1163381564 Jun 27 06:27:28 PM PDT 24 Jun 27 06:30:49 PM PDT 24 22808785866 ps
T865 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2451997854 Jun 27 06:27:33 PM PDT 24 Jun 27 06:38:05 PM PDT 24 22651686489 ps
T866 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3383371709 Jun 27 06:28:26 PM PDT 24 Jun 27 06:29:09 PM PDT 24 115566732 ps
T867 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1706573736 Jun 27 06:28:28 PM PDT 24 Jun 27 06:43:30 PM PDT 24 22444226039 ps
T868 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2420884986 Jun 27 06:29:25 PM PDT 24 Jun 27 06:47:14 PM PDT 24 44578813555 ps
T869 /workspace/coverage/default/34.sram_ctrl_regwen.30067400 Jun 27 06:28:09 PM PDT 24 Jun 27 06:29:23 PM PDT 24 594129718 ps
T870 /workspace/coverage/default/20.sram_ctrl_lc_escalation.2079745681 Jun 27 06:27:21 PM PDT 24 Jun 27 06:27:44 PM PDT 24 348342517 ps
T871 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2727439496 Jun 27 06:27:38 PM PDT 24 Jun 27 06:33:18 PM PDT 24 26918300419 ps
T872 /workspace/coverage/default/31.sram_ctrl_executable.4195651609 Jun 27 06:27:54 PM PDT 24 Jun 27 06:42:36 PM PDT 24 9883906197 ps
T873 /workspace/coverage/default/32.sram_ctrl_bijection.3463706728 Jun 27 06:27:56 PM PDT 24 Jun 27 06:29:08 PM PDT 24 14603046300 ps
T874 /workspace/coverage/default/21.sram_ctrl_lc_escalation.4216797623 Jun 27 06:27:24 PM PDT 24 Jun 27 06:27:50 PM PDT 24 600693116 ps
T875 /workspace/coverage/default/3.sram_ctrl_regwen.2648415014 Jun 27 06:26:36 PM PDT 24 Jun 27 06:44:38 PM PDT 24 7011132337 ps
T876 /workspace/coverage/default/2.sram_ctrl_mem_walk.1235664786 Jun 27 06:26:32 PM PDT 24 Jun 27 06:26:47 PM PDT 24 467007227 ps
T877 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3571603832 Jun 27 06:27:34 PM PDT 24 Jun 27 06:37:13 PM PDT 24 138365060192 ps
T878 /workspace/coverage/default/40.sram_ctrl_bijection.3027135913 Jun 27 06:28:43 PM PDT 24 Jun 27 06:29:22 PM PDT 24 1727275673 ps
T879 /workspace/coverage/default/42.sram_ctrl_mem_walk.2828691622 Jun 27 06:29:00 PM PDT 24 Jun 27 06:29:08 PM PDT 24 282021007 ps
T880 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.924360996 Jun 27 06:28:07 PM PDT 24 Jun 27 06:33:20 PM PDT 24 34457525275 ps
T881 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.123341378 Jun 27 06:26:58 PM PDT 24 Jun 27 06:33:52 PM PDT 24 10961914229 ps
T882 /workspace/coverage/default/26.sram_ctrl_max_throughput.2650660185 Jun 27 06:27:28 PM PDT 24 Jun 27 06:29:02 PM PDT 24 239724163 ps
T883 /workspace/coverage/default/41.sram_ctrl_partial_access.1227684237 Jun 27 06:28:43 PM PDT 24 Jun 27 06:28:59 PM PDT 24 2433285441 ps
T884 /workspace/coverage/default/14.sram_ctrl_smoke.2133994712 Jun 27 06:27:04 PM PDT 24 Jun 27 06:27:17 PM PDT 24 455226979 ps
T885 /workspace/coverage/default/14.sram_ctrl_multiple_keys.1276776643 Jun 27 06:27:02 PM PDT 24 Jun 27 06:42:51 PM PDT 24 7013308549 ps
T886 /workspace/coverage/default/9.sram_ctrl_smoke.1581466862 Jun 27 06:27:01 PM PDT 24 Jun 27 06:27:12 PM PDT 24 164510032 ps
T887 /workspace/coverage/default/8.sram_ctrl_multiple_keys.555716177 Jun 27 06:27:00 PM PDT 24 Jun 27 06:43:42 PM PDT 24 15440069027 ps
T888 /workspace/coverage/default/44.sram_ctrl_mem_walk.484974844 Jun 27 06:28:57 PM PDT 24 Jun 27 06:29:06 PM PDT 24 700928576 ps
T889 /workspace/coverage/default/14.sram_ctrl_alert_test.2963799861 Jun 27 06:27:17 PM PDT 24 Jun 27 06:27:34 PM PDT 24 14335522 ps
T890 /workspace/coverage/default/40.sram_ctrl_lc_escalation.1320480823 Jun 27 06:28:40 PM PDT 24 Jun 27 06:28:44 PM PDT 24 135438585 ps
T891 /workspace/coverage/default/24.sram_ctrl_multiple_keys.1000570361 Jun 27 06:27:28 PM PDT 24 Jun 27 06:28:40 PM PDT 24 1020695572 ps
T892 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2918616260 Jun 27 06:26:38 PM PDT 24 Jun 27 06:26:46 PM PDT 24 418369098 ps
T893 /workspace/coverage/default/27.sram_ctrl_bijection.1323340336 Jun 27 06:27:41 PM PDT 24 Jun 27 06:28:54 PM PDT 24 3467041819 ps
T894 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3016809657 Jun 27 06:28:11 PM PDT 24 Jun 27 06:36:13 PM PDT 24 4816272742 ps
T895 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1327832595 Jun 27 06:27:25 PM PDT 24 Jun 27 06:28:17 PM PDT 24 96280926 ps
T896 /workspace/coverage/default/25.sram_ctrl_lc_escalation.2066122710 Jun 27 06:27:41 PM PDT 24 Jun 27 06:28:04 PM PDT 24 502580600 ps
T897 /workspace/coverage/default/29.sram_ctrl_partial_access.842470243 Jun 27 06:27:50 PM PDT 24 Jun 27 06:28:26 PM PDT 24 2243061519 ps
T898 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3666357029 Jun 27 06:27:24 PM PDT 24 Jun 27 06:33:06 PM PDT 24 27459731192 ps
T899 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2995222015 Jun 27 06:28:13 PM PDT 24 Jun 27 06:28:25 PM PDT 24 42750647 ps
T900 /workspace/coverage/default/24.sram_ctrl_alert_test.2446152515 Jun 27 06:27:40 PM PDT 24 Jun 27 06:27:57 PM PDT 24 88019776 ps
T901 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1150878790 Jun 27 06:28:40 PM PDT 24 Jun 27 06:41:40 PM PDT 24 5686318223 ps
T902 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1151170091 Jun 27 06:28:10 PM PDT 24 Jun 27 06:34:07 PM PDT 24 14523418292 ps
T903 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2622435 Jun 27 06:28:31 PM PDT 24 Jun 27 06:29:15 PM PDT 24 1135050736 ps
T904 /workspace/coverage/default/9.sram_ctrl_stress_all.33302053 Jun 27 06:27:01 PM PDT 24 Jun 27 07:40:02 PM PDT 24 280789381588 ps
T905 /workspace/coverage/default/47.sram_ctrl_max_throughput.2604525260 Jun 27 06:29:19 PM PDT 24 Jun 27 06:30:51 PM PDT 24 448573977 ps
T906 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3277963780 Jun 27 06:27:18 PM PDT 24 Jun 27 06:50:57 PM PDT 24 5196148249 ps
T907 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3266957751 Jun 27 06:27:42 PM PDT 24 Jun 27 06:28:01 PM PDT 24 883043284 ps
T908 /workspace/coverage/default/5.sram_ctrl_executable.2396800985 Jun 27 06:26:36 PM PDT 24 Jun 27 06:40:45 PM PDT 24 14632667528 ps
T909 /workspace/coverage/default/24.sram_ctrl_stress_all.1165720610 Jun 27 06:27:26 PM PDT 24 Jun 27 07:35:32 PM PDT 24 24006829291 ps
T27 /workspace/coverage/default/1.sram_ctrl_sec_cm.1520330818 Jun 27 06:26:31 PM PDT 24 Jun 27 06:26:39 PM PDT 24 407697286 ps
T910 /workspace/coverage/default/31.sram_ctrl_smoke.2849511102 Jun 27 06:27:50 PM PDT 24 Jun 27 06:28:20 PM PDT 24 2902365722 ps
T911 /workspace/coverage/default/48.sram_ctrl_ram_cfg.3218560725 Jun 27 06:29:41 PM PDT 24 Jun 27 06:29:45 PM PDT 24 32634238 ps
T912 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.873972514 Jun 27 06:26:32 PM PDT 24 Jun 27 06:33:50 PM PDT 24 18657301115 ps
T913 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2298551065 Jun 27 06:27:24 PM PDT 24 Jun 27 06:32:40 PM PDT 24 9053777908 ps
T914 /workspace/coverage/default/25.sram_ctrl_smoke.2425269862 Jun 27 06:27:26 PM PDT 24 Jun 27 06:27:50 PM PDT 24 89143933 ps
T915 /workspace/coverage/default/36.sram_ctrl_lc_escalation.310949428 Jun 27 06:28:27 PM PDT 24 Jun 27 06:28:34 PM PDT 24 1245783992 ps
T916 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2505556036 Jun 27 06:27:05 PM PDT 24 Jun 27 06:33:09 PM PDT 24 9533451099 ps
T917 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2034758114 Jun 27 06:27:58 PM PDT 24 Jun 27 06:29:38 PM PDT 24 197489967 ps
T918 /workspace/coverage/default/12.sram_ctrl_max_throughput.2349573543 Jun 27 06:27:02 PM PDT 24 Jun 27 06:27:18 PM PDT 24 66537766 ps
T919 /workspace/coverage/default/23.sram_ctrl_partial_access.110082941 Jun 27 06:27:22 PM PDT 24 Jun 27 06:28:21 PM PDT 24 278738410 ps
T920 /workspace/coverage/default/17.sram_ctrl_stress_all.3203017248 Jun 27 06:27:18 PM PDT 24 Jun 27 07:09:16 PM PDT 24 219737721703 ps
T921 /workspace/coverage/default/30.sram_ctrl_multiple_keys.760151836 Jun 27 06:27:45 PM PDT 24 Jun 27 06:31:14 PM PDT 24 13786576853 ps
T922 /workspace/coverage/default/30.sram_ctrl_mem_walk.1233632933 Jun 27 06:27:44 PM PDT 24 Jun 27 06:28:06 PM PDT 24 79611435 ps
T923 /workspace/coverage/default/45.sram_ctrl_bijection.783691514 Jun 27 06:29:20 PM PDT 24 Jun 27 06:29:57 PM PDT 24 2069446329 ps
T924 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.522974754 Jun 27 06:27:04 PM PDT 24 Jun 27 06:31:38 PM PDT 24 70214253499 ps
T925 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3950747128 Jun 27 06:27:56 PM PDT 24 Jun 27 06:29:44 PM PDT 24 769291445 ps
T926 /workspace/coverage/default/33.sram_ctrl_executable.2766593560 Jun 27 06:28:08 PM PDT 24 Jun 27 06:44:36 PM PDT 24 10181735852 ps
T927 /workspace/coverage/default/19.sram_ctrl_bijection.2567338506 Jun 27 06:27:23 PM PDT 24 Jun 27 06:28:22 PM PDT 24 5993924796 ps
T928 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3932118346 Jun 27 06:29:24 PM PDT 24 Jun 27 06:33:04 PM PDT 24 2554741442 ps
T929 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2691008515 Jun 27 06:27:22 PM PDT 24 Jun 27 06:28:38 PM PDT 24 503254782 ps
T930 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3251472101 Jun 27 06:28:11 PM PDT 24 Jun 27 06:28:28 PM PDT 24 1238901871 ps
T931 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3391306291 Jun 27 06:27:16 PM PDT 24 Jun 27 06:30:19 PM PDT 24 7583702968 ps
T932 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.171533388 Jun 27 06:29:25 PM PDT 24 Jun 27 06:33:11 PM PDT 24 2342490423 ps
T933 /workspace/coverage/default/4.sram_ctrl_multiple_keys.103268944 Jun 27 06:26:36 PM PDT 24 Jun 27 06:45:51 PM PDT 24 13376732163 ps
T934 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.742269349 Jun 27 06:27:21 PM PDT 24 Jun 27 06:31:14 PM PDT 24 520075416 ps
T57 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4141632486 Jun 27 06:25:52 PM PDT 24 Jun 27 06:25:59 PM PDT 24 207596171 ps
T58 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.594329511 Jun 27 06:25:43 PM PDT 24 Jun 27 06:25:47 PM PDT 24 23746016 ps
T54 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.62936416 Jun 27 06:25:43 PM PDT 24 Jun 27 06:25:49 PM PDT 24 404988150 ps
T935 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1110892608 Jun 27 06:25:54 PM PDT 24 Jun 27 06:26:01 PM PDT 24 125265576 ps
T936 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1655671933 Jun 27 06:25:50 PM PDT 24 Jun 27 06:25:57 PM PDT 24 241013084 ps
T55 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2861462953 Jun 27 06:25:59 PM PDT 24 Jun 27 06:26:06 PM PDT 24 138769436 ps
T937 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2812967450 Jun 27 06:25:35 PM PDT 24 Jun 27 06:25:44 PM PDT 24 527350651 ps
T104 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2508172191 Jun 27 06:25:50 PM PDT 24 Jun 27 06:25:55 PM PDT 24 46921713 ps
T105 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1722640384 Jun 27 06:25:32 PM PDT 24 Jun 27 06:25:38 PM PDT 24 14733243 ps
T94 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2940165108 Jun 27 06:25:44 PM PDT 24 Jun 27 06:25:48 PM PDT 24 13988824 ps
T64 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4039873661 Jun 27 06:25:48 PM PDT 24 Jun 27 06:25:53 PM PDT 24 163723569 ps
T56 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3808453087 Jun 27 06:25:48 PM PDT 24 Jun 27 06:25:53 PM PDT 24 692904543 ps
T938 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3568529207 Jun 27 06:25:54 PM PDT 24 Jun 27 06:26:02 PM PDT 24 52034339 ps
T939 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3891257015 Jun 27 06:25:36 PM PDT 24 Jun 27 06:25:42 PM PDT 24 28581953 ps
T95 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2799670352 Jun 27 06:25:55 PM PDT 24 Jun 27 06:26:03 PM PDT 24 393510272 ps
T122 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4141742394 Jun 27 06:25:53 PM PDT 24 Jun 27 06:26:01 PM PDT 24 276136081 ps
T65 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.310330947 Jun 27 06:25:42 PM PDT 24 Jun 27 06:25:47 PM PDT 24 38204978 ps
T66 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.289919609 Jun 27 06:25:50 PM PDT 24 Jun 27 06:25:56 PM PDT 24 1006338457 ps
T130 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3622985212 Jun 27 06:25:57 PM PDT 24 Jun 27 06:26:05 PM PDT 24 143932719 ps
T106 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3218278387 Jun 27 06:25:42 PM PDT 24 Jun 27 06:25:47 PM PDT 24 11636739 ps
T107 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.485270996 Jun 27 06:25:50 PM PDT 24 Jun 27 06:25:56 PM PDT 24 73086657 ps
T940 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.56914670 Jun 27 06:25:39 PM PDT 24 Jun 27 06:25:47 PM PDT 24 920335094 ps
T96 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3657363348 Jun 27 06:25:53 PM PDT 24 Jun 27 06:25:59 PM PDT 24 20021107 ps
T67 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1242475662 Jun 27 06:25:36 PM PDT 24 Jun 27 06:25:42 PM PDT 24 13051543 ps
T68 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1488941666 Jun 27 06:25:54 PM PDT 24 Jun 27 06:26:03 PM PDT 24 971869831 ps
T941 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.301934216 Jun 27 06:26:02 PM PDT 24 Jun 27 06:26:08 PM PDT 24 199037113 ps
T121 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1218540769 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:57 PM PDT 24 120872250 ps
T942 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2924390424 Jun 27 06:25:35 PM PDT 24 Jun 27 06:25:46 PM PDT 24 673930699 ps
T943 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1500689962 Jun 27 06:25:47 PM PDT 24 Jun 27 06:25:50 PM PDT 24 49965365 ps
T69 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3300171612 Jun 27 06:25:58 PM PDT 24 Jun 27 06:26:04 PM PDT 24 57716022 ps
T70 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.463676646 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:57 PM PDT 24 39753389 ps
T944 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.288941416 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:57 PM PDT 24 66806717 ps
T71 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1508363315 Jun 27 06:25:50 PM PDT 24 Jun 27 06:25:55 PM PDT 24 13991366 ps
T945 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1588862790 Jun 27 06:25:43 PM PDT 24 Jun 27 06:25:48 PM PDT 24 159542515 ps
T946 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2024903229 Jun 27 06:25:42 PM PDT 24 Jun 27 06:25:51 PM PDT 24 277567205 ps
T947 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.551708646 Jun 27 06:25:40 PM PDT 24 Jun 27 06:25:46 PM PDT 24 20994280 ps
T72 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3621780773 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:59 PM PDT 24 654744241 ps
T948 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1729637064 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:56 PM PDT 24 324201998 ps
T949 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3452816580 Jun 27 06:25:44 PM PDT 24 Jun 27 06:25:48 PM PDT 24 64137905 ps
T950 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1330404897 Jun 27 06:25:36 PM PDT 24 Jun 27 06:25:43 PM PDT 24 93454734 ps
T951 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3935901108 Jun 27 06:26:00 PM PDT 24 Jun 27 06:26:07 PM PDT 24 64261891 ps
T952 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.339064213 Jun 27 06:25:53 PM PDT 24 Jun 27 06:26:01 PM PDT 24 613468264 ps
T953 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.126579864 Jun 27 06:25:52 PM PDT 24 Jun 27 06:26:01 PM PDT 24 1783232813 ps
T954 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.743633026 Jun 27 06:25:32 PM PDT 24 Jun 27 06:25:39 PM PDT 24 102141784 ps
T955 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3123803902 Jun 27 06:25:50 PM PDT 24 Jun 27 06:25:58 PM PDT 24 459417491 ps
T956 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1212364266 Jun 27 06:25:43 PM PDT 24 Jun 27 06:25:51 PM PDT 24 139037236 ps
T957 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1140065207 Jun 27 06:25:52 PM PDT 24 Jun 27 06:25:58 PM PDT 24 27130695 ps
T73 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3266295441 Jun 27 06:25:56 PM PDT 24 Jun 27 06:26:05 PM PDT 24 4082337263 ps
T958 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1317726981 Jun 27 06:25:36 PM PDT 24 Jun 27 06:25:42 PM PDT 24 19920970 ps
T959 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.909108598 Jun 27 06:25:59 PM PDT 24 Jun 27 06:26:09 PM PDT 24 869673324 ps
T960 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4259054944 Jun 27 06:25:50 PM PDT 24 Jun 27 06:25:57 PM PDT 24 909803893 ps
T74 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1544492712 Jun 27 06:25:49 PM PDT 24 Jun 27 06:25:53 PM PDT 24 45525797 ps
T961 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.921035632 Jun 27 06:25:52 PM PDT 24 Jun 27 06:26:03 PM PDT 24 573474864 ps
T962 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1983516002 Jun 27 06:25:35 PM PDT 24 Jun 27 06:25:42 PM PDT 24 18259979 ps
T963 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.142124527 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:58 PM PDT 24 205781478 ps
T75 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.290043483 Jun 27 06:25:47 PM PDT 24 Jun 27 06:25:50 PM PDT 24 37927280 ps
T964 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3590961206 Jun 27 06:25:34 PM PDT 24 Jun 27 06:25:41 PM PDT 24 118069042 ps
T76 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1218359928 Jun 27 06:26:01 PM PDT 24 Jun 27 06:26:08 PM PDT 24 240242693 ps
T965 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2173658503 Jun 27 06:25:36 PM PDT 24 Jun 27 06:25:43 PM PDT 24 137066700 ps
T966 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.82928025 Jun 27 06:25:36 PM PDT 24 Jun 27 06:25:43 PM PDT 24 28508499 ps
T967 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2094490475 Jun 27 06:25:54 PM PDT 24 Jun 27 06:26:09 PM PDT 24 325520079 ps
T968 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2564282180 Jun 27 06:25:35 PM PDT 24 Jun 27 06:25:43 PM PDT 24 116148173 ps
T123 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3115124113 Jun 27 06:25:41 PM PDT 24 Jun 27 06:25:48 PM PDT 24 436270825 ps
T969 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1194479530 Jun 27 06:25:43 PM PDT 24 Jun 27 06:25:49 PM PDT 24 148486534 ps
T970 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1245537676 Jun 27 06:25:52 PM PDT 24 Jun 27 06:26:01 PM PDT 24 96004552 ps
T971 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.852194396 Jun 27 06:25:48 PM PDT 24 Jun 27 06:25:53 PM PDT 24 42917460 ps
T972 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2196327569 Jun 27 06:26:01 PM PDT 24 Jun 27 06:26:07 PM PDT 24 105177477 ps
T973 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.560983975 Jun 27 06:25:54 PM PDT 24 Jun 27 06:26:04 PM PDT 24 559442409 ps
T974 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3520197293 Jun 27 06:26:01 PM PDT 24 Jun 27 06:26:12 PM PDT 24 67908235 ps
T975 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1102741276 Jun 27 06:25:49 PM PDT 24 Jun 27 06:25:56 PM PDT 24 131665697 ps
T87 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.973299070 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:59 PM PDT 24 377208143 ps
T976 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2881489542 Jun 27 06:26:01 PM PDT 24 Jun 27 06:26:07 PM PDT 24 15970222 ps
T92 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2219958782 Jun 27 06:25:58 PM PDT 24 Jun 27 06:26:04 PM PDT 24 39004087 ps
T977 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3949791365 Jun 27 06:25:52 PM PDT 24 Jun 27 06:26:00 PM PDT 24 522847781 ps
T978 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1542338671 Jun 27 06:25:37 PM PDT 24 Jun 27 06:25:44 PM PDT 24 15712893 ps
T979 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3440766887 Jun 27 06:25:50 PM PDT 24 Jun 27 06:25:58 PM PDT 24 591752660 ps
T980 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2387475656 Jun 27 06:25:35 PM PDT 24 Jun 27 06:25:41 PM PDT 24 31695079 ps
T981 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.989797881 Jun 27 06:26:01 PM PDT 24 Jun 27 06:26:07 PM PDT 24 34813457 ps
T88 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3750453630 Jun 27 06:25:53 PM PDT 24 Jun 27 06:26:01 PM PDT 24 244583992 ps
T982 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2507020839 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:57 PM PDT 24 26095878 ps
T983 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2391985181 Jun 27 06:25:41 PM PDT 24 Jun 27 06:25:46 PM PDT 24 25040943 ps
T984 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2609860785 Jun 27 06:25:54 PM PDT 24 Jun 27 06:26:01 PM PDT 24 28438967 ps
T985 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3594671466 Jun 27 06:25:34 PM PDT 24 Jun 27 06:25:44 PM PDT 24 276482082 ps
T986 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1384273313 Jun 27 06:25:49 PM PDT 24 Jun 27 06:25:56 PM PDT 24 122739964 ps
T987 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1253747340 Jun 27 06:26:05 PM PDT 24 Jun 27 06:26:12 PM PDT 24 110605888 ps
T125 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1001913418 Jun 27 06:25:52 PM PDT 24 Jun 27 06:25:59 PM PDT 24 131208611 ps
T988 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1977714765 Jun 27 06:25:52 PM PDT 24 Jun 27 06:25:58 PM PDT 24 22170823 ps
T131 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3622623713 Jun 27 06:25:52 PM PDT 24 Jun 27 06:26:00 PM PDT 24 153933221 ps
T89 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1344214230 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:59 PM PDT 24 1590740653 ps
T90 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.737511110 Jun 27 06:25:53 PM PDT 24 Jun 27 06:26:02 PM PDT 24 1542241955 ps
T989 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1702322601 Jun 27 06:25:53 PM PDT 24 Jun 27 06:26:00 PM PDT 24 18566264 ps
T990 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3014885629 Jun 27 06:26:01 PM PDT 24 Jun 27 06:26:07 PM PDT 24 20576604 ps
T991 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1436060276 Jun 27 06:25:56 PM PDT 24 Jun 27 06:26:03 PM PDT 24 28219626 ps
T91 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3644144128 Jun 27 06:25:52 PM PDT 24 Jun 27 06:25:58 PM PDT 24 66831117 ps
T992 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2032017848 Jun 27 06:25:47 PM PDT 24 Jun 27 06:25:50 PM PDT 24 166953229 ps
T993 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2976869896 Jun 27 06:25:52 PM PDT 24 Jun 27 06:25:59 PM PDT 24 29937577 ps
T994 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.163683335 Jun 27 06:25:40 PM PDT 24 Jun 27 06:25:46 PM PDT 24 21542581 ps
T995 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3992847672 Jun 27 06:25:49 PM PDT 24 Jun 27 06:25:53 PM PDT 24 13512254 ps
T996 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1956998125 Jun 27 06:25:35 PM PDT 24 Jun 27 06:25:43 PM PDT 24 83013284 ps
T997 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3577710334 Jun 27 06:25:48 PM PDT 24 Jun 27 06:25:52 PM PDT 24 112991768 ps
T93 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3589736040 Jun 27 06:25:49 PM PDT 24 Jun 27 06:25:53 PM PDT 24 28020176 ps
T998 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.4193452038 Jun 27 06:26:01 PM PDT 24 Jun 27 06:26:09 PM PDT 24 402466299 ps
T999 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1296627555 Jun 27 06:25:34 PM PDT 24 Jun 27 06:25:41 PM PDT 24 41007237 ps
T1000 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1202682151 Jun 27 06:25:40 PM PDT 24 Jun 27 06:25:48 PM PDT 24 924403025 ps
T1001 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1296818050 Jun 27 06:25:52 PM PDT 24 Jun 27 06:25:59 PM PDT 24 453841031 ps
T1002 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3652664703 Jun 27 06:25:42 PM PDT 24 Jun 27 06:25:48 PM PDT 24 197623731 ps
T1003 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1186639120 Jun 27 06:25:56 PM PDT 24 Jun 27 06:26:03 PM PDT 24 18117970 ps
T1004 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.892949479 Jun 27 06:25:51 PM PDT 24 Jun 27 06:25:57 PM PDT 24 17539474 ps
T1005 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3457171531 Jun 27 06:25:35 PM PDT 24 Jun 27 06:25:43 PM PDT 24 859711859 ps
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