Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14201357	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59986436

1

T1

45056

T2

6142

T3

276799

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36989625	1			T1	22528		T2	2048		T3	152327
values[0x0]	17174781	1			T1	11265		T2	2028		T3	73308
values[0x1]	20023387	1			T1	11263		T2	2066		T3	78879

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7073906	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67113887

1

T1

45056

T2

6142

T3

290628

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	292754	1			T1	135		T2	29		T3	841
valid_sources[0x01]	275588	1			T1	173		T2	30		T3	434
valid_sources[0x02]	280848	1			T1	228		T2	22		T3	458
valid_sources[0x03]	289758	1			T1	172		T2	4		T3	134
valid_sources[0x04]	270985	1			T1	205		T2	27		T3	87
valid_sources[0x05]	291469	1			T1	186		T2	31		T3	10412
valid_sources[0x06]	254173	1			T1	136		T2	28		T3	680
valid_sources[0x07]	246976	1			T1	188		T2	18		T3	478
valid_sources[0x08]	271682	1			T1	178		T2	20		T3	312
valid_sources[0x09]	285658	1			T1	194		T2	29		T3	565
valid_sources[0x0a]	255182	1			T1	180		T2	20		T3	237
valid_sources[0x0b]	294192	1			T1	180		T2	21		T3	700
valid_sources[0x0c]	329048	1			T1	150		T2	11		T3	319
valid_sources[0x0d]	306680	1			T1	183		T2	17		T3	500
valid_sources[0x0e]	256667	1			T1	193		T2	25		T3	792
valid_sources[0x0f]	266857	1			T1	188		T2	16		T3	722
valid_sources[0x10]	288642	1			T1	178		T2	19		T3	308
valid_sources[0x11]	311802	1			T1	142		T2	33		T3	1068
valid_sources[0x12]	332105	1			T1	149		T2	37		T3	996
valid_sources[0x13]	281793	1			T1	167		T2	18		T3	361
valid_sources[0x14]	256167	1			T1	228		T2	12		T3	451
valid_sources[0x15]	292426	1			T1	124		T2	29		T3	393
valid_sources[0x16]	251347	1			T1	157		T2	14		T3	232
valid_sources[0x17]	288658	1			T1	152		T2	25		T3	837
valid_sources[0x18]	258236	1			T1	238		T2	29		T3	425
valid_sources[0x19]	272387	1			T1	188		T2	13		T3	520
valid_sources[0x1a]	271869	1			T1	175		T2	30		T3	581
valid_sources[0x1b]	300409	1			T1	160		T2	22		T3	1179
valid_sources[0x1c]	248689	1			T1	210		T2	35		T3	1224
valid_sources[0x1d]	339606	1			T1	183		T2	27		T3	479
valid_sources[0x1e]	254787	1			T1	161		T2	19		T3	555
valid_sources[0x1f]	263358	1			T1	177		T2	32		T3	517
valid_sources[0x20]	336977	1			T1	140		T2	24		T3	459
valid_sources[0x21]	259856	1			T1	132		T2	21		T3	247
valid_sources[0x22]	246041	1			T1	161		T2	40		T3	152
valid_sources[0x23]	284449	1			T1	168		T2	26		T3	277
valid_sources[0x24]	271145	1			T1	201		T2	22		T3	554
valid_sources[0x25]	259633	1			T1	134		T2	51		T3	290
valid_sources[0x26]	266754	1			T1	160		T2	18		T3	354
valid_sources[0x27]	291144	1			T1	155		T2	32		T3	374
valid_sources[0x28]	285400	1			T1	187		T2	29		T3	438
valid_sources[0x29]	353552	1			T1	149		T2	16		T3	346
valid_sources[0x2a]	350697	1			T1	132		T2	30		T3	650
valid_sources[0x2b]	270717	1			T1	173		T2	33		T3	943
valid_sources[0x2c]	269361	1			T1	170		T2	17		T3	651
valid_sources[0x2d]	413627	1			T1	202		T2	54		T3	532
valid_sources[0x2e]	292633	1			T1	194		T2	16		T3	579
valid_sources[0x2f]	307714	1			T1	188		T2	15		T3	588
valid_sources[0x30]	329001	1			T1	205		T2	25		T3	326
valid_sources[0x31]	280254	1			T1	220		T2	32		T3	543
valid_sources[0x32]	272200	1			T1	152		T2	20		T3	353
valid_sources[0x33]	294137	1			T1	227		T2	6		T3	271
valid_sources[0x34]	308467	1			T1	173		T2	44		T3	468
valid_sources[0x35]	251118	1			T1	167		T2	19		T3	437
valid_sources[0x36]	288433	1			T1	154		T2	53		T3	773
valid_sources[0x37]	280416	1			T1	179		T2	20		T3	555
valid_sources[0x38]	279744	1			T1	193		T2	14		T3	945
valid_sources[0x39]	318690	1			T1	117		T2	21		T3	536
valid_sources[0x3a]	261426	1			T1	160		T2	16		T3	739
valid_sources[0x3b]	277169	1			T1	153		T2	24		T3	587
valid_sources[0x3c]	246600	1			T1	130		T2	31		T3	476
valid_sources[0x3d]	273785	1			T1	135		T2	15		T3	175
valid_sources[0x3e]	323119	1			T1	142		T2	16		T3	1033
valid_sources[0x3f]	285552	1			T1	125		T2	17		T3	518
valid_sources[0x40]	329106	1			T1	113		T2	33		T3	487
valid_sources[0x41]	351210	1			T1	168		T2	22		T3	398
valid_sources[0x42]	297578	1			T1	129		T2	26		T3	947
valid_sources[0x43]	310435	1			T1	170		T2	19		T3	378
valid_sources[0x44]	317717	1			T1	153		T2	10		T3	880
valid_sources[0x45]	264651	1			T1	203		T2	39		T3	708
valid_sources[0x46]	329294	1			T1	227		T2	26		T3	694
valid_sources[0x47]	286934	1			T1	175		T2	37		T3	399
valid_sources[0x48]	280978	1			T1	184		T2	36		T3	474
valid_sources[0x49]	262530	1			T1	184		T2	29		T3	21001
valid_sources[0x4a]	267876	1			T1	209		T2	21		T3	503
valid_sources[0x4b]	273464	1			T1	145		T2	43		T3	593
valid_sources[0x4c]	270938	1			T1	140		T2	13		T3	504
valid_sources[0x4d]	257337	1			T1	186		T2	27		T3	320
valid_sources[0x4e]	255420	1			T1	191		T2	18		T3	937
valid_sources[0x4f]	280496	1			T1	160		T2	19		T3	633
valid_sources[0x50]	263893	1			T1	170		T2	11		T3	782
valid_sources[0x51]	280295	1			T1	172		T2	16		T3	488
valid_sources[0x52]	248753	1			T1	180		T2	21		T3	754
valid_sources[0x53]	292809	1			T1	163		T2	16		T3	534
valid_sources[0x54]	254752	1			T1	239		T2	25		T3	585
valid_sources[0x55]	279539	1			T1	198		T2	17		T3	714
valid_sources[0x56]	296757	1			T1	171		T2	26		T3	519
valid_sources[0x57]	278308	1			T1	200		T2	32		T3	511
valid_sources[0x58]	270406	1			T1	193		T2	27		T3	698
valid_sources[0x59]	284620	1			T1	201		T2	6		T3	929
valid_sources[0x5a]	279212	1			T1	169		T2	33		T3	307
valid_sources[0x5b]	269972	1			T1	165		T2	26		T3	413
valid_sources[0x5c]	281986	1			T1	215		T2	27		T3	781
valid_sources[0x5d]	262681	1			T1	167		T2	18		T3	1002
valid_sources[0x5e]	271677	1			T1	149		T2	22		T3	899
valid_sources[0x5f]	315784	1			T1	181		T2	48		T3	769
valid_sources[0x60]	488926	1			T1	166		T2	31		T3	332
valid_sources[0x61]	264108	1			T1	211		T2	21		T3	1133
valid_sources[0x62]	379127	1			T1	188		T2	30		T3	730
valid_sources[0x63]	302706	1			T1	192		T2	52		T3	483
valid_sources[0x64]	354964	1			T1	162		T2	13		T3	717
valid_sources[0x65]	301467	1			T1	212		T2	27		T3	450
valid_sources[0x66]	264838	1			T1	158		T2	23		T3	609
valid_sources[0x67]	312344	1			T1	131		T2	31		T3	799
valid_sources[0x68]	246321	1			T1	188		T2	46		T3	356
valid_sources[0x69]	305906	1			T1	200		T2	29		T3	394
valid_sources[0x6a]	279417	1			T1	153		T2	42		T3	634
valid_sources[0x6b]	296625	1			T1	184		T2	18		T3	228
valid_sources[0x6c]	274260	1			T1	158		T2	14		T3	354
valid_sources[0x6d]	305900	1			T1	263		T2	14		T3	930
valid_sources[0x6e]	274183	1			T1	176		T2	27		T3	484
valid_sources[0x6f]	260688	1			T1	179		T2	29		T3	224
valid_sources[0x70]	291975	1			T1	232		T2	21		T3	814
valid_sources[0x71]	248021	1			T1	187		T2	30		T3	875
valid_sources[0x72]	290979	1			T1	191		T2	16		T3	750
valid_sources[0x73]	356231	1			T1	213		T2	17		T3	445
valid_sources[0x74]	366104	1			T1	230		T2	20		T3	821
valid_sources[0x75]	339713	1			T1	178		T2	10		T3	351
valid_sources[0x76]	314143	1			T1	209		T2	18		T3	8863
valid_sources[0x77]	301995	1			T1	135		T2	24		T3	1386
valid_sources[0x78]	273673	1			T1	146		T2	37		T3	685
valid_sources[0x79]	287807	1			T1	170		T2	45		T3	314
valid_sources[0x7a]	244448	1			T1	146		T2	32		T3	437
valid_sources[0x7b]	331420	1			T1	190		T2	21		T3	392
valid_sources[0x7c]	319569	1			T1	155		T2	23		T3	444
valid_sources[0x7d]	287636	1			T1	189		T2	38		T3	158
valid_sources[0x7e]	366597	1			T1	194		T2	42		T3	397
valid_sources[0x7f]	267264	1			T1	192		T2	25		T3	524
valid_sources[0x80]	293465	1			T1	165		T2	11		T3	318

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29889959

1

T1

22528

T2

2048

T3

138470

values[0x0]

all_enables

biggest_size

15046447

1

T1

11265

T2

2028

T3

69114

values[0x1]

all_enables

biggest_size

15050030

1

T1

11263

T2

2066

T3

69215

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153973

1

T1

5

T2

4

T3

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55472	1			T3	48		T6	83		T22	19
values[0x0]	65845	1			T1	10		T2	6		T3	41
values[0x1]	70637	1			T1	12		T2	3		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28698	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163256

1

T1

8

T2

5

T3

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	602	1			T7	1		T26	1		T27	9
valid_sources[0x01]	815	1			T6	4		T26	1		T27	8
valid_sources[0x02]	707	1			T6	5		T24	1		T26	1
valid_sources[0x03]	693	1			T3	1		T26	3		T27	9
valid_sources[0x04]	764	1			T3	1		T6	4		T22	1
valid_sources[0x05]	860	1			T22	1		T26	5		T27	10
valid_sources[0x06]	915	1			T3	2		T26	6		T27	1
valid_sources[0x07]	570	1			T3	4		T6	3		T26	2
valid_sources[0x08]	725	1			T26	6		T27	5		T28	9
valid_sources[0x09]	591	1			T26	2		T27	5		T41	1
valid_sources[0x0a]	659	1			T3	1		T26	1		T27	7
valid_sources[0x0b]	654	1			T3	1		T6	2		T7	1
valid_sources[0x0c]	890	1			T26	2		T27	3		T28	8
valid_sources[0x0d]	771	1			T6	2		T22	1		T7	1
valid_sources[0x0e]	743	1			T22	2		T26	4		T27	2
valid_sources[0x0f]	729	1			T6	7		T26	1		T27	7
valid_sources[0x10]	765	1			T3	2		T6	3		T26	2
valid_sources[0x11]	633	1			T44	1		T26	3		T27	3
valid_sources[0x12]	1078	1			T6	2		T7	2		T26	12
valid_sources[0x13]	684	1			T3	1		T6	3		T27	5
valid_sources[0x14]	762	1			T6	3		T27	9		T45	1
valid_sources[0x15]	813	1			T3	1		T6	1		T26	4
valid_sources[0x16]	881	1			T6	7		T22	3		T26	12
valid_sources[0x17]	849	1			T3	1		T6	1		T26	1
valid_sources[0x18]	714	1			T5	1		T6	5		T12	1
valid_sources[0x19]	755	1			T3	3		T6	2		T26	4
valid_sources[0x1a]	779	1			T26	1		T27	7		T28	13
valid_sources[0x1b]	632	1			T26	3		T27	3		T28	14
valid_sources[0x1c]	580	1			T27	5		T28	19		T133	1
valid_sources[0x1d]	745	1			T6	1		T43	2		T7	1
valid_sources[0x1e]	906	1			T7	1		T26	20		T27	5
valid_sources[0x1f]	856	1			T27	4		T28	6		T134	2
valid_sources[0x20]	664	1			T6	2		T22	2		T26	6
valid_sources[0x21]	710	1			T6	1		T7	1		T26	3
valid_sources[0x22]	848	1			T3	2		T6	9		T27	6
valid_sources[0x23]	751	1			T2	1		T26	2		T27	2
valid_sources[0x24]	605	1			T6	2		T7	1		T26	9
valid_sources[0x25]	703	1			T6	2		T27	2		T28	6
valid_sources[0x26]	861	1			T2	1		T3	4		T6	2
valid_sources[0x27]	877	1			T3	1		T22	1		T7	1
valid_sources[0x28]	924	1			T6	2		T26	1		T27	3
valid_sources[0x29]	865	1			T6	2		T22	1		T44	1
valid_sources[0x2a]	675	1			T6	2		T22	1		T7	1
valid_sources[0x2b]	635	1			T6	1		T26	5		T27	1
valid_sources[0x2c]	747	1			T1	1		T3	1		T6	1
valid_sources[0x2d]	702	1			T1	1		T3	1		T6	1
valid_sources[0x2e]	797	1			T6	2		T22	5		T7	1
valid_sources[0x2f]	597	1			T27	8		T28	4		T133	1
valid_sources[0x30]	706	1			T3	1		T7	1		T26	1
valid_sources[0x31]	994	1			T6	2		T22	1		T7	1
valid_sources[0x32]	764	1			T3	3		T6	4		T27	1
valid_sources[0x33]	739	1			T6	3		T26	6		T27	1
valid_sources[0x34]	520	1			T3	1		T6	2		T7	1
valid_sources[0x35]	796	1			T3	1		T6	2		T27	5
valid_sources[0x36]	651	1			T2	1		T6	2		T24	1
valid_sources[0x37]	810	1			T42	2		T7	1		T26	3
valid_sources[0x38]	944	1			T26	1		T27	2		T28	19
valid_sources[0x39]	604	1			T3	3		T26	12		T27	8
valid_sources[0x3a]	895	1			T23	2		T22	1		T26	2
valid_sources[0x3b]	764	1			T3	1		T6	1		T27	5
valid_sources[0x3c]	844	1			T6	4		T26	1		T27	5
valid_sources[0x3d]	628	1			T7	1		T27	6		T28	16
valid_sources[0x3e]	705	1			T6	4		T25	1		T26	1
valid_sources[0x3f]	1130	1			T3	1		T4	1		T6	3
valid_sources[0x40]	1127	1			T11	2		T6	2		T22	2
valid_sources[0x41]	575	1			T3	1		T27	7		T28	9
valid_sources[0x42]	873	1			T3	2		T26	4		T27	6
valid_sources[0x43]	674	1			T3	2		T6	4		T27	5
valid_sources[0x44]	879	1			T3	1		T22	1		T7	1
valid_sources[0x45]	791	1			T3	1		T26	5		T27	7
valid_sources[0x46]	724	1			T44	1		T26	4		T27	3
valid_sources[0x47]	714	1			T2	1		T26	2		T28	30
valid_sources[0x48]	688	1			T6	1		T7	1		T27	9
valid_sources[0x49]	1017	1			T26	1		T27	14		T28	7
valid_sources[0x4a]	1051	1			T6	3		T7	1		T27	8
valid_sources[0x4b]	543	1			T11	2		T22	1		T26	2
valid_sources[0x4c]	728	1			T26	4		T27	8		T100	1
valid_sources[0x4d]	637	1			T26	3		T27	6		T28	12
valid_sources[0x4e]	554	1			T6	5		T26	4		T27	5
valid_sources[0x4f]	613	1			T6	2		T26	4		T27	3
valid_sources[0x50]	560	1			T6	5		T27	5		T28	10
valid_sources[0x51]	515	1			T22	4		T53	1		T26	9
valid_sources[0x52]	1011	1			T26	2		T27	4		T28	12
valid_sources[0x53]	688	1			T3	2		T6	1		T22	1
valid_sources[0x54]	770	1			T22	1		T26	1		T27	3
valid_sources[0x55]	911	1			T3	1		T26	6		T27	6
valid_sources[0x56]	647	1			T3	2		T6	2		T27	5
valid_sources[0x57]	758	1			T26	2		T27	3		T28	7
valid_sources[0x58]	811	1			T10	1		T6	3		T22	1
valid_sources[0x59]	726	1			T26	2		T27	9		T28	6
valid_sources[0x5a]	799	1			T3	1		T6	2		T7	1
valid_sources[0x5b]	781	1			T26	1		T27	3		T28	6
valid_sources[0x5c]	782	1			T3	1		T6	3		T22	2
valid_sources[0x5d]	631	1			T6	2		T7	3		T26	1
valid_sources[0x5e]	896	1			T8	1		T26	7		T27	7
valid_sources[0x5f]	929	1			T26	5		T27	3		T28	11
valid_sources[0x60]	695	1			T27	6		T28	17		T71	2
valid_sources[0x61]	610	1			T3	4		T26	12		T27	5
valid_sources[0x62]	812	1			T26	6		T27	4		T28	7
valid_sources[0x63]	861	1			T26	1		T27	9		T45	1
valid_sources[0x64]	628	1			T6	5		T44	2		T26	1
valid_sources[0x65]	752	1			T3	2		T6	2		T7	1
valid_sources[0x66]	946	1			T3	2		T6	12		T44	1
valid_sources[0x67]	975	1			T3	1		T6	4		T7	1
valid_sources[0x68]	627	1			T3	2		T6	3		T26	6
valid_sources[0x69]	795	1			T27	3		T13	8		T28	25
valid_sources[0x6a]	864	1			T3	1		T6	2		T26	1
valid_sources[0x6b]	761	1			T6	5		T22	1		T26	6
valid_sources[0x6c]	681	1			T3	1		T6	1		T7	1
valid_sources[0x6d]	796	1			T6	4		T27	7		T28	29
valid_sources[0x6e]	614	1			T22	1		T27	2		T28	15
valid_sources[0x6f]	777	1			T3	1		T6	1		T26	1
valid_sources[0x70]	757	1			T3	1		T22	1		T27	5
valid_sources[0x71]	718	1			T6	1		T26	1		T27	6
valid_sources[0x72]	627	1			T6	2		T74	2		T25	1
valid_sources[0x73]	1037	1			T6	1		T26	2		T27	13
valid_sources[0x74]	757	1			T27	8		T28	20		T135	4
valid_sources[0x75]	911	1			T26	3		T12	1		T27	7
valid_sources[0x76]	667	1			T6	1		T22	3		T7	1
valid_sources[0x77]	699	1			T6	2		T22	2		T26	10
valid_sources[0x78]	731	1			T26	4		T27	5		T28	7
valid_sources[0x79]	802	1			T3	3		T6	13		T7	1
valid_sources[0x7a]	766	1			T6	4		T22	1		T27	5
valid_sources[0x7b]	604	1			T3	1		T26	6		T27	5
valid_sources[0x7c]	775	1			T3	1		T26	1		T27	4
valid_sources[0x7d]	833	1			T6	2		T22	1		T7	1
valid_sources[0x7e]	906	1			T3	1		T22	1		T7	1
valid_sources[0x7f]	656	1			T3	1		T6	5		T22	2
valid_sources[0x80]	643	1			T3	4		T6	4		T26	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42214

1

T3

24

T6

40

T22

10

values[0x0]

all_enables

biggest_size

57098

1

T1

2

T2

3

T3

16

values[0x1]

all_enables

biggest_size

54661

1

T1

3

T2

1

T3

8