Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13892357

1

T3

26710

T4

654

T5

547

full_word

54897483

1

T1

45056

T2

6142

T3

266826

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68789540	1			T1	45056		T2	6142		T3	293536
auto[TlIntgErrCmd]	102	1			T65	5		T66	6		T67	1
auto[TlIntgErrData]	96	1			T65	5		T66	6		T67	7
auto[TlIntgErrBoth]	102	1			T65	10		T66	8		T67	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31511768

1

T1

22528

T2

2048

T3

143823

auto[1]

37278072

1

T1

22528

T2

4094

T3

149713

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6638163	1			T3	13070		T4	334		T5	264
auto[TlIntgErrNone]	partial	auto[1]	7253911	1			T3	13640		T4	320		T5	283
auto[TlIntgErrNone]	full_word	auto[0]	24873467	1			T1	22528		T2	2048		T3	130753
auto[TlIntgErrNone]	full_word	auto[1]	30023999	1			T1	22528		T2	4094		T3	136073
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T65	2		T66	2		T123	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T65	2		T66	4		T67	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T120	1		T126	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T65	1		T123	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T65	4		T66	2		T67	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T65	1		T66	4		T67	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T123	1		T122	1		T117	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T119	1		T125	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T65	3		T66	2		T67	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T65	6		T66	6		T123	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T65	1		T125	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T128	1		-	-		-	-